JPH03211771A - Conductivity-modulation mosfet - Google Patents

Abstract

PURPOSE:To prevent the concentration of current and latch-up by providing a source layer around a striped drain layer, wherein the drain-source spacing is greater in the edge portions of the striped drain than in the other portions. CONSTITUTION:An n-type base layer and a drain layer 16 in it are formed in a stripe pattern and divided into three parts. A source layer 13 is formed around the base and drain layers. in this striped area, a relation b>a is determined where (a) and (b) are the drain-source spacing in the linear and edge portions of the stripe pattern, respectively. In this conductivity-modulation MOSFET, the lateral distribution of resistor of the n-type base layer is greater in the edge portions than in the linear portions. Therefore, the distribution of hole current in the n-type base layer is substantially uniform although the source layer 13 faced with the drain layer 16 has longer sides in the edge portions. Thus, the concentration of current in the edge portion is reduced compared with the conventional device.

Description

Detailed Description of the Invention [Objective of the Invention] (Industrial Application Field) The present invention relates to a lateral conductive MO: A-type MO in which drain, source and gate electrodes are formed on one side of a semiconductor wafer.
Regarding 5FET.

(Prior Art) A conductivity modulation type MO3FET is a switching element that has a pnpn structure but does not operate in a silica manner, but operates in a bipolar manner under the control of a MOS gate. Among the conduction modulation type MO8FETs, the one in which the pnpn structure is formed laterally on the surface of the 11 conductor wafer is the lateral conduction modulation type M
It is called O5FET.

FIG. 17 is a plan view of an example of such a lateral conductivity modulation type MOSFET, and FIGS. 18(a), (b), and (c)
are A-A', B-B' and c-c in FIG. 20, respectively.
'This is a cross-sectional view. An n-type base layer 14.15 is formed on the surface of the p-type silicon urchin 1111, and a p+-type drain layer 16 is formed within this n-type base layer 14.15. The wafer 11 also has a p-type base layer 12 formed adjacent to the n-type base layer 14.15.
An n'-type source layer 13 is formed within 2. A region sandwiched between the n4 type source layer 13 and the n type base layer 14 is used as a channel region, and a gate electrode 18 is formed thereon via a gate insulating film 17. The source electrode 21 is provided in contact with the p-type base layer 12 at the same time as the source layer 13, and the drain electrode 24 is provided in the drain layer 16.

In order to configure a lateral conductive 7ft modulation type MOSFET as a large current switching element, a long channel width is required. For this reason, as shown in FIG. 17, the n-type base layer 14, 15 and the p+ type drain layer 16 therein are divided into a plurality of stripes and arranged, and the p-type base layer 14 and 15 are arranged to surround them. 12 and n
A + type source layer 13 is formed. Therefore, the gate electrode 18 is formed with a plurality of ring-shaped patterns, as shown by broken lines in FIG. 17, which are drawn out in the longitudinal direction and commonly led to the gate electrode pad (G).

A drain electrode 24 in contact with each drain layer is drawn out to the side opposite to the gate electrode 18 and commonly led to a drain electrode pad (D). The source electrode 21 is disposed to mesh with the drain electrode 18 and is led to the source electrode pad (S). This configuration example can be regarded as three conductive modulation type MO8FET units connected in parallel.

This conductivity is 3! The operation of the J-type MOSFET is as follows.

When a positive bias is applied to the gate electrode 18 with respect to the source electrode 21, the surface of the channel region under the gate electrode 18 is inverted, and electrons are injected from the source layer 13 into the n-type base layer 14. This electron current passes through the n-type base layer 15 and enters the p+-type drain layer 16, turning on the device.

At this time, as a result of forward biasing of the drain junction, holes are injected from the p-type drain layer 16 to the n-type base layer 14 through the n-type base layer 15. As a result, electrons and holes are accumulated in the n-type base layer 14, causing conductivity modulation. Due to the effect of this conductivity modulation, the resistance of the n-type base layer 14 becomes substantially small when it is on, and an extremely small on-voltage can be obtained. The holes injected from the drain layer 16 into the n-type base layer 14 are connected to the p-type base layer 12 and n″
Since the ``type source layer 13 is short-circuited by the source electrode 21, it passes directly under the source layer 13 of the p-type base layer 12 to the source electrode 21. Therefore, the thyristor operation is prevented.The gate electrode 18 is connected to the source electrode 21. When biasing 21 negative or zero, the inversion layer in the channel region disappears and the device turns off.

This conventional conductivity modulation type MOSFET has the following problems.

First, current concentration occurs at the edges of the drain layer having a striped pattern. This is because when forming an n-type source layer that surrounds an n-type base layer and a p-type drain layer therein at equal intervals, which have a striped pattern whose edges form a semicircle, the edges form a semicircle. Focusing on the edge part, the length of the opposing sides of the drain layer and source layer is
This is because the inner drain layer is smaller. Due to this current concentration, element destruction occurs when large current operation is performed.

Second, latch-up is likely to occur at the edge of the drain layer. The hole current from the drain layer 16 passes through the p-type base layer 12 under the source layer 13 to the source electrode 21 as described above.

On the other hand, the source layer 13 is formed continuously surrounding the striped drain layer 16;
In the extraction electrode part up to electrode pad No. 4, source electrode 2
1 is not in contact with the source layer 13 and the p-type base layer 12.

That is, in the edge portion of the stripe, the source layer 13
and p-type base layer 12 are not short-circuited.

For this reason, at the time of large current, the p75 base layer 12
Due to the lateral voltage drop within, the junction between the p-type base layer 12 and the source layer 13 is forward biased and enters thyristor operation. When this latch-up occurs, the gate
Even if the bias between the sources is reduced to zero, the device will not turn off, which will still lead to device destruction.

(Problems to be Solved by the Invention) As described above, in the conventional lateral conductivity modulation MOSFET, there is a problem in that the device is easily destroyed due to current concentration and latch-up at the edge of the drain region of the striped pattern. .

An object of the present invention is to solve such problems and provide a lateral conduction modulation '112M08FET with improved reliability.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a lateral conductivity modulated MO5F in which a source layer is formed surrounding a drain layer having a striped pattern.
The ET is characterized in that the distance between the drain layer and the source layer at the stripe edge portion is larger than that at other regions.

The present invention also provides a lateral conductivity modulation type MOSFET in which a source layer is formed surrounding a drain layer, in which the source layer is divided so that the source layer is not formed under the extraction electrode portions of the gate electrode and the drain electrode. It is characterized by its placement.

These conductivity modulation type MO3FETs use a semiconductor wafer of the same conductivity type as the drain layer, but if the conductivity type of the semiconductor wafer used is reversed, the source layer is formed in an island shape, and the drain layer will surround this.

The present invention is also effective in this structure. In this case, the above-mentioned source and drain may be reversed.

Furthermore, these conductivity modulation type MO9FETs are constructed on one substrate as will be explained later, but when integrating these conductivity modulation type Fv10 SFETs, it is necessary to perform dielectric separation. be. For this purpose, for example, a dielectric isolation wafer formed by bonding another substrate on which an oxide film is formed may be used.

(Function) According to the present invention, the source-drain spacing is not uniform, but the spacing is increased at edge portions such as stripes, thereby suppressing current concentration at the edge portions. Further, by not providing the source layer under the lead-out electrode portions of the gate electrode and drain electrode that cannot be contacted with the source electrode, latch-up occurring in these portions can be prevented. As described above, a highly reliable lateral conduction modulation type MOSFET can be obtained.

(Example) The present invention will be explained in detail below.

FIG. 1 shows the electrode layout of a horizontal conductivity modulation type MO5FET of the first embodiment. FIG. 2 shows the main structure of FIG. 1 together with source and drain diffusion layer patterns. Figures 3(a), (b) and (C) are A-A in Figure 2, respectively.
A', BB' and CC' cross-sectional structures are shown. In these figures, parts corresponding to those in FIGS. 17 and 18 of the conventional example are given the same reference numerals. P type layer 11
．． On the surface of a p-type silicon wafer 11 consisting of a high-resistance p-type layer 11 □, a deep low-resistance n-type layer (drain buffer layer) 15 and a shallower high-resistance low-type layer (drift layer). A plurality of n-type base layers consisting of 14 are formed in an island shape. The silicon wafer 11 is, for example, p”
A p-type silicon substrate may be epitaxially grown with a p-type layer, or a p+-type silicon substrate and a p--type silicon substrate may be directly integrated by a blue bonding technique.

p+ type layer 11. may be an n- or fl' type layer. A p+ type drain layer 16 is formed on the surface of the rl type base layer 14.15. These n-type base layers 14
．． 15 and the drain layer 16, an n-type base layer 12 is formed by diffusion, and an n-type source layer 1 is formed in the n-type base layer 12.
3 is formed by diffusion. A deep n-type layer 19 is diffused into the n-type base layer 12 to lower the lateral resistance, and a p+-type layer 2 is formed on the surface to lower the contact resistance.
0 is formed by diffusion. The n-type base layer 12 inside the n+-type source layer 13, and the p-type silicon layer inside it.
A polycrystalline silicon gate electrode 18 is formed on a region of wafer 11 with a gate oxide film 17 interposed therebetween. Source layer 13. The drain layer 16 has source electrodes 21 . A drain electrode 24 is formed. The source electrode 21 is arranged so as to simultaneously contact the source layer 13 and the p+ type layer 20 outside thereof. Further, a high resistance film 23 as a field plate is provided on the element bone M oxide film 22 between the gate electrode 18 and the drain electrode 42. The high resistance film 23 is, for example, a semi-insulating polycrystalline silicon film.

Briefly explaining the manufacturing process of this conductivity modulation type MO3FET, first, a deep n-type layer 19 is diffused into a silicon wafer 11, an n-type layer 15 is formed inside the deep n-type layer 19, and an n-type layer 15 is formed outside the deep n-type layer 19. Diffusion formation of layer 14. Next, a thick field oxide film 22 is formed over the entire surface of the wafer. Then, the oxide film 22 is selectively etched, and a gate oxide film 17 is formed on the exposed wafer surface by thermal oxidation. Next, a polycrystalline silicon film is deposited, a photoresist pattern defining the source side edge of the gate electrode is formed thereon, and the polycrystalline silicon film is selectively etched. Then, boron ions are implanted through the same opening to form an n-type base layer 12 by diffusion. Thereafter, a photoresist pattern is formed to define the edge of the gate electrode on the drain side, and the excess polycrystalline silicon film on the drain region side is selectively etched to pattern the gate electrode 18. Then, the oxide film in a region extending over a part of the gate electrode 18 from above the drain formation region is selectively etched so that the gate electrode 18 is exposed.
From above the exposed gate electrode 18 to inside the n-type layer 14
The high-resistance film 23 is patterned so as to extend over the region and further to a part of the n-type layer 15 region inside the region. Thereafter, using the gate electrode 18 as part of a mask, the n+ type source layer 1 is
form 3. Next, the high resistance film 23 is used as a part of the mask, and the remaining mask is formed of photoresist.
A p+ type drain layer 16 is provided in the n type base layer, and a p+ type layer 20 for lowering contact resistance is provided in the p type base layer.
Diffusion forms. Then, an insulating film 25 is deposited on the entire surface, contact holes are opened, and a drain electrode 24 and a source electrode 21 are formed.

In this embodiment, the n-type base layers 14, 15 and the drain layer 16 formed therein are divided into three parts in a striped pattern, and the source layer 13 is formed around them. The gate electrode 18, which is shown by broken lines in FIGS. 1 and 2, has an elongated ring shape as shown, and its edge portion forms a semicircle.

FIG. 2 is an enlarged view of one MO3FET unit in FIG. 1, and shows the layout of the source and drain layers overlapping the electrode layout. As is clear from the figure, the drain layer 16 and the source layer The distance between 13 is not uniform. The lead electrode part 18 of the gate electrode 18 is
The distance between the drain and the source at the lead electrode portion 24a1 of the drain electrode 24, that is, the stripe edge portion, is set to aa. Although this structure was not described in detail in the previous explanation of the manufacturing process, it can be obtained as follows. That is, the high resistance film 23 is formed to have a ring-shaped pattern similar to the pattern of the gate electrode 18, partially overlapping the gate If electrode 18, and covering the inside thereof. When doping the drain layer 16 with impurities, the high-resistance film 23 is used as a mask for the straight portions, and a photoresist mask is formed so as to cover the inside of the high-resistance film 23 for the edge portions. As a result, as shown in the cross-sectional views of FIGS. 3(b) and 3(e), a state is obtained in which the drain layer 16 is largely retreated from the edge of the n-type base layer 15 at the striped edge.

Therefore, in the conductivity modulation type MO8FET of this example,
Looking at the distribution of the lateral resistance of the n-type base layer 15, it is found that it is larger at the stripe edges than at the straight portions. As a result, even though the side of the source layer 13 facing the drain layer 16 is long at the stripe edge, the distribution of hole current in the n-type base layer 15 becomes almost uniform. Therefore, a highly reliable conduction modulation type MO3FET can be obtained without causing current concentration at the stripe edge portion as in the conventional case.

FIGS. 4 and 5 are diagrams showing the main structure of the lateral conductivity modulation type MO3FET of the second embodiment, corresponding to FIGS. 2 and 3 of the first embodiment, respectively. In this embodiment, the drain layer 16 is not set back at the stripe edges. Instead, regions 26 and 27 where there is no source layer are provided below this edge portion, that is, the extraction electrode portion 24a of the drain electrode 24 and the extraction electrode portion 18a of the gate electrode]8. In other words, the source layer 13 has two source layers 13 . on both sides of the straight portion of the drain layer 16 . ．． 132 is divided and placed as MOS
A FET unit is configured. An extraction electrode portion 24a and IgB for guiding the drain electrode 24 and gate electrode 18 to their respective electrode pads are laid out so as to pass over the regions 26 and 27 where the source layer is not formed.

According to this embodiment, the source electrode 2 has the gate lead electrode part 18a and the drain lead electrode part 24a.
Since the source layer is not formed in the regions where 1 cannot be contacted, latch-up is prevented from occurring in these regions. Therefore, this embodiment also provides a highly reliable lateral conduction modulation type ~108 FET.

FIGS. 6 and 7 show the main structure of a lateral conduction modulation type MO8FET of the third embodiment. In this example, the first
．． As is clear from the comparison with the structure of the second embodiment, the first
A structure that is a combination of the above embodiment and the second embodiment is adopted.

Therefore, this embodiment also provides a highly reliable conduction modulation type MOSFET i').

FIG. 8 shows the lateral conductivity modulation type MO3FE of the embodiment of S4.
This is the main structure of T. This is a further improved embodiment of the third embodiment. As is clear from a comparison with FIG. 6, in this embodiment, the source layers 13+ and 13 are divided into two.
□ is formed in a striped pattern that approximately corresponds to the straight line portion of the drain layer 16.

According to this embodiment, although the source area is slightly smaller than that of the third embodiment, device destruction due to current concentration or latch-up at the stripe edge portion can be more reliably prevented.

All examples thus far have used p-type silicon wafers. An example using an n-type silicon wafer will be described below. In this case, the relationship between the source and drain is reversed from the layout.

FIG. 9 shows the lateral conductivity modulation type MO3FET of the fifth embodiment.
The electrode layout is shown below. FIG. 10 shows the main structure of FIG. 9 together with source and drain diffusion layer patterns. Figures 11(a), (b) and (c) are respectively 10th
AA', B-8' and c-c' cross-sectional structures in the figure are shown. Also in these figures, the same reference numerals are given to the parts corresponding to those of the previous embodiments. As shown in FIG. 11, in this embodiment, an n+ type layer 311 and a high resistance n- type layer 312
A raw silicon wafer 31 consisting of the following is used.

The n-type base layer 12 is formed into a plurality of islands (three in the figure) with a striped pattern. Then, in the peripheral part of the valley p-type base layer 12, as shown in FIG.
An n"M source layer 13 is formed in a ring shape by diffusion. An n-type base layer 15 is formed surrounding the p!42 base layer 12, and a p'-type drain layer 16 is formed therein. .

The gate electrode 18 is patterned in a ring shape, but unlike the previous embodiments, the extraction electrode portion 18
a is formed of the same metal film as the source electrode 21 and the drain electrode 24.

This is different from the previous embodiments in which the drain to which a high potential is applied is located at the center of the device, but when the gate lead-out electrode part is formed using polycrystalline silicon on a thin oxide film at the same time as the gate electrode. This is because the high potential of the drain easily causes dielectric breakdown at t11. For this reason, as shown in FIGS. 9 and 10, a portion of the source electrode 21 is hollowed out, and a gate lead-out electrode portion 113 is formed on the thick insulating film 25. The extraction electrode portion 18a is connected to a polycrystalline silicon wiring 18b formed at a predetermined distance from the element chain acid and guided to the bonding pad region.

In this embodiment, the stripe edge portion of the n-type base layer 15 formed in a striped pattern is not opposed to the drain layer, that is, the length of the n-type base layer 12 is A striped drain layer 16 divided into two parts so as to face only the sides.
, 16□.

This embodiment also reliably prevents current concentration and latch-up at the stripe edges.

FIGS. 12 and 13 show a lateral conduction modulation type MOS FET of the sixth embodiment, which is a further improvement of the fifth embodiment.
10 and 11 respectively. In this embodiment, in addition to the fifth embodiment, two source layers 1, 3, . ．． It is divided and arranged as 13□.

According to this embodiment, the -layer reliability can be improved.

In the above embodiments, the case where the conductive modulation type MO8FET unit is in the form of a stripe was exclusively explained, but the MOSFE
The present invention is effective even if the T unit has other pattern shapes.

For example, FIGS. 14 and 15 show conduction modulation type MOSF
The electrode layout of the seventh embodiment in which the ET unit is in a square pattern and the source for one of the units,
The layout of the drain layer is shown in Figures 1 and 4, respectively.
It is shown in accordance with the figure.

Further, in the above embodiments, the case where the drain or the source is divided into three parts has been described, but the number of divisions may be two or four or more. Furthermore, if the 7H current capacity is relatively small, there is no need to divide it into a plurality of units, and the present invention is effective even in such a case.

Furthermore, for the above δ embodiment, FIGS. 16(a) to (C
) The present invention is also effective when an element structure such as the one shown in FIG. In FIG. 16(a), the n-type base layer 15 is exposed on a part of the surface of the drain layer 16, and this is connected to the drain electrode 24 through the n+-type layer 41 to form a so-called anode short structure. . FIG. 16 (a>, n
Although the ``'' type layer 41 is formed shallower than the drain layer 16, FIG. 16(b) shows the case where the n'' type layer 41 is formed deeper than the drain layer 16. FIG. It has a double gate structure in which a gate electrode 43 is provided not only on the side but also on the drain side with a gate insulation 11% 42 interposed therebetween.

[Effect of the invention] According to the present invention as explained above, the sauce.

By improving the layout of the drain diffusion layer,
Horizontal conduction modulation type MO8FET that suppresses current concentration and latch-up and improves reliability! 2 can be done.

[Brief explanation of drawings]

FIG. 1 shows a conductive bag type MO3FE according to the first embodiment of the present invention.
FIG. 2 is a partially enlarged view showing the electrode layout along with the source and drain layers. FIGS. -A'B-B' and c-c' sectional views, Figure 4 is the 2nd
5(a), (b) and (C) are A-A'BB' and c-c' of FIG. 4, respectively. The cross-sectional view, FIG. 6 is a view showing the main structure of the third embodiment in correspondence with FIG. 2, and FIGS. BB' and c-c' cross-sectional views, FIG. 8 is a diagram showing the main structure of the fourth embodiment corresponding to FIG. 2, and FIG. 9 is a diagram showing the electrode layout of the fifth embodiment. 1. FIG. 10 is a partially enlarged view showing the source and drain layers as well as the electrode layout. FIGS. 11(a), (b) and (c) are the 10th
AA', BB' and c-c' sectional views of the figure, 1st
2 is a diagram showing the main structure of the sixth embodiment in correspondence with FIG. 10, and FIGS.
AA', BB' and c-c' sectional views of the figure, 1st
Figure 4 is a diagram showing the electrode layout of the lateral conductivity modulation type MO5FET of the seventh embodiment, Figure 15 is a partially enlarged diagram showing the electrode layout along with the source and drain layers, and Figures 16 (a) to 4. (c) is a diagram showing the device structure of yet another embodiment, Figure 17 is a diagram showing the electrode layout of a conventional lateral conduction modulation type MO3FET, and Figures 18 (a), (b), and (c) are respectively 17
They are AA', BB', and CC' cross-sectional views of the figure. 11... High resistance p-type silicon sea urchin l, 12...
・P-type base layer, 13...n" type source layer, 14...
・High resistance n-type base layer, ]5...Low resistance n-type base layer, 16...p+ type drain layer, 17...gate insulating film, 18...gate electrode, 18a...gate Extraction electrode part, 19...p type layer, 20...p+ type layer, 2
DESCRIPTION OF SYMBOLS 1... Source electrode, 22... Insulating film, 23... High resistance film, 24... Drain electrode, 24B... Drain extraction electrode part, 25... Insulating film, 31... High Resistance n-type silicon wafer.

Claims (11)

[Claims] (1) a semiconductor wafer having a high resistance layer of a first conductivity type on a surface portion; a base layer of a second conductivity type formed with a striped pattern on the high resistance layer; and a base layer of a second conductivity type formed in a striped pattern on the high resistance layer; a first conductivity type base layer formed to surround the type base layer at a predetermined distance; and a gate insulating film formed on a channel region spanning from a peripheral portion of the first conductivity type base layer to the high resistance layer. a gate electrode having a ring-shaped pattern formed on the first conductivity type base layer, a second conductivity type source layer formed on the first conductivity type base layer in a self-aligned manner with the gate electrode, and a stripe formed on the second conductivity type base layer. A first conductive layer is formed with a shape pattern, and the distance of its longitudinal edge facing the second conductive type source layer is set to be larger than the distance of its longitudinal edge facing the second conductive type source layer. type drain layer; a source electrode disposed in simultaneous contact with the source layer and the first conductivity type base layer; and a drain electrode disposed in contact with the drain layer. Conductivity modulation type MOSFET. (2) a semiconductor wafer having a high resistance layer of a first conductivity type on a surface portion; a base layer of a second conductivity type formed with a predetermined pattern on the high resistance layer; and a base layer of the second conductivity type formed on the high resistance layer; a first conductivity type base layer formed to surround the base layer at a predetermined distance; a first conductivity type drain layer formed within the second conductivity type base layer; and within the first conductivity type base layer. a second conductivity type source layer formed by being divided so as to sandwich the second conductivity type base layer; and a gate formed on a channel region spanning from a peripheral portion of the first conductivity type base layer to the high resistance layer. a gate electrode formed in a ring-shaped pattern through an insulating film and having an extraction electrode portion passing over a region where the second conductivity type source layer is not in contact with the source layer and the first conductivity type base layer at the same time; and a drain electrode having an extraction electrode portion disposed in contact with the drain layer and passing over a region where the second conductivity type source layer is not provided. Conductivity modulation type MOSFET. (3) a semiconductor wafer having a high resistance layer of a first conductivity type on a surface portion; a base layer of a second conductivity type formed with a striped pattern on the high resistance layer; and a base layer of a second conductivity type formed in a striped pattern on the high resistance layer; a first conductivity type base layer formed to surround the type base layer at a predetermined distance; a first conductivity type drain layer formed in a striped pattern in the second conductivity type base layer; A second conductive type source layer is formed in the conductive type base layer so as to be divided so as to face the two long sides of the second conductive type base layer; a gate electrode formed in a ring-shaped pattern on a channel region extending over a high-resistance layer through a gate insulating film and having an extraction electrode portion passing over a region where the second conductivity type source layer is not provided; and the source layer; A source electrode disposed in simultaneous contact with the first conductivity type base layer, and an extraction electrode portion disposed in contact with the drain layer and passing over a region where the second conductivity type source layer is not present. A conductivity modulation type MOSFET characterized by having a drain electrode. (4) The second conductivity type base layer is divided into a plurality of parts, each of which includes a deeply diffused low-resistance base layer and a shallowly diffused high-resistance base layer outside the low-resistance base layer. 4. The conductivity modulation type MOSFET according to claim 1, wherein the conductivity modulation type MOSFET is comprised of a layer. (5) A high-resistance film formed on the second conductivity type base layer and the high-resistance layer outside thereof via an insulating film, one end of which is connected to the drain electrode and the other end of which is connected to the gate electrode. The conductivity modulation type MOSFET according to any one of claims 1, 2 and 3, comprising: (6) The second conductive type base layer is partially exposed on the surface within the drain layer region, and the drain electrode is in contact with the exposed second conductive type base layer.
or 3. The conductivity modulation type MOSFET according to any one of 3. (7) a semiconductor wafer having a high resistance layer of a first conductivity type on a surface portion; a base layer of a second conductivity type formed with a predetermined pattern on the high resistance layer; and a base layer of a second conductivity type formed on the high resistance layer; a first conductivity type base layer formed to surround the second conductivity type base layer at a predetermined interval with respect to the base layer; and a ring-shaped pattern formed in the second conductivity type base layer. a first conductivity type source layer; and a second conductivity type source layer within the first conductivity type base layer;
a second conductivity type drain layer surrounding the conductivity type base layer and having at least one isolation region; and a gate formed on a channel region extending from the peripheral part of the second conductivity type base layer to the high resistance layer. a gate electrode formed in a ring-shaped pattern through an insulating film and having an extraction electrode portion passing over the separation region; and a gate electrode disposed in simultaneous contact with the first conductivity type source layer and the second conductivity type base layer. A conductivity modulation type MOSFET further comprising: a source electrode having an extraction electrode portion passing over the separation region; and a drain electrode disposed in contact with the second conductivity type drain layer. (8) a semiconductor wafer having a high resistance layer of a first conductivity type on a surface portion; a base layer of a second conductivity type formed in a striped pattern on the high resistance layer; and a base layer of a second conductivity type formed in a striped pattern on the high resistance layer; a first conductive type base layer formed to surround the second conductive type base layer at a predetermined interval with respect to the mold base layer; and a first conductive type base layer formed on the first conductive type base layer and said second conductive type base layer. The second layer is divided and placed so as to face each of the two long sides of the layer.
a conductive type drain layer; a first conductive type source layer formed with two striped patterns in the second conductive type base layer; and a channel extending from a peripheral portion of the second conductive type base layer to the high resistance layer. a gate electrode having a ring-shaped pattern formed on the region via a gate insulating film; a source electrode disposed in simultaneous contact with the first conductivity type source layer and the second conductivity type base layer; A conductivity modulation type MOSFET comprising: a drain electrode disposed in contact with the second conductivity type drain layer. (9) The conductivity modulation type MOSFET according to claim 7 or 8, wherein the second conductivity type base layer is divided into a plurality of pieces and arranged. (10) A high resistance film formed on the first conductivity type base layer and the high resistance layer inside thereof via an insulating film, one end of which is connected to the drain electrode, and the other end of which is connected to the gate electrode. The conductivity modulation type MOSFET according to claim 7 or 8, having the following. (11) Any one of claims 7 and 8, wherein the first conductivity type base layer is partially exposed on the surface within the drain layer region, and the drain electrode is in contact with the exposed first conductivity type base layer. The conductivity modulation type MOSFET described in .