JP2001053276A - Forming method of vertical semiconductor device with increased source contact area - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a vertical MOS device increased in contact area between a source and a source electrode so as to improve the performance. SOLUTION: An oxide layer is etched, by which a first oxide spacer 108 is left on a substrate adjacent to the gate polysilicon layer 112, the gate polysilicon layer 112 and the source region 106 of the substrate are selectively etched using a nitride layer or the like deposited on the oxide spacer 108 as a mask, and a recess 117 which includes a vertical plane and a horizontal plane is formed adjacent to the source region 106. A first conductivity dopant is injected and implanted into the recess 117 adjacent to the source region 106, by which a shallow emitter region 114 is formed in a well region 105 under the recess 117. The nitride layer or the like used as a mask is removed by etching, conductive material layers 117 and 116 are deposited on the residual part of the gate polysilicon layer 112, the source region 106, and the emitter region 114. With this setup, a contact surface between a source region and a conductive material can be improved in area by the recess 117.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
More specifically, a vertical D having an increased source contact area
The present invention relates to a method for forming a MOS device.

[0002]

U.S. Pat. No. 4,960,723 discloses a silicon nitride sidewall spacer formed around a polysilicon gate and an oxide covering the nitride sidewall spacer. Disclosed is a method of manufacturing a self-aligned vertical field effect transistor that forms a spacer. Using the oxide spacer as a mask, a portion of the source is etched to expose a portion of the silicon substrate, and then the oxide spacer is removed. Thereby, the contact area between the source and the source electrode increases.

US Pat. No. 5,498,555 includes a first spacer element made of polysilicon on vertical sidewalls of a gate electrode, and a second spacer element made of silicon dioxide on the first spacer element. Horizontal type F equipped
A method for manufacturing ET is disclosed. The purpose of this manufacturing method is to improve performance and provide resistance to the thermal carrier effect.

US Pat. No. 5,208,472 discloses a horizontal MOS device having two dielectric films on the edge of the gate. This device is aimed at reducing junction leakage and reducing gate to source / drain shorts.

US Pat. No. 5,663,079 discloses a method for manufacturing a MOS gate double diffused semiconductor device. According to one embodiment, a nitride spacer layer is used to separate the implanted and diffused deep body region from the gate region and then perform an etch away.

US Pat. No. 5,668,065 discloses a method for simultaneously forming a silicide-based self-aligned contact and a local interconnect in a horizontal semiconductor device. An oxide spacer adjacent the gate forms a lightly doped drain region within the drain region adjacent the gate and separates the gate from a later formed self-aligned source region contact. U.S. Pat. No. 5,702,972 discloses a method for reducing source / drain resistance in the processing of a horizontal semiconductor device, in which a first spacer made of oxide is formed on a side wall of a gate electrode and nitrided. A method of forming a second spacer made of a material on the first spacer is disclosed. After implantation of the highly doped source / drain regions, the second spacer is removed.

[0007]

According to the present invention, there is provided a method of forming a vertical semiconductor device having an increased source contact area, comprising the steps of: (a) depositing a poly-silicon substrate on a silicon substrate; Forming a gate including a silicon layer;
(B) implanting and implanting a first conductivity type dopant into the substrate to form a well region in the substrate; and (c) implanting and implanting a second conductivity type dopant into the well region. Forming a shallow source region in the well region; (d) depositing a first oxide layer on the gate and on the source region and the well region in the substrate; and (e) forming the first oxide layer. Selectively etching a material layer to form a first oxide spacer on the substrate adjacent to the gate; and (f) thin nitride on the gate and on the source region in the substrate. Depositing a layer; and (g) depositing a second oxide layer on the thin nitride layer;
(H) selectively etching the second oxide layer to form a second oxide spacer, wherein the second oxide spacer is separated from the first oxide spacer and the substrate by the thin nitride layer. (I) selectively plasma etching the polysilicon layer at the gate and the source region at the substrate using the oxide spacer and the nitride spacer as a mask, Including a plane substantially perpendicular to and horizontal to the source region by removing a nitride layer from the gate and the substrate, a portion of the polysilicon layer from the gate, and a portion of the source region. Forming a recess, and (j) injecting and implanting a first conductivity type dopant into the recess in the source region to form the recess. Forming a shallow emitter region in said well region located below; and (k) forming said second oxide spacer and said thin nitride layer separating said second oxide spacer from said first oxide spacer. Removing the second oxide spacer and the thin nitride layer by selectively etching; and (l) forming a conductive material layer on the remaining polysilicon layer and the source region. And thereby increasing the contact area with the conductive material by the recess in the source region.

[0008] Advantageously, a method of forming a vertical semiconductor device having an increased source contact area comprises forming a gate on a silicon substrate, the gate including a polysilicon layer deposited on an oxide layer. Implanting and implanting one conductivity type dopant into the substrate to form a well region in the substrate. A shallow source region is formed in the well region by implanting and implanting a second conductivity type dopant into the well region. A first oxide layer is deposited on the gate and on the source and well regions of the substrate. The first oxide layer is etched to form a first oxide spacer on the substrate adjacent to the gate.

A thin nitride layer is deposited on the gate and on the source region on the substrate, and a second oxide layer is deposited on the thin nitride layer. The second oxide layer is etched to form a second oxide spacer. The second oxide spacer is separated from the first oxide spacer and the substrate by the thin nitride layer. Using the oxide spacers and nitride spacers as masks, selectively etch the polysilicon layer at the gate and the source region at the substrate to remove the thin nitride layer from the gate and the substrate. By removing a portion of the gate polysilicon layer and a portion of the source region, a recess is formed that includes a surface substantially perpendicular and horizontal to the source region.

A shallow emitter region is formed in the well region below the recess in the source region by implanting and implanting a first conductivity type dopant into the recess in the source region. The second oxide spacer and the thin nitride layer separating the second oxide spacer from the first oxide spacer are removed by etching, and a conductive material layer is formed on the remaining polysilicon layer and the source region. To be deposited. Due to the recess in this source region,
The contact area with the conductive material increases.

Conveniently, a method for forming a vertical semiconductor device having an increased source contact area comprises forming a gate on a silicon substrate, the gate including a polysilicon layer deposited on an oxide layer; Implanting and implanting a first conductivity type dopant into the substrate to form a well region in the substrate. A shallow source region is formed in the well region by implanting and implanting a second conductivity type dopant into the well region, and an oxide layer is deposited on the gate and on the source region and the well region in the substrate. Let it. The oxide layer is etched to form a first spacer of oxide on the substrate adjacent the gate.

Depositing and etching a nitride layer on the gate and on the source region on the substrate,
A nitride spacer is formed adjacent to the oxide spacer. Using the oxide spacers and the nitride spacers as masks, selectively etch the polysilicon layer in the gate and the source region in the substrate to form a portion of the gate polysilicon layer and the source region. By removing a portion, a recess is formed in the source region that includes a substantially vertical surface and a horizontal surface.

A shallow emitter region is formed in the well region below the recess in the source region by implanting and implanting a first conductivity type dopant into the recess in the source region. The nitride spacer is removed by etching, and a conductive material layer is deposited on the remaining polysilicon layer and on the source region. The contact area with the conductive material increases due to the recess in the source region.

A highly doped source region in a vertical semiconductor device manufactured by the manufacturing method of the present invention includes a vertical component and a horizontal component, and is characterized by an increased source contact area realizing improved I-off capability. I have.

[0015]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

Increasing the source contact area to lower the drain / source resistance in a vertical semiconductor device is as follows.
This is achieved by forming a horizontal contact surface and a vertical contact surface in the source region using a plurality of spacers according to the manufacturing method of the present invention. One embodiment of the method is illustrated in FIGS.
Shown in Although the device shown is a MOS controlled thyristor, the method of the present invention is also useful for processing other devices such as, for example, MOSFETs and insulated gate bipolar transistors (IGBTs).

Hereinafter, the first conductivity type dopant and the second conductivity type dopant will be described. When the first conductivity type dopant is P, the second conductivity type dopant is N, and conversely, when the first conductivity type dopant is N,
The second conductivity type dopant is P.

As shown in FIG. 1, a polysilicon layer 101 deposited on a thin gate oxide layer 102 grown on a silicon substrate 103 is patterned using a photoresist mask M. The mask M is removed, and an upper base region 104 is formed by implanting and implanting a second conductivity type dopant into the substrate 103 as shown in FIG. M
If the processing of the OSFET is desired, the upper base region 1
04 is omitted.

FIG. 3 shows the formation of the well region 105 by injecting and implanting a first conductivity type dopant into the upper base region 104. Next, a shallow source region 106 is formed by implanting and implanting a second conductivity type dopant into well region 105, and an oxide layer 107 is deposited over the entire structure, as shown in FIG. Oxide layer 10
7 is etched to form spacers 108 adjacent to polysilicon layer 101, as shown in FIG.

As shown in FIG. 6, a thin silicon nitride layer 109 is deposited on the structure. Layer 109 protects spacer 108 from further etching. As shown in FIG. 7, a second oxide layer 110 is deposited on the nitride layer 109. Next, as shown in FIG. 8, the second spacer 111 is formed by etching the oxide layer.

As shown in FIG. 9, not only a part of the polysilicon layer 101 is removed by plasma etching (leaving the gate polysilicon 112) but also a nitride layer 109 is formed.
, The thin nitride spacer 113 leaves only the portion between the spacers 108 and 111. As shown in FIG. 10, an emitter region 114 is formed by implanting and implanting a first conductivity type dopant into the well region 105 to a shallow depth.

The oxide spacer 1 is selectively etched.
After removing the thin nitride spacer 11 and the thin nitride spacer 113, a conductive material layer 115 is deposited on the structure as shown in FIG.
The conductive material of layer 115 can be formed from metals such as titanium, platinum, cobalt and tungsten, silicides of these metals, and mixtures of metals with their corresponding silicides.

Layer 1 shown as containing titanium
15 is silicified to match gate polysilicon 112 and source / emitter regions 106/114 to form titanium silicide gate contacts 116 and source contacts 117, respectively, as shown in FIG.
Source contact 117 includes both horizontal and vertical components, which increases the contact area and is beneficial for I-off capability.

FIGS. 13 to 24 show a second embodiment of the method of the present invention. The steps shown in FIGS. 13 to 17 are the same as the steps shown in FIGS. 1 to 5 for the first embodiment.

FIG. 18 shows the deposition of a nitride layer 201 on the structure. This nitride layer 201 is etched to form a second spacer 202 as shown in FIG. As shown in FIG. 20, a part of the polysilicon layer 101 is removed by plasma etching to remove the gate polysilicon 1.
12 and a part of the source region 106 is removed to form a recess 203. Next, as shown in FIG. 21, an emitter region 114 is formed in the well region 105 by implanting a first conductivity type dopant into the concave portion 203 and implanting it into a shallow depth.

As shown in FIG. 22, the second spacer 202 is removed by etching. Deposition of conductive material layer 115, gate contact 116 and source contact 11
The formation of 7 is shown in FIGS. These are the same as the steps shown in FIGS. 11 and 12 for the first embodiment of the method of the present invention.

The vertical semiconductor device manufactured by the method of the present invention is characterized in that the source contact area can be increased as desired at the peak seed concentration. The increase in the contact area improves the continuity of the source contact silicide, and thus increases the turn-off capability.

The method of the present invention has substantial advantages over known methods using nitride spacers adjacent to the gate. Since nitrides have much higher stress levels than oxides, they are particularly easy to form trap sites. High interface levels of nitride to silicon can cause current leakage from the gate, resulting in significant degradation of device performance. Furthermore, nitride deposition and removal by etching is slower than the corresponding operation with oxides, especially compared to embodiments of the invention in which a thin nitride layer is used deposited only between two oxide spacers. As a result, the time and cost for processing the device increase.

A method for forming a vertical semiconductor device having an increased source contact area includes forming a gate on a silicon substrate by depositing a polysilicon layer on an oxide layer; Forming a well region in the substrate by implanting and driving into the substrate. A shallow source region is formed in the well region by implanting and implanting a second conductivity type dopant into the well region, and a first oxide layer is deposited on the gate and on the source and well regions in the substrate. Let it. The first oxide layer is etched to form a first oxide spacer on the substrate adjacent the gate. Depositing a thin nitride layer on the gate and on the source region in the substrate;
A second oxide layer is deposited on the thin nitride layer. The second oxide layer is etched to form a first oxide spacer and a second oxide spacer separated from the substrate by the thin nitride layer. Using the oxide spacers and the nitride spacers as masks, selectively etch the polysilicon layer at the gate and the source region at the substrate from the gate and substrate to a thin nitride layer, a portion of the gate polysilicon layer and the By removing a part of the source region, a concave portion including a substantially vertical surface and a horizontal surface is formed in the source region. A first conductivity type dopant is implanted and implanted into the recess in the source region to form a shallow emitter region in the well region located below the recess in the source region. The second oxide spacer and the thin nitride layer separating the second oxide spacer from the first oxide spacer are removed by etching, and the conductive material layer is removed on the remaining polysilicon layer and on the source region. To be deposited. The contact area with the conductive material increases due to the recess in the source region.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing the steps in one embodiment of the method of the present invention.

FIG. 2 is a schematic diagram showing steps in one embodiment of the method of the present invention.

FIG. 3 is a schematic diagram showing steps in one embodiment of the method of the present invention.

FIG. 4 is a schematic diagram showing steps in one embodiment of the method of the present invention.

FIG. 5 is a schematic diagram showing the steps in one embodiment of the method of the present invention.

FIG. 6 is a schematic diagram showing the steps in one embodiment of the method of the present invention.

FIG. 7 is a schematic diagram showing steps in one embodiment of the method of the present invention.

FIG. 8 is a schematic diagram showing steps in one embodiment of the method of the present invention.

FIG. 9 is a schematic diagram showing steps in one embodiment of the method of the present invention.

FIG. 10 is a schematic diagram showing steps in one embodiment of the method of the present invention.

FIG. 11 is a schematic diagram showing steps in one embodiment of the method of the present invention.

FIG. 12 is a schematic diagram showing steps in one embodiment of the method of the present invention.

FIG. 13 is a schematic diagram showing steps in a second embodiment of the method of the present invention.

FIG. 14 is a schematic diagram showing steps in a second embodiment of the method of the present invention.

FIG. 15 is a schematic diagram showing steps in a second embodiment of the method of the present invention.

FIG. 16 is a schematic diagram showing steps in a second embodiment of the method of the present invention.

FIG. 17 is a schematic view showing steps in a second embodiment of the method of the present invention.

FIG. 18 is a schematic diagram showing steps in a second embodiment of the method of the present invention.

FIG. 19 is a schematic diagram showing steps in a second embodiment of the method of the present invention.

FIG. 20 is a schematic view showing steps in a second embodiment of the method of the present invention.

FIG. 21 is a schematic diagram showing steps in a second embodiment of the method of the present invention.

FIG. 22 is a schematic view showing the steps in the second embodiment of the method of the present invention.

FIG. 23 is a schematic view showing steps in a second embodiment of the method of the present invention.

FIG. 24 is a schematic view showing steps in a second embodiment of the method of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Polysilicon layer 102 Thin gate oxide layer 103 Silicon substrate 104 Upper base region 105 Well region 106 Shallow source region 107 Oxide layer 108 Spacer 109 Thin silicon nitride layer 110 Second oxide layer 111 Second spacer 112 Gate polysilicon 113 Thin nitride spacer 114 Emitter region 115 Conductive material layer 116 Gate contact 117 Source contact 201 Nitride layer 202 Second spacer 203 Depression M Photoresist

Claims (10)

[Claims] 1. A method of forming a vertical semiconductor device having an increased source contact area, comprising: (a) forming a gate on a silicon substrate, the gate including a polysilicon layer deposited on an oxide layer; (B) implanting and implanting a first conductivity type dopant into the substrate to form a well region in the substrate; and (c) implanting and implanting a second conductivity type dopant into the well region. Forming a shallow source region in the well region; (d) depositing a first oxide layer on the gate and on the source region and the well region in the substrate; Selectively etching an oxide layer to form a first oxide spacer on the substrate adjacent to the gate; and (f) forming a first oxide spacer on the gate and in the substrate. Depositing a thin nitride layer on the source region; (g) depositing a second oxide layer on the thin nitride layer; and (h) selectively etching the second oxide layer. Forming a second oxide spacer, wherein the second oxide spacer is separated from the first oxide spacer and the substrate by the thin nitride layer; and The thin nitride layer is removed from the gate and the substrate by selectively plasma etching the polysilicon layer at the gate and the source region at the substrate using the nitride spacer as a mask. By removing a portion of the layer from the gate and a portion of the source region, a recess including a plane substantially perpendicular and horizontal to the source region is formed. (J) implanting and implanting a first conductivity type dopant into the recess in the source region to form a shallow emitter region in the well region located below the recess; (k) The second oxide spacer and the thin nitride layer are removed by selectively etching the second oxide spacer and the thin nitride layer separating the second oxide spacer from the first oxide spacer. And (l) forming a conductive material layer on the remaining polysilicon layer and on the source region, thereby increasing a contact area with the conductive material by the concave portion of the source region. A method comprising: 2. A step of forming an upper base region in the substrate by injecting and implanting a second conductivity type dopant into the substrate following the gate forming step (a),
The method of claim 1, wherein the first conductivity type is P and the second conductivity type is N. 3. The method according to claim 2, wherein the conductive material is titanium metal, platinum metal,
The method of claim 1, wherein the metal is selected from the group consisting of cobalt metal and tungsten metal, a corresponding silicide of the metal, and a mixture of the metal and the corresponding silicide. 4. The method of claim 1, wherein said conductive material is selected from the group consisting of titanium, titanium silicide, and mixtures thereof. 5. The semiconductor device according to claim 5, wherein the vertical semiconductor device is a MOSFET,
The method of claim 1, wherein the method is selected from the group consisting of a MOS controlled thyristor and an insulated gate bipolar transistor. 6. A method of forming a vertical semiconductor device having an increased source contact area, comprising: (a) forming a gate on a silicon substrate, the gate including a polysilicon layer deposited on an oxide layer; (B) implanting and implanting a first conductivity type dopant into the substrate to form a well region in the substrate; and (c) implanting and implanting a second conductivity type dopant into the well region. Forming a shallow source region in the well region; (d) depositing an oxide layer on the gate and on the source region and the well region in the substrate; and (e) depositing an oxide layer. Selectively etching to form an oxide spacer on the substrate adjacent to the gate; and (f) on the gate and on the source region in the substrate. Depositing a nitride layer; (g) selectively etching the nitride layer to form a nitride spacer adjacent to the oxide spacer; and (h) depositing the oxide layer and the nitride layer. Using the nitride layer as a mask, the polysilicon layer in the gate and the source region in the substrate are selectively plasma etched to remove a portion of the polysilicon layer from the gate and a portion of the source region. Removing to form a recess including a substantially vertical and horizontal surface in the source region; and (i) implanting and implanting a first conductivity type dopant into the recess in the source region. Forming a shallow emitter region in the well region located below the recess; and (j) selectively etching the nitride spacer. Removing the second nitride spacer; and (k) forming a conductive material layer on the remaining polysilicon layer and on the source region, whereby the conductive layer is formed by the recess in the source region. A method characterized by increasing the contact area with a material. 7. A step of forming an upper base region in the substrate by injecting and implanting a second conductivity type dopant into the substrate following the gate forming step (a),
The method of claim 6, wherein the first conductivity type is P and the second conductivity type is N. 8. The method according to claim 1, wherein the conductive material is titanium metal, platinum metal,
7. The method of claim 6, wherein the method is selected from the group consisting of cobalt metal and tungsten metal, a corresponding silicide of the metal, and a mixture of the metal and the corresponding silicide. 9. The method according to claim 8, wherein said conductive material is selected from the group consisting of titanium, titanium silicide and mixtures thereof. 10. The vertical semiconductor device is a MOSFE.
The method of claim 7, wherein the method is selected from the group consisting of T, MOS controlled thyristor, and insulated gate bipolar transistor.