JPH0324737A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a small-sized vertical type MOS transistor whose ON resistance is small, by forming a side wall of highly-doped polycrystalline silicon via an insulating film, on the side wall of a gate electrode, and forming a source region on said side wall in the self alignment manner. CONSTITUTION:A side wall 27 of highly-doped polycrystalline silicon is formed on the side wall of a gate electrode 20 via an insulating film 24, and a source region 31 is formed on said side wall 27, in the self alignment manner. As a result, the margin for position deviation is not required; further the contact area is large since the source region 31 exists just under the side wall 27; further the side wall 27 also acts as a contact. Thereby a small-sized vertical type MOS transistor whose ON resistance is small can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to miniaturization of vertical MOS transistors.

(Prior art) As a conventional vertical MOS transistor, 11, for example, 7th
As shown in the figure, an n-type epitaxial layer 2 is formed on a highly impurity-concentrated n-type silicon substrate 1 that serves as a drain, and a gate insulating film 3 is formed on the surface of the n-type epitaxial layer 2. A gate electrode 4, a p-well 7 formed in the n-type epitaxial layer 2 in a region corresponding to the outside of the gate electrode 4, an n+ region 12 forming a source formed in the p-well 7, and the p-well 7. There is one that is composed of a p+ region 13 for making contact with the well 7.

Here, 5 is a silicon oxide film covering the surface of the gate electrode 4, 14 is an interlayer insulating film, and 16 is a source electrode wiring layer.

By the way, such a vertical MOS transistor is usually formed as follows.

First, as shown in FIG. 8(a), an epitaxial layer 2 with a low impurity concentration is formed on an n-type silicon substrate 1 with a high impurity concentration.
form.

Next, as shown in FIG. 8(b), after forming a silicon oxide film as the gate oxide film 3, a polycrystalline silicon film 4 is formed by CVD.

Then, as shown in FIG. 8(C), the silicon oxide film 3 and the polycrystalline silicon film are patterned using photolithography to form a gate electrode pattern and windows 6 for impurity diffusion. After that, a silicon oxide film 5 is formed on the surface.

Thereafter, as shown in FIG. 8(d), boron ions are implanted into the entire surface and heat treatment is performed to diffuse the boron into the substrate through the window 6 to form a p-well 7.

Then, as shown in FIG. 8(e), a first resist pattern 9 is formed using a photolithography technique, and phosphorus ions 8 are implanted only into the periphery of the window 6. Then, as shown in FIG.

Further, as shown in FIG. 8('), after removing the first resist pattern 9, a second resist pattern 10 having a window is formed in a region corresponding to the center of the window 6, and this window is 1l of boron ions only in the area corresponding to the center of 6
ion implantation.

Then, as shown in FIG. 8(g), a PSG film 14 as an interlayer insulating film is formed.

Thereafter, as shown in FIG. 8(h), heat treatment is performed to diffuse phosphorus ions 8 and boron ions 11, and to form an n+ region 12 as a source and a p-well contact as a p-well contact.
Ten regions 13 are formed.

Thereafter, as shown in FIG. 8(1), the contact window 15 of the source electrode is
form.

Finally, as shown in FIG. 8 (D), a source electrode wiring 16 made of an aluminum-silicon layer is formed.

In the conventional vertical MOS transistor formed in this manner, the patterns of the n+ region 12 as the source, the p+ region 13 as the p-well contact, and the source electrode contact window 15 are all similar to that of the gate electrode 4. Align the position and form the pattern.

Incidentally, there is a growing demand for miniaturization of such vertical MOS transistors, and in particular, it is said that miniaturization is necessary to reduce the on-resistance.

However, for the reasons mentioned above, in conventional vertical MOS transistors, it is necessary to have enough pattern margin to tolerate misalignment. It was the cause.

Furthermore, as the horizontal pattern size is made smaller, the contact area between the n0 region 12 as a source and the source electrode wiring 16 becomes smaller, and the contact resistance increases, so even with miniaturization, the on-resistance increases. The problem was that it did not become smaller.

Furthermore, since the region where the n+ region 12 as a source is formed is the periphery of the bottom of the contact window of the source electrode wiring 16, especially when aluminum-silicon is used for the source electrode wiring 16, the silicon in the aluminum-silicon There is a problem in that contact resistance tends to increase due to in-phase epitaxial growth. This is considered to be because this region is a triple point of aluminum-silicon, silicon oxide, and lithium silicon, where solid phase bitaxial growth is likely to occur.

(Problems to be Solved by the Invention) As described above, conventional vertical MOS transistors have a problem in that miniaturization is difficult due to an increase in on-resistance.

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a vertical MOS transistor that is small in size and has low on-resistance.

[Structure of the invention]

(Means for solving the problem) Therefore, in the present invention, in a vertical MOS transistor,
A sidewall made of highly doped polycrystalline silicon is formed on the sidewall of the gate electrode via an insulating film.
A source region is formed in this sidewall in a self-aligned manner.

In addition, after forming a sidewall made of highly doped polycrystalline silicon on the sidewall of the gate electrode via an insulating film, impurities for forming a source region are implanted using the polycrystalline silicon as a diffusion source. It's straining.

(Function) With the above configuration, a sidewall made of highly doped polycrystalline silicon is formed on the sidewall of the gate electrode via an insulating film, and a source region is formed in a self-aligned manner on this sidewall. , there is no need to allow for misalignment, the source region exists directly under the sidewall, the contact area is large, and the sidewall of the sidewall also acts as a contact, making it possible to create a vertical MOS transistor that is small and has low on-resistance. It becomes possible to obtain.

Furthermore, according to the above method, since the polycrystalline silicon of the sidewall is used as a diffusion source to implant impurities for forming the source region, it is extremely easy to form the source region in a self-aligned manner on the sidewall. This makes it possible to obtain a vertical MOS transistor that is compact and has low on-resistance.

(Example) Hereinafter, a first example of the present invention will be described in detail with reference to the drawings.

This vertical MOS transistor, as shown in FIG.
A sidewall 27 made of highly concentrated polycrystalline silicon is formed on the sidewall of the gate electrode 20 via a sidewall insulating film 24, and the n+ region 31, which becomes the source, is in sufficient contact with the bottom of the sidewall 27. The rest is exactly the same as the conventional example.

In other words, an n-type silicon substrate with a concentration of approximately 1015CI1-3 formed on a high impurity concentration n-type silicon substrate 17 which becomes a drain.
type epitaxial layer 18 and the n type epitaxial layer 1
A gate electrode 20 is formed on the surface of 8 with a gate insulating film 19 interposed therebetween, and a p-well 2 is formed in the n-type epitaxial layer 18 in a region corresponding to the outside of this gate electrode 20.
5 and an n source formed in this p well 25.
There is one constructed of a ten region 31 and a p ten region 30 for making contact with the p well 25.

Here, 21 is a silicon oxide film covering the surface of the gate electrode 20, 22 is a silicon nitride film, and 32 is a source electrode wiring layer.

Next, a method for manufacturing this vertical MOS transistor will be explained.

First, as shown in FIG. 2(a), an epitaxial layer 18 having a low impurity concentration of about 1015 cm-'' is formed on a low resistance r1 type silicon substrate 17.

Next, as shown in FIG. 2(b), a gate oxide film 19 is formed.
After forming a silicon oxide film with a thickness of 200 to 500A as
A polycrystalline silicon film 20 having a high impurity concentration of about 1019 cm-3 is formed.

Then, as shown in FIG. 2(C), this upper layer has a film thickness of 5.
A silicon oxide film 21 of about 0.006 is formed.

Subsequently, as shown in FIG. 2(d), a silicon nitride film 22 having a thickness of 200 OA is formed.

Thereafter, as shown in FIG. 2(e), the silicon oxide film 19, polycrystalline silicon film 20, silicon oxide film 21, and silicon nitride film 22 are patterned using photolithography, and the gate 7Ii electrode is patterned. When a pattern is formed, impurities W. A window 23 of the late river is formed.

Thereafter, as shown in FIG. 2('), thermal oxidation is performed to form a silicon oxide film 24 on the side walls of the gate electrode 20 and the bottom of the diffusion window 23.

After this, as shown in FIG. 2(g), boron ions are implanted into the entire surface and heat treatment is performed to diffuse the boron into the substrate through this window 23 to form a p-well 25, and to further increase the reactivity. The silicon oxide film at the bottom of the diffusion window 23 is removed by anisotropic etching such as ion etching.

Then, as shown in FIG. 2(h), 10
A polycrystalline silicon film 26 containing about 3 cm -3 of phosphorus or arsenic is deposited to a thickness of about 3000 to 5000 A.

Subsequently, as shown in FIG. 2(1), when this polycrystalline silicon film 26 is etched by anisotropic etching,
A polycrystalline silicon film remains as sidewalls 27 only on the sidewalls of the gate electrode.

Furthermore, as shown in FIG. 2 N), the surface is oxidized to form a silicon oxide film with a thickness of approximately 500 mm at the bottom of the diffusion window 23, and boron ions are ionized at low acceleration through this silicon oxide film. 29 is ion-implanted. During this surface oxidation, the surface of the sidewall 27 is also oxidized, but since the sidewall 27 is doped with a high concentration of phosphorus or arsenic, accelerated oxidation occurs, and the film thickness is about 100A.
A thick silicon oxide film 28 is formed, and ions are blocked by this thick silicon oxide film, so that almost no boron ions are implanted into the sidewall 27.

When heat treatment is performed in this state, phosphorus or arsenic is released from the sidewall 27 into the P well 2, as shown in FIG. 2(k).
5 to form the source n+ region 31,
Boron ions 29 are diffused from the bottom of the diffusion window 23 to form a p-well contact region 30.

After that, as shown in FIG. 2(1), the surface is cleaned, the silicon oxide film 28 is removed, and the sidewall 27 is removed.
, the surfaces of the source n+ region 31 and the p+ region 30 are exposed.

Finally, as shown in FIG. 2(m), a source electrode wiring 32 made of an aluminum-silicon layer is formed.

In the vertical MOS transistor formed in this way, the patterns of the n+ region 31 as the source, the p+ region 30 as the p-well contact, and the source electrode contact window 23 are all formed on the sidewall of the gate electrode 4. Since the formed sidewall 27 is formed as a mask or a diffusion source, there is no need to take allowance into consideration for positional deviation, and it is possible to achieve significant miniaturization.

Further, a sidewall 27 made of polycrystalline silicon is formed on the n+ region 31 as a source, and is connected to the source electrode wiring 32 via this sidewall 27, so that the source electrode wiring is substantially The contact area can be increased, and the contact resistance can be reduced.

Furthermore, since there is no triple point of aluminum-silicon, silicon oxide, and single-crystal silicon where solid-phase epitaxial growth is likely to occur, there is no risk of an increase in contact resistance due to silicon diffusion due to solid-phase epitaxial growth.

Next, as a second embodiment of the present invention, Cyduol 3
A method for preventing boron ions from being implanted into the substrate will be explained.

In this example, an insulating film such as a silicon nitride film that cannot be etched with a hydrogen fluoride (HF)-based etchant is formed on the main surface and sidewalls of the gate electrode, and a mask is added before forming the polycrystalline silicon sidewalls. A sidewall insulating film is formed as a sidewall insulating film, and boron ions are implanted for forming a p-well contact.

This vertical MOS transistor, as shown in Figure 3,
In addition to the structure of the first embodiment, a silicon nitride film 34 is interposed between the side wall insulating film 24 and the side wall 39, and a side wall insulating film of silicon oxide is further formed on the side wall of the silicon nitride film 34. After ion implantation for forming a p-well contact, this silicon oxide sidewall insulating film is selectively removed and a new silicon film sidewall 3 is formed.
9 is formed.

During manufacturing, thermal oxidation is performed to form a silicon oxide film 24 on the side walls of the gate electrode 20 and the bottom of the diffusion window 23, a p-well 25 is formed, and anisotropic etching such as reactive ion etching is performed. Diffusion window 2
The process up to the step shown in FIG. 2(g) for removing the silicon oxide film at the bottom of 3 is formed in exactly the same manner as in the first embodiment.

This state is shown in FIG. 4(a).

Subsequently, as shown in FIG. 4(b), CV
A silicon nitride film 33 having a thickness of 1000 Å to 2000 Å is formed by method D.

Then, as shown in FIG. 4C, the silicon nitride film 33 is etched by anisotropic etching, leaving the silicon nitride film 33 only on the side walls of the side wall insulating film 24 on the side walls of the gate electrode.

Furthermore, as shown in FIG. 4(d), CVD is applied to this upper layer.
By depositing a silicon oxide film 35 with a thickness of 2,000 to 5,000 Å using the method and performing anisotropic etching once again, the second sidewall insulating film 3 is formed as shown in FIG. 4(e).
6 is formed.

Then, as shown in FIG. 4(f'), boron ions 37 are implanted into the bottom of the diffusion window 23 using the second sidewall insulating film 36 as a mask.

Thereafter, as shown in FIG. 4(g), the second sidewall insulating film 36 is removed using a hydrogen fluoride-based etching solution. At this time, a silicon nitride film 34 that is not etched by the hydrogen fluoride-based etching solution is formed between the second sidewall insulating film 36 and the first sidewall insulating film 24 in contact with the gate electrode. , the etching will not proceed further.

Then, as shown in FIG. 4(h), 10
A polycrystalline silicon film 39 containing about 20,013 phosphorus or arsenic is deposited at about 3,000 to 500 OA, and by anisotropic etching, a side wall 39 is formed, and by heat treatment, phosphorus or arsenic is diffused from the side wall 39. While the source n+ region 41 is formed,
Boron ions 37 are diffused from the bottom of the diffusion window 23 to form a p-well contact region 40.

Thereafter, as shown in FIG. 4(j), the surface is cleaned and a source electrode wiring 42 made of an aluminum-silicon layer is formed.

In the vertical MOS transistor formed in this way, the sidewalls of the gate electrode are covered with the silicon nitride film 34 that cannot be etched with a hydrogen fluoride-based etchant, so a thick second silicon oxide film is formed. After forming a sidewall insulating film and implanting boron ions using this as a mask, this thick second sidewall insulating film can be selectively removed. Therefore, even if a large amount of boron is implanted, boron is not implanted into the three polycrystalline silicon sidewalls, so there is no risk of lowering the surface carrier concentration.

In addition, in order to make the boron concentration of the p-well contact region 40 sufficiently high, phosphorus or arsenic is implanted after forming the silicon nitride film 34 as shown in FIG. 4(C). A source n+ region 41 is formed, and later boron ions with a concentration higher than this are implanted to form a p source region 41.
It also becomes possible to form a p-type region 40 for a well contact.

Furthermore, in this example, a method has been described in which the gate electrode is covered with a silicon nitride film and the silicon oxide film sidewalls 36 are etched with a hydrogen fluoride-based etching solution. The sidewalls may be selectively etched with a phosphoric acid-based etching solution.

Further, according to the vertical MOS transistor of the present invention, since a polycrystalline silicon film is formed on the side wall of the gate electrode, titanium, tungsten,
The metal silicide film 43 made of palladium, platinum, etc. can be formed up to the bottom and sidewalls of the contact region with the source electrode wiring 32, and it is possible to further reduce the contact resistance.

Furthermore, when selectively growing a tungsten film from a contact hole using a selective CvDl film, it is necessary to
15 items Tungsten film 4 from silicon sidewall
4 grows, the contact hole is completely filled, and even if the source electrode wiring 45 is formed thinly, it is possible to obtain a highly reliable one without any breakage or the like.

[Effects of the Invention] As explained above, according to the present invention, a sidewall made of highly doped polycrystalline silicon is formed on the sidewall of the gate electrode via an insulating film, and this sidewall has self-containing properties. Since the source regions are formed in a matching manner, it is possible to obtain a vertical MOS transistor that is small and has low on-resistance.

Furthermore, according to the method of the present invention, since the polycrystalline silicon of the sidewall is used as a diffusion source to implant impurities for forming the source region, it is extremely easy to form the source region in a self-aligned manner with the sidewall. This makes it possible to obtain a vertical MOS transistor that is small and has low on-resistance.

[Brief explanation of drawings]

FIG. 1 shows a vertical MOS transistor according to the first embodiment of the present invention, and FIGS. 2(a) to 2(m) show the same vertical MOS transistor.
FIG. 3 is a diagram showing the manufacturing process of an OS transistor, FIG. 3 is a diagram showing a vertical MOS transistor of the second embodiment of the present invention, and FIGS. 4(a) to 4(j) are diagrams showing the manufacturing process of the vertical MOS transistor. 5 and 6 are diagrams showing the manufacturing process, FIGS. 5 and 6 are diagrams showing a vertical MOS transistor according to another embodiment of the present invention, FIG. 7 is a diagram showing a conventional vertical MOS transistor, and FIG.
8(a) to 8(j) are diagrams showing the manufacturing process of the same vertical MOS transistor. DESCRIPTION OF SYMBOLS 1... N-type silicon substrate, 2... N-type epitaxial layer, 3... Gate insulating film, 4... Gate electrode, 5
... Insulating film, 6... Diffusion window, 7... P well,
8... Phosphorus ion, 9... Resist pattern, 10
...Resist pattern, 12...n0 region (source region), 13...p10 region, 14... interlayer insulating film,
15... Contact window, 16... Source electrode wiring layer, 17... N-type silicon substrate, 18... N-type epitaxial layer, one. ．． ．． Gate insulating film, 20... Gate electrode, 21... Insulating film, 22... Silicon nitride film, 23... Diffusion window, 24... Sidewall insulating film, 25
... p-well, 26... polycrystalline silicon film, 27.
...Polycrystalline silicon side wall, 28...Silicon oxide film, 29...Boron ion, 30...P10 region, 31...N00 region (source region), 32...Source electrode wiring Layer, 33... Silicon nitride film, 34...
・Silicon nitride sidewall, 35. ．． ．． Silicon oxide film, 36... Silicon oxide side wall, 37.
...Boron ion, 38...Polycrystalline silicon film, 39...Polycrystalline silicon sidewall, 40...
-p10 region, 41...n0 region (source region), 42...source electrode wiring layer, 43...metal silicide, 44...tungsten film, 45...source electrode wiring layer.

Claims (2)

[Claims] (1) A well region of a second conductivity type, which is a conductivity type opposite to the first conductivity type, is provided on the main surface of the substrate region of the first conductivity type serving as a drain, and a channel region is provided at the end of the well region. a well contact region consisting of a high concentration region of a second conductivity type formed on the surface of the well region; and a gate electrode on the channel region. In the vertical MOS transistor, a sidewall made of polycrystalline silicon containing impurities of the same conductivity type as the source region is formed on the sidewall of the gate electrode via an insulating film, and directly below the sidewall. A semiconductor device characterized in that a source region is formed in a self-aligned manner. (2) A well region of a second conductivity type, which is a conductivity type opposite to the first conductivity type, is provided on the main surface of the substrate region of the first conductivity type serving as a drain, and a channel region is provided at the end of the well region. a well contact region consisting of a high concentration region of a second conductivity type formed on the surface of the well region; and a gate electrode on the channel region. A method for manufacturing a vertical MOS transistor comprising: after forming a gate electrode, a sidewall insulating film forming step of forming a sidewall insulating film on the sidewalls of the gate electrode; a second conductivity type impurity implantation step of implanting a second conductivity type impurity into the surface of the well formation region; A method for manufacturing a semiconductor device, comprising the steps of performing impurity diffusion using the impurity as a diffusion source to form a source region, and a heat treatment step of diffusing the second conductivity type impurity to form a well contact region.