KR100314272B1 - Method for forming silicide in semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming silicide in a semiconductor device is provided to reduce contact resistance between a source and drain junction and to improve uniformity of the silicide by performing ion-implantation after forming the silicide. CONSTITUTION: After forming a field oxide(2) at a semiconductor substrate(1) having a well(1'), a gate oxide layer(3) and a gate electrode(4) are sequentially formed on the resultant structure. An LDD(Lightly Doped Drain) region(5) is formed in the substrate. An oxide spacer(6) is formed at both sidewalls of the gate electrode. A titanium silicide layer(10) having a low resistance is grown selectively on the LDD region(5) and the gate electrode(4) by performing sequentially low-temperature RTP(Rapid Thermal Processing) and high-temperature RTP. Then, a source and drain junction(7) are formed by implanting heavily doped As ions into the LDD region.

Description

Silicide Formation Method of Semiconductor Device

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a metal silicide in a CMOS semiconductor element.

In recent years, as the degree of integration of semiconductor devices increases, the design rules of integrated circuit devices are reduced to sub-micron or smaller, resulting in smaller contact hole sizes, resulting in increased contact resistance and increased sheet resistance in shallow junctions of source / drain regions. .

Self-Aligned Silicide technology is used to reduce these resistance values and at the same time reduce the interconnect resistance of the polysilicon gate line.

That is, metal is deposited on the MOS structure to react with the silicon surface of the exposed source / drain and the polysilicon surface of the exposed gate to form silicide. After silicide formation, the unetched metal is removed by selective etching.

The most commonly used silicide in the silicide formation process is TiSi ₂ , and an example of the important process and the final silicide structure will be described with reference to FIGS. 1 (a) to 1 (e).

1 (a) to (e) are process cross-sectional views showing one example of a metal silicide forming method according to the prior art.

An example of a method of forming a metal silicide according to the prior art, as shown in FIG. (3) After patterning the gate electrode 4 after polysilicon deposition, impurity diffusion for forming the N ^- LDD region 5 is performed.

Next, as shown in FIG. 1B, an oxide is deposited on the upper surface of the entire structure including the gate electrode 4, and then sidewall spacers 6 are formed by anisotropic etching.

Subsequently, as shown in FIG. 1 (C), N ⁺ impurities are implanted into the silicon substrate 1 below both sides of the gate electrode 4 to form a source / drain junction region 7, and then the entire structure After depositing a titanium layer 9 on the substrate, the low temperature rapid heat treatment (RTP) process is performed to prevent the titanium layer 9 on the top of the field oxide film 2 and the sidewall oxide 6 from reacting with them. Titanium-silicide 10 is formed in the source / drain junction region 7 with the gate electrode 4 without being formed.

Then, as shown in Figure 1 (d), after removing the portion of the titanium layer (9) that did not react in the previous step through the etching process, the low-resistance of the titanium-silicide (10) through the high temperature RTP process It is formed of silicide of resistance.

Subsequently, as shown in FIG. 1E, the structure is completed by covering the BSG passivation film 11, performing reflow, forming a contact hole, and depositing aluminum to form the electrode wiring 12. .

In such a silicide structure, silicide is formed in the source / drain junction region and the gate electrode, and these regions are separated by the sidewall spacers 6.

Since the separation interval is very narrow, a bridging phenomenon occurs in which the gate and the source / drain junction region are short-circuited, and annealing is performed in pure nitrogen gas or pure forming gas (90% nitrogen + 10% hydrogen) atmosphere to eliminate this.

On the other hand, when the silicide formation method is adapted to a CMOS device, after forming N wells and P wells, metal silicide is formed after implanting predetermined impurities to form source / drain junction regions of the PMOS device and the NMOS device.

[Inventive problem to solve]

However, unlike the results of silicide formation in the PMOS region, the scanning of the high concentration of arsenic (As) atoms implanted to make the source / drain junction region in the NMOS region affects the formation of the titanium-silicide, preventing the formation of uniform silicide. Observation results with an electron microscope (SEM) were revealed.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and the source of the NMOS device region can be prevented from forming uneven silicide by arsenic atoms ionically implanted at high concentration in the source / drain junction region of the NMOS device. It is an object of the present invention to provide a silicide forming method in which a titanium-silicide is first formed in a / drain junction region and then a junction is formed by a predetermined ion implantation.

[Means for solving the problem]

The present invention for achieving the above object, the step of forming a field oxide film on a semiconductor substrate, and forming a gate oxide film, a gate electrode thereon; Forming an N ^- LDD region on the semiconductor substrate below both sides of the gate electrode; Depositing an oxide on an upper surface of the entire structure and anisotropically etching the oxide to form a sidewall spacer on a side of the gate electrode; Growing a titanium layer on an NMOS element region portion of the semiconductor substrate; The low temperature RTP process causes the titanium oxide layer on the field oxide layer and the sidewall spacer to form titanium-silicide having high resistance in the gate electrode and the N ^- LDD region without reacting with titanium, and then not reacting with the oxide layer. Etching the portion and then performing a high temperature RTP process to change the high-resistance titanium-silicide into a low-resistance titanium-silicide; And implanting a high concentration of arsenic ions into the N ^- LDD region to form a source / drain junction region.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 (a) to (c) are main cross-sectional views showing a metal silicide forming process of a semiconductor device according to the present invention.

In the silicide forming method according to the present invention, as shown in FIG. 2 (a), first, a separation region is formed on the semiconductor substrate 1 by the field oxide film 2, and then the well ( 1 ').

Next, a gate oxide film 3 and a gate electrode 4 using polysilicon are formed thereon, ion implantation is performed to form the N ^- LDD region 5, and then oxides are deposited on the entire surface, and then anisotropically etched. A sidewall spacer 6 is formed on the side of the gate electrode 4. Titanium (Ti) is then deposited over the entire surface to grow the titanium layer 9.

Subsequently, as illustrated in FIG. 2B, a portion of the titanium oxide layer 9 and the upper portion of the field oxide layer 2 and the sidewall spacers 6 are prevented from reacting with titanium through a low temperature RTP process. (4) and the titanium-silicide (10) having high resistance in the N ^- LDD region (5) were formed, and then the portion of the turtan layer (9) which did not react with the oxide film was etched with an etchant, followed by high temperature RTP The high-resistance titanium-silicide 10 formed in the gate electrode 4 and the N ^- LDD region 5 is changed to the low-resistance titanium-silicide 10. A high concentration of arsenic As ⁺ ion implantation (K) for source / drain junction region formation is performed to form the source / drain junction region 7.

Then, as shown in Fig. 2 (C), a high concentration of arsenic As ⁺ ion implantation (K) to form a source / drain junction region to form a source / drain junction region (7), and then the subsequent process After forming the contact hole through passivation and reflow, aluminum is deposited to form the electrode wiring, thereby completing the CMOS structure.

1 (a) to (e) are process cross-sectional views showing one example of a metal silicide forming method according to the prior art.

2 (a) to (c) are main process cross-sectional views showing a metal silicide forming process of a semiconductor device according to the present invention.

Explanation of symbols on the main parts of the drawings

4: polysilicon gate 6: sidewall spacer

7: source / drain junction 9: titanium layer

10: titanium-silicide K: high concentration of arsenic ions

As described above, according to the present invention, in the titanium-silicide process of reducing the contact resistance between the gate and the source / drain junction region of the NMOS device, a high concentration of arsenic ion implantation is performed after the titanium-silicide is formed so that the resistance of the source / drain junction is small and uniform. There is an advantage in obtaining a titanium-silicide.

Claims (1)

Forming a field oxide film on the semiconductor substrate, and forming a gate oxide film and a gate electrode of the NMOS device thereon; Forming an N ^- LDD region on the semiconductor substrate below both sides of the gate electrode; Depositing an oxide on an upper surface of the entire structure and anisotropically etching the oxide to form a sidewall spacer on a side of the gate electrode; Growing a titanium layer on an NMOS element region portion of the semiconductor substrate; The low temperature RTP process causes the titanium oxide layer on the field oxide layer and the sidewall spacer to form titanium-silicide having high resistance in the gate electrode and the N ^- LDD region without reacting with titanium, and then not reacting with the oxide layer. Etching the portion and then performing a high temperature RTP process to change the high-resistance titanium-silicide into a low-resistance titanium-silicide; Forming a source / drain junction region by implanting a high concentration of arsenic ions into the N ^- LDD region;