JPH0548110A - Manufacture of semiconductor element - Google Patents

Abstract

PURPOSE:To improve the concentration controllability of layers so as to reduce the fluctuation of a threshold value by implanting ions of P-type impurity into a P<-> layer after ions of an N-type impurity are implanted into the P<-> layer after an opening and gate pattern are formed and, at the same time, diffusing controlled amount of the impurity in an N<+> layer. CONSTITUTION:After an opening 5 and gate pattern composed of a CVD SiO2 film 4, poly-Si film 3, and SiO film 2 are formed on an N-type semiconductor substrate 1, an N<+> layer 12 is formed in a P<-> layer 6 by implanting ions of an N-type impurity As into the layer 6 by using the gate pattern as a mask. Then, after removing the ion-implanted N-type impurities, the N<+> layer 12 and a P<+> layer 13 are formed in the layer 6 by implanting ions of a P-type impurity into and heat treating the layer 6. At the time of forming the N<+> and P<+> layers 12 and 13, controlled amount of the impurity is diffused in the layer 12 and the side wall of an Si-removed section becomes an N<+> layer. When the N<+> layer is formed by ion implantation in such way, the concentration controllability can be improved and fluctuation of a threshold can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a vertical double diffusion MOSFET in a semiconductor device, and provides a method for obtaining better electric characteristics.

[0002]

2. Description of the Related Art Conventionally, a method of manufacturing a semiconductor device of this type has been described in IEDM. 88 (1988) IEEE (US) p. 8
13-816, a vertical double diffusion MOSFET is shown as an example in FIGS. 3A to 3C, and will be described below.

As shown in FIG. 3A, a 1000 Å SiO ₂ film _2, 4000 Å is formed on the main surface of the U-type semiconductor substrate 1.
Conductive polysilicon film 3 and C of 8000Å
The VDSiO ₂ film 4 is sequentially formed. The next desired patterning, the SiO ₂ film 2, by etching the polysilicon film 3 and CVD SiO ₂ film 4, CVD SiO ₂ film 4 by opening the opening portion 5, the polysilicon film 3 and the SiO ₂ film A gate pattern of 2 is formed.

Then, as shown in FIG. 3B, boron, which is a P-type impurity, is implanted into the U-type semiconductor substrate 1 by an ion implantation method using the patterned gate pattern as a mask, and heat treatment is performed. , P ⁻ layer 6 is formed. Next, a PSG film containing phosphorus which is an N-type impurity
After the formation, the anisotropic etching by dry etching is performed to form the PSG sidewall 7 and the sidewall opening portion 8.

Next, as shown in FIG. 3C, CVDSiO
_{2 Using the} film 4 and the PSG sidewall 7 as a mask, boron, which is a P-type impurity, is implanted into the P ⁻ layer 6 below the sidewall opening 8 by ion implantation. Next, heat treatment is applied,
The ion-implanted boron is diffused to form the P ⁺ layer 10, and the phosphorus in the PSG sidewall 7 diffuses into the P ⁻ layer and spreads laterally, so that it is below the polysilicon film 3 and inside the sidewall opening. To form an N ⁺ layer 9. Next, metal is vapor-deposited on the entire surface to form a metal 11 serving as a source electrode in ohmic contact with the N ⁺ layer 9 and the P ⁺ layer 10 in the sidewall opening.

Through the above process, the vertical double diffusion type MOS
FET is obtained.

[0007]

However, in the above-mentioned manufacturing method, since the N ⁺ layer 9 is formed by the diffusion of phosphorus in the PSG sidewall 7, the concentration of phosphorus entering the P ⁻ layer 6 is reduced. It is determined by the phosphorus concentration at the time of forming the PSG sidewall and the heat treatment conditions for diffusing from the PSG sidewall 7 into silicon. Therefore, the phosphorus concentration in the P ⁻ layer 6 has a large variation, and the junction depth of the N ⁺ layer also has a large variation. This allows double diffusion type M
The OSFET has a problem that the variation in V _T (threshold value) becomes large.

Further, the ohmic contact between the N ⁺ layer 9 and the metal 11 is taken in the laterally diffused portion diffused from the PSG sidewall 7 into the P ⁻ layer 6, and the contact portion of the contact portion due to the phosphorus concentration described above is taken. Since there is a large variation in the area, there is a problem that the variation in the contact resistance becomes large.

In order to eliminate the above-mentioned problems of deteriorating the electrical characteristics, the present invention provides a manufacturing method in which the N ⁺ layer is formed by the ion implantation method to improve the controllability of the N-type impurity concentration. To aim.

[0010]

SUMMARY OF THE INVENTION The present invention for the purpose described above, in the manufacturing method of the semiconductor device, after forming the opening and the gate pattern, the N-type impurity for the N ⁺ layer formed P ^- Ions are implanted in the layer using the gate pattern as a mask. Then, after forming a SiO ₂ sidewall on the side wall of the opening, using the SiO ₂ sidewall as a mask, P
^- silicon layer is etched away as 0.3 [mu] m, removing the ion-implanted N-type impurity. Then again Si
A P-type impurity is ion-implanted into the P ⁻ layer using the O ₂ sidewall as a mask, and a heat treatment is applied to the N ⁺ layer and the P ⁻ layer.
⁺ Form a layer. At this time N ⁺ layer weight was controlled impurity is diffused, the side wall of the silicon removed portion becomes N ⁺ layer. Next, metal is vapor-deposited on the entire surface to make contact with the N ⁺ layer and the side wall of the silicon-removed portion as a center, and
The contact is made with the P ⁺ layer at the bottom surface where the silicon is removed.

[0011]

As described above, according to the present invention, since the N ⁺ layer is formed by the ion implantation method, the controllability of the concentration is improved and the accuracy of the junction depth of the N ⁺ layer is improved. The variation of _T becomes small. Further, since the accuracy of the contact area with the source electrode is improved, the variation in contact resistance is reduced and the electrical characteristics are improved.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention is shown in FIGS.
A description will be given according to (e).

As shown in FIG. 1A, similarly to the conventional method, a SiO ₂ film ₂ as an insulating film of about 1000 Å is formed on the main surface of the N-type semiconductor substrate 1, and a poly-silicon film having a conductivity of about 4000 Å is formed. After the CVD SiO ₂ film 4 is sequentially formed as a silicon film 3 and an insulating film of about 8000 Å, the CVD SiO ₂ film 4, the polysilicon film 3 and the SiO ₂ film 2 are etched and removed by desired gate patterning,
A gate pattern composed of the opening 5 and the CVD SiO ₂ film 4, the polysilicon film 3 and the SiO ₂ film 2 is formed.

Next, as shown in FIG. 1B, using the gate pattern as a mask, an ion implantation method is performed to change the amount of boron to 4
About 5 × 10 ¹³ ions / cm ² N in the opening 5 at 0 keV
By injecting into the semiconductor substrate 1 and heat-treating,
A P ⁻ layer 6 having a junction depth of about 2 μm is formed. Next, using the gate pattern as a mask, an N-type impurity such as arsenic is ion-implanted at 40 keV and 1 × 10 ¹⁶ ions.
/ Cm ² is injected into the surface of the P ⁻ layer 6 in the opening 5, and N
⁺ Implant (ion implantation) layer 7 is formed.

Next, as shown in FIG. 1C, C is used as an insulating film.
12000Å SiO ₂ film containing no impurities by VD method
After the formation, the SiO ₂ side wall 8 having a lateral length of about 12,000 Å is formed on the side wall of the opening 5 by anisotropic etching by dry etching to form the side wall opening 9.

Next, as shown in FIG. 1D, with the SiO ₂ sidewall 8 and the gate pattern as a mask, the silicon under the sidewall opening 9 is removed by about 0.3 μm by dry etching. ^{+ The} implanter layer 7 is removed and the opening 10 is formed. Next, similarly, by using the SiO ₂ sidewall 8 and the gate pattern as a mask, an ion implantation method is applied to the P ⁻ layer 6 in the opening 10 with an amount smaller than the dose amount of the N ⁺ implantation layer 7, for example, 40 keV. Inject about 1 × 10 ¹⁵ ions / cm ² and p ⁺ implant layer 1
1 is formed.

Next, as shown in FIG. 1E, 1000 ° C., 6
By performing the heat treatment for about 0 minutes, the N ⁺ implantation layer 7 and the P ⁺ implantation layer 11 are diffused, and the junction depth is 0.5 μm.
An N ⁺ layer 12 having a thickness of about m and a P ⁺ layer 13 having a diffusion depth of about 1 μm are formed. At this time, the surface concentration of the N ⁺ layer 12 is P ⁺ layer 1
Since the surface concentration is higher than that of No. 3 by about one digit, the vicinity of the side wall of the opening 10 becomes an N ⁺ layer.

Next, a metal 14 is vapor-deposited on the entire surface, and ohmic contact is made with the N ⁺ layer 12 and the P ⁺ layer 13 in the opening portion 10 to form a source electrode.

By the above manufacturing method, the vertical double diffusion type M
An OSFET is obtained.

In this embodiment, the SiO ₂ sidewall 8 is used.
Was formed of a CVD SiO ₂ film containing no impurities.
Even if the SiO ₂ film containing impurities such as the SGSiO ₂ film is used, if a thin SiO ₂ film is formed so that the concentration does not affect the junction depth of the N ⁺ layer 12 or that it does not enter, it is used. Needless to say, it does not matter.

Further, in this embodiment, an N channel double spread type M
Although the OSFET is taken as an example, it goes without saying that it can be applied to a semiconductor element having the same structure such as an insulated gate bipolar transistor or P channel by reversing P and N.

Next, a second embodiment will be described with reference to FIGS.

As shown in FIG. 2 (a), a CVD SiO ₂ film 4 of about 17,000 Å is formed as in FIG. 1 (a) of the first embodiment, and then the steps of FIGS. 1 (b) to 1 (c) are performed. After the formation of the P ⁺ implantation layer 11, as shown in FIG. 2B, the entire surface is subjected to anisotropic etching by dry etching or wet etching by about 0.5 μm, and the SiO ₂ sidewall 8 is formed by 0.5 μm. The width is reduced, that is, the side wall opening is expanded by 0.5 μm on one side to form the exposed portion 21 of the N ⁺ implantation layer 7.

Next, as shown in FIG. 2 (c), 6 at 1000.degree.
After heat treatment for about 0 minutes to form the N ⁺ layer 12 and the P ⁺ layer 13, the metal 14 is vapor-deposited on the entire surface, and the N ⁺ layer 12 and the opening are formed in the vicinity of the exposed portion 21 and the side wall of the opening 10. A source electrode having ohmic contact with the P ⁺ layer 13 is formed at the bottom of the portion 10.

By performing the above steps, a vertical double diffusion MOSFET can be obtained.

In the second embodiment, the SiO ₂ sidewall is reduced before the formation of the N ⁺ layer 12 and the P ⁺ layer 13, but it goes without saying that it may be performed after the formation. Absent.

[0027]

As described in detail above, according to the present invention, since the N ⁺ layer is formed by the ion implantation method, the controllability of the concentration is improved and the accuracy of the junction depth of the N ⁺ layer is improved. Therefore, the variation of V _T becomes small. Further, since the accuracy of the contact area with the source electrode is improved, the variation in contact resistance is reduced and the electrical characteristics are improved.

Further, as shown in the second embodiment, after the ion implantation for forming the P ⁺ diffusion layer is performed, the SiO ₂ sidewall is reduced to form the exposed portion of the N ⁺ layer. Since the contact area between the source electrode and the N ⁺ layer is large, the contact resistance is reduced and ohmic contact is surely obtained in the exposed portion, so that the variation in the contact resistance is further reduced.

[Brief description of drawings]

FIG. 1 is a process sectional view of a first embodiment of the present invention.

FIG. 2 is a process sectional view of a second embodiment of the present invention.

FIG. 3 is a process sectional view of a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 N-type semiconductor substrate 2 SiO ₂ film 3 Polysilicon film 4 CVDSiO ₂ film 5 Opening part 6 P ^- layer 7 N ⁺ implantation layer 8 SiO ₂ sidewall 9 Sidewall opening portion 10 Opening portion 11 P ⁺ implantation layer 12 N ⁺ layer 13 P ⁺ layer 14 metal

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 8617-4M H01L 21/265 L

Claims (2)

[Claims] 1. (a) A first insulating film, a conductive conductive film, and a second insulating film are sequentially formed on one main surface of a first conductive type semiconductor substrate, and then desired patterning is performed. And forming a gate opening formed of the first insulating film, the conductive film, and the second insulating film, and a first opening reaching the semiconductor substrate, (b) the first opening. After diffusing impurities into the semiconductor substrate in the hole to form a first impurity region of the second conductivity type, a first impurity region in the first hole is exposed to a surface portion in the first impurity region. Forming a second impurity region of the first conductivity type; (c) forming a sidewall made of an insulating film on a sidewall of the first opening; (d) the first opening. By etching away the surface portion of the semiconductor substrate in the portion where the sidewall is not present, A second opening is formed by removing the second impurity region, and a second conductivity type third impurity region is formed in the first impurity region in the second opening. And (e) heat treatment is performed to form a fourth impurity region diffused from the second impurity region and a fifth impurity region diffused from the third impurity region. A step of vapor-depositing metal to make ohmic contact with the fourth and fifth impurity regions in the second opening, and a method of manufacturing a semiconductor element. 2. After performing the steps (a) to (d) of claim 1, the sidewall of (c) is further reduced by etching to obtain the second layer of the above item. A method of manufacturing a semiconductor device, which comprises performing the step (e) of claim 1 after forming the exposed portion of the impurity region.