JP3161767B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a vertical double-diffused MOSFET in a semiconductor device, and provides a method for obtaining better electric characteristics.

[0002]

2. Description of the Related Art Conventionally, a method of manufacturing a semiconductor device of this kind has been disclosed in IEDM. 88 (1988) IEEE (US) p. 8
13 (a) to 13 (c), which will be described below by taking a vertical double-diffused MOSFET as an example.

[0003] As shown in FIG. 3 (a), a 1000 ° SiO ₂ film _2, 4000 ° is formed on the main surface of a U-type semiconductor substrate 1.
Conductive polysilicon film 3 and 8000 ° C.
A VDSiO ₂ film 4 is sequentially formed. The next desired patterning, the SiO ₂ film 2, by etching the polysilicon film 3 and CVD SiO ₂ film 4, CVD SiO ₂ film 4 by opening the opening portion 5, the polysilicon film 3 and the SiO ₂ film 2 are formed.

Next, as shown in FIG. 3B, boron as a P-type impurity is implanted into the U-type semiconductor substrate 1 by ion implantation using the patterned gate pattern as a mask, and heat treatment is performed. , P ^- layer 6 are formed. Next, a PSG film containing phosphorus, which is an N-type impurity, is deposited at 12000Å.
After the formation, anisotropic etching by dry etching is performed to form a PSG sidewall 7 and a sidewall opening 8.

[0005] Next, as shown in FIG.
_{Using the second} film 4 and the PSG sidewall 7 as a mask, boron as a P-type impurity is implanted into the P ⁻ layer 6 below the sidewall opening 8 by an ion implantation method. Next, heat treatment is applied,
To form a P ⁺ layer 10 to diffuse the ion-implanted boron, PSG phosphorus in the sidewalls 7, P ^- by diffusion and Yoko拡Ri in the layer, or the side wall opening in the bottom of the polysilicon film 3 And an N ⁺ layer 9 is formed. Next, a metal 11 is formed as a source electrode in ohmic contact with the N ⁺ layer 9 and the P ⁺ layer 10 in the side wall opening by depositing a metal on the entire surface.

[0006] By the above process, the vertical double diffusion type MOS
An FET is obtained.

[0007]

[SUMMARY OF THE INVENTION However, in the manufacturing method described above, since it the formation of N ⁺ layer 9 is formed by diffusion of phosphorus in the PSG sidewall 7, P ^- phosphorus concentration entering in the layer 6 is It is determined by the phosphorus concentration at the time of forming the PSG sidewall and the heat treatment conditions for diffusing from the PSG sidewall 7 into silicon. For this reason, the phosphorus concentration in the P ⁻ layer 6 has a large variation, and the junction depth of the N ⁺ layer has a large variation. Thereby, the double diffusion type M
The OSFET has a problem that V _T (threshold) varies greatly.

The ohmic contact between the N ⁺ layer 9 and the metal 11 is diffused from the PSG side wall 7 into the P ⁻ layer 6 and is taken in a laterally expanded portion. Since the variation in the area is large, there is a problem that the variation in the contact resistance becomes large.

The present invention provides a manufacturing method in which the N ⁺ layer is formed by an ion implantation method to improve the controllability of the N-type impurity concentration in order to eliminate the above-mentioned problem that the electric characteristics are deteriorated. Aim.

[0010]

SUMMARY OF THE INVENTION The present invention for the purpose described above, in the manufacturing method of the semiconductor device, after forming the opening and the gate pattern, the N-type impurity for the N ⁺ layer formed P ^- Ions are implanted into the layer using the gate pattern as a mask. Then, after forming an SiO ₂ sidewall on the side wall of the opening, the SiO ₂ sidewall is used as a mask, and P
^- silicon layer is etched away as 0.3 [mu] m, removing the ion-implanted N-type impurity. Then again Si
P-type impurities are ion-implanted into the P ⁻ layer using the O ₂ side wall as a mask, and heat treatment is performed, so that the N ⁺ layer and the P ⁺
Form a ⁺ layer. At this time N ⁺ layer weight was controlled impurity is diffused, the side wall of the silicon removed portion becomes N ⁺ layer. Next, metal is vapor-deposited on the entire surface, and contact is made around the N ⁺ layer and the side wall of the portion where silicon has been removed.
The contact is made with the P ⁺ layer on the bottom surface from which silicon has been removed.

[0011]

As described above, according to the present invention, since the N ⁺ layer is formed by the ion implantation method, the controllability of the concentration is improved, and the accuracy of the junction depth of the N ⁺ layer is improved. _T variations are reduced. Further, since the accuracy of the contact area with the source electrode is improved, the electrical characteristics are improved, such as the variation in the contact resistance is reduced.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention is shown in FIGS.
Explanation will be given according to (e).

As shown in FIG. 1A, as in the conventional method, an SiO ₂ film is formed on the main surface of the N-type semiconductor substrate 1 as an insulating film of about 1000 °, and a poly-electrode is formed as a film having a conductivity of about 4000 °. After sequentially forming a silicon film 3 and a CVD SiO ₂ film 4 as an insulating film of about 8000 °, the CVD SiO ₂ film 4, the polysilicon film 3 and the SiO ₂ film 2 are removed by etching by desired gate patterning.
A gate pattern composed of the opening 5, the CVD SiO ₂ film 4, the polysilicon film 3, and the SiO ₂ film 2 is formed.

Next, as shown in FIG. 1B, using the gate pattern as a mask, boron is
At 0 keV, 5 × 10 ¹³ ions / cm ^{2 in the} opening 5
By injecting into the mold semiconductor substrate 1 and performing a heat treatment,
A P ⁻ layer 6 having a junction depth of about 2 μm is formed. Next, using the gate pattern as a mask, an N-type impurity such as arsenic is ion-implanted at 40 keV and 1 × 10 ¹⁶ ions.
/ Cm ^{2 to} the surface of the P ⁻ layer 6 in the opening 5 and N
⁺ Implantation (ion implantation) layer 7 is formed.

[0015] Next, as shown in FIG.
12,000Å of SiO ₂ film containing no impurities by VD method
Thereafter, an SiO ₂ sidewall 8 having a lateral length of about 12000 ° is formed on a side wall of the opening 5 by anisotropic etching by dry etching, and a sidewall opening 9 is formed.

Next, as shown in FIG. 1D, by using the SiO ₂ side walls 8 and the gate pattern as a mask, silicon under the side wall openings 9 is removed by about 0.3 μm by dry etching. ⁺ Implantation layer 7 is removed, and opening 10 is formed. Next, similarly, using the SiO ₂ side wall 8 and the gate pattern as a mask, the ion implantation method is used to implant the P ⁺ layer 6 in the opening 10 into the P ⁻ layer 6 at a dose smaller than the dose of the N ⁺ implant layer 7, for example, 40 keV. Inject about 1 × 10 ¹⁵ ions / cm ² , P ⁺ implant layer 1
Form one.

Next, as shown in FIG.
By performing the heat treatment for about 0 minutes, the N ⁺ implanted layer 7 and the P ⁺ implanted layer 11 are diffused to have a junction depth of 0.5 μm.
An N ⁺ layer 12 having a thickness of about m and a P ⁺ layer 13 having a diffusion depth of about 1 μm are formed. At this time, the surface concentration of the N ⁺ layer 12 is the P ⁺ layer 1
Since the surface concentration of the hole 3 is higher by about one digit, the vicinity of the side wall of the opening 10 becomes an N ⁺ layer.

Next, a metal 14 is vapor-deposited on the entire surface, and an ohmic contact is made with the N ⁺ layer 12 and the P ⁺ layer 13 in the opening 10 to form a source electrode.

The vertical double diffusion type M
An OSFET is obtained.

In this embodiment, the SiO ₂ side wall 8 is used.
Was formed of a CVD SiO ₂ film containing no impurities.
Even if an SiO ₂ film containing impurities such as an SGSiO ₂ film is used, if a concentration that does not affect the junction depth of the N ⁺ layer 12 or a thin SiO ₂ film is formed so as not to enter. Needless to say, it does not matter.

In this embodiment, an N-channel double diffusion type M
Although an OSFET is taken as an example, it goes without saying that the present invention can be applied to a P-channel by inverting P and N and a semiconductor element having the same structure such as an insulated gate bipolar transistor.

Next, a second embodiment will be described with reference to FIGS.

As shown in FIG. 2 (a), after forming a CVD SiO ₂ film 4 about 17000 ° like FIG. 1 (a) of the first embodiment, the steps of FIGS. 1 (b) to 1 (c) are performed. After the formation of the P ⁺ implant layer 11, as shown in FIG. 2B, anisotropic etching or wet etching by dry etching is performed on the entire surface by about 0.5 μm, and the SiO ₂ sidewall 8 is formed by 0.5 μm. In other words, the exposed portion 21 of the N ⁺ implant layer 7 is formed by expanding the side wall opening by about 0.5 μm on one side.

Next, as shown in FIG.
After performing heat treatment for about 0 minutes to form the N ⁺ layer 12 and the P ⁺ layer 13, a metal 14 is deposited on the entire surface, and the N ⁺ layer 12 and the hole are formed near the exposed portion 21 and the side wall of the hole 10. At the bottom of the portion 10, a source electrode which makes ohmic contact with the P ⁺ layer 13 is formed.

By performing the above steps, a vertical double-diffused MOSFET is obtained.

In the second embodiment, the reduction of the SiO ₂ sidewall is performed before the formation of the N ⁺ layer 12 and the P ⁺ layer 13, but it is needless to say that the reduction may be performed after the formation. Absent.

[0027]

As described above in detail, according to the present invention, since the N ⁺ layer is formed by the ion implantation method, the controllability of the concentration is improved, and the accuracy of the junction depth of the N ⁺ layer is improved. in order to, variations of V _T is reduced. In addition, since the accuracy of the contact area with the source electrode is improved, the variation in the contact resistance is reduced, and the electrical characteristics are improved.

As shown in the second embodiment, after the ion implantation for forming the P ⁺ diffusion layer is performed, the SiO ₂ side wall is reduced to form the exposed portion of the N ⁺ layer. Since the contact area between the source electrode and the N ⁺ layer is increased, the contact resistance is reduced, and the ohmic contact is reliably obtained at the exposed portion, so that the variation in the contact resistance is further reduced.

[Brief description of the drawings]

FIG. 1 is a process sectional view of a first embodiment of the present invention.

FIG. 2 is a process sectional view of a second embodiment of the present invention.

FIG. 3 is a process sectional view of a conventional example.

[Explanation of symbols]

1 N-type semiconductor substrate 2 SiO ₂ film 3 polysilicon film 4 CVD SiO ₂ film 5 opening 6 P ^- layers 7 N ⁺ implantation layer 8 SiO ₂ sidewalls 9 sidewall opening 10 opening 11 P ⁺ implanted layer 12 N ⁺ layer 13 P ⁺ layer 14 metal

Claims (2)

(57) [Claims] (A) forming a first insulating film, a conductive film having conductivity, and a second insulating film on one main surface of a semiconductor substrate of a first conductivity type and then performing desired patterning; Forming a gate pattern portion comprising the first insulating film, the conductive film, and the second insulating film, and a first opening reaching the semiconductor substrate; and (b) forming the first opening portion. by diffusing impurities into said semiconductor base in the hole, after forming the first impurity region of a second conductivity type, a first surface portion in the impurity region of the first inside opening, the Forming a second impurity region of the first conductivity type by an ion implantation method using the gate pattern portion as a mask ; and (c) forming a sidewall made of an insulating film on a side wall of the first opening. (D) a portion without the sidewall in the first opening portion; The surface portion of the semiconductor substrate is removed by etching to form a second opening portion in which the second impurity region formed by ion implantation is partially removed, and then a second opening portion is formed in the second opening portion. The side surface in the first impurity region of
Forming a third impurity region of a second conductivity type using the wall and the gate pattern portion as a mask ; and (e) performing a heat treatment to diffuse the third impurity region from the second impurity region.
The fourth impurity region is diffused from the third impurity region to form a fifth impurity region including immediately below the fourth impurity region , and then a metal is evaporated to form the second impurity region. Forming an ohmic contact with the fourth and fifth impurity regions in the opening. " After wherein subjected to to claim 1, wherein the (a) absence of up paragraph (d) step, by shrink by further etching the sidewalls of the section (c), wherein (b) above, wherein Forming an exposed portion of the second impurity region.
A method for manufacturing a semiconductor device, comprising performing the step (e).