JP3955123B2 - Manufacturing method of MOS transistor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a MOS transistor, and is a technique that is particularly effective when applied to speeding up of an LSI.
[0002]
[Prior art]
As a prior art, FIG. 4 shows a method for manufacturing a MOS transistor. The MOS transistor in this example is an N-type MOS transistor, and a field shield element isolation method is used for element isolation.
[0003]
A field shield gate oxide film 201, a field shield gate electrode 202, and a cap oxide film 203 are formed on a P-type silicon substrate 200, patterned, and then a side wall spacer oxide film 204 covering these sidewalls is formed to form a field shield. An element isolation structure is formed (FIG. A).
[0004]
Next, a gate oxide film 205, a gate electrode 206, and a cap oxide film 207 are formed in the active region, patterned, and then a sidewall spacer oxide film 208 covering these sidewalls is formed (FIG. B).
[0005]
Next, after forming a polycrystalline silicon film doped with arsenic on the entire surface, patterning is performed to form the source / drain electrodes 209 of the MOS transistor (FIG. C).
[0006]
Next, an interlayer insulating film 210 is formed. By the heat treatment at this time, arsenic is thermally diffused from the source / drain electrode 209 to the P-type silicon substrate 200, and the source / drain diffusion layer 212 is formed. Subsequently, the contact hole 211 is opened (FIG. D).
[0007]
Finally, metal wiring 213 is formed to complete a MOS transistor having a field shield element isolation structure (FIG. E).
[0008]
[Problems to be solved by the invention]
In the MOS transistor having the above structure, a side wall spacer made of an oxide film is present on the side wall of the gate electrode, so that a parasitic capacitance is formed between the gate electrode and the drain electrode. Due to the delay due to the parasitic capacitance, there is a problem that the circuit operation becomes slow.
[0009]
Therefore, an object of the present invention is to provide a method for manufacturing a MOS transistor in which the parasitic capacity is reduced and the driving capability is improved.
[0010]
[Means for Solving the Problems]
In order to solve the above problems, the present invention forms a two-layer film of a silicon oxide film (lower layer) and a silicon nitride film (upper layer) as a cap insulating film of a gate electrode, and after patterning the gate electrode, these (that is, , Means for forming a sidewall spacer made of a silicon nitride film is provided on the sidewalls of the gate electrode, silicon oxide film and silicon nitride film .
[0011]
In addition, after patterning the source / drain electrodes made of the polycrystalline silicon film, a means for selectively removing the cap insulating film made of the silicon nitride film and the side wall spacer made of the silicon nitride film from the silicon oxide film or the like is provided. It is a thing.
[0012]
[Action]
According to the above means, since the gap is formed between the gate electrode and the source / drain electrode, the parasitic capacitance between the electrodes is reduced. As a result, the driving capability of the MOS transistor is improved, and the circuit operation speed can be increased.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
As an embodiment of the present invention, a plan view of a MOS transistor is shown in FIG. Further, FIG. 2 shows a vertical cross-sectional view of the manufacturing process on the plane AA ′ in FIG. 1, and FIG.
[0014]
A field shield gate oxide film 101 made of a silicon oxide film of 50 to 100 nm is formed on a P-type silicon substrate 100 by a thermal oxidation method, and then a field shield made of a polycrystalline silicon film doped with phosphorus of 150 to 200 nm by a CVD method. The gate electrode 102 and a cap oxide film 103 made of a silicon oxide film of 200 to 250 nm are sequentially formed, patterned into a predetermined shape, and then a sidewall spacer oxide film 104 made of a silicon oxide film is formed so as to cover these sidewalls. To do. Through the above steps, a field shield element isolation structure is formed (FIG. A).
[0015]
Next, after a gate oxide film 105 made of a silicon oxide film of 10 to 20 nm is formed on the silicon substrate 100 in the active region by a thermal oxidation method, a polycrystalline silicon film doped with phosphorus of 150 to 200 nm by a CVD method. A gate electrode 106 made of 150, a cap oxide film 107 made of a 150-200 nm silicon oxide film, and a cap nitride film 108 made of a 150-200 nm silicon nitride film are sequentially formed and patterned into a predetermined shape. A sidewall spacer nitride film 109 made of a silicon nitride film is formed so as to cover it (FIG. B).
[0016]
Next, a polycrystalline silicon film 110 having a thickness of 150 to 200 nm is formed on the entire surface by CVD, and arsenic (acceleration energy: 50 to 90 keV, dose: 5 to 10E15 cm −2) is introduced by an ion implantation method to have a predetermined shape. The source / drain electrode 110 is formed by patterning (FIG. C).
[0017]
Next, the cap nitride film 108 and the sidewall spacer nitride film 109 are selectively removed by wet etching using hot phosphoric acid. As a result, a gap 111 is formed between the gate electrode 106 and the source / drain electrode 110 (FIG. D).
[0018]
Next, a BPSG film 112 having a thickness of 500 to 800 nm is formed as an interlayer insulating film on the entire surface by CVD, and heat treatment is performed for planarization. By this heat treatment, arsenic diffuses from the source / drain electrode 110 into the silicon substrate 100 to form a source / drain diffusion layer 113 (FIG. D).
[0019]
Finally, the contact hole 114 is opened, and the metal wiring 115 is formed.
[0020]
【The invention's effect】
As described above, according to the present invention, a gap having a small dielectric constant (1.0 and about 1/4 with respect to the relative dielectric constant 3.9 of the oxide film) is formed between the gate electrode and the drain electrode. Therefore, the parasitic capacitance between the electrodes is reduced. As a result, the driving capability of the MOS transistor is improved, and the circuit operation speed can be increased by a relatively simple manufacturing method.
[Brief description of the drawings]
FIG. 1 is a plan view of a MOS transistor showing an embodiment of the present invention.
2 is a vertical cross-sectional view of a manufacturing process along the AA ′ plane in FIG. 1; FIG.
3 is a vertical cross-sectional view of a manufacturing process along a BB ′ plane in FIG. 1; FIG.
FIG. 4 is a diagram illustrating an example of a conventional technique.
[Explanation of symbols]
100 P-type silicon substrate 101 Field shield oxide film 102 Field shield electrode 103 Cap oxide film 104 Side wall spacer oxide film 105 Gate oxide film 106 Gate electrode 107 Cap oxide film 108 Cap nitride film 109 Side wall spacer nitride film 110 Source / drain electrode 111 gap
112 BPSG film 113 Source / drain diffusion layer 114 Contact hole 115 Metal wiring 200 P-type silicon substrate 201 Field shield oxide film 202 Field shield electrode 203 Cap oxide film 204 Side wall spacer oxide film 205 Gate oxide film 206 Gate electrode 207 Cap oxide film 208 Sidewall spacer oxide film 209 Source / drain electrode 210 BPSG film 211 Source / drain diffusion layer 212 Contact hole 213 Metal wiring

Claims (4)

Forming a first insulating film, a first conductive film, and a second insulating film on a semiconductor substrate of a first conductivity type in order and patterning the first insulating film, a first conductive film, and a second insulating film; Forming a field shield element isolation structure through a step of forming and patterning the side wall spacers covering the side surfaces of the first insulating film, the first conductive film, and the second insulating film formed and patterned ; A fourth insulating film, a second conductive film, a fifth insulating film, and a sixth insulating film are sequentially formed in an active region isolated by the field shield element isolation structure and patterned to obtain a predetermined side covering the step of processing the shape, the patterned to form a seventh insulating film fourth insulating film, said second conductive film, the side surface of the fifth insulating film and the sixth insulating film Through the process of the Orusupesa, forming a gate structure of a MOS transistor, comprising the steps of a third conductive film is formed, processed into a predetermined shape by patterning, to form source / drain electrodes, the second insulating film, wherein the third insulating film and the fifth insulating film to selectively remove the sidewall spacer made of the sixth insulating film and the seventh insulating film, the gate A manufacturing method of a MOS transistor having a field shield element isolation structure, characterized by forming a gap between an electrode and the source / drain electrode.   2. The second insulating film, the third insulating film, and the fifth insulating film are silicon oxide films, and the sixth insulating film and the seventh insulating film are silicon nitride films. Of manufacturing a MOS transistor.   2. The method of manufacturing a MOS transistor according to claim 1, wherein the first conductive film and the second conductive film are polycrystalline silicon films doped with phosphorus as an N-type impurity.   2. The method of manufacturing a MOS transistor according to claim 1, wherein in the case of an N-type MOS transistor, the third conductive film is a polycrystalline silicon film doped with arsenic as an N-type impurity.

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