JP2858623B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a MOSFET (Metal Oxide Semico).
nductor Field Effect Transistor) and its manufacturing method.

[0002]

2. Description of the Related Art In a conventional MOSFET, as shown in FIG. 8, impurities are diffused into a substrate 1 to form a source region 2 and a drain region 3, and a gate electrode 5 is provided via a gate oxide film 4. Structure. When the MOSFET having such a structure is miniaturized, the distance between the source region 2 and the drain region 3 is reduced, and a punch-through phenomenon in which conduction occurs between them is caused. It was necessary to increase the concentration. As a result, the width of the depletion layer below the gate electrode 5 when a gate voltage is applied becomes narrower, and the vertical electric field at the interface with the gate oxide film 4 increases, so that the mobility of carriers decreases and the driving capability of the transistor decreases. Was causing it.

[0003] By the way, the power supply voltage of a MOSFET tends to decrease as the device is miniaturized, and accordingly, the threshold voltage also needs to be reduced. However, increasing the impurity concentration of the substrate 1 also increases the threshold voltage.
Therefore, an impurity of the conductivity type opposite to that of the substrate 1 is introduced into the surface of the substrate 1 to lower the apparent threshold voltage.

[0004]

When an impurity of the conductivity type opposite to that of the substrate 1 is introduced into the surface of the substrate 1, the apparent threshold voltage drops, but the drain current (0 V) when the gate voltage is 0 V is reduced. There is a problem that the leakage current value increases.

As can be seen from the graph of gate voltage-drain current shown in FIG. 9, the characteristic of the S coefficient indicating the gate voltage required to lower the drain current by one digit in the region below the threshold voltage is as follows. Although it depends on the impurity concentration of the substrate 1,
Since the impurity concentration of the substrate 1 did not change, the S coefficient did not change, and the leakage current increased when the threshold value was lowered in a simple order. Therefore, in order to lower the threshold current without increasing the leak current, it was necessary to lower the S coefficient at the same time.

When the impurity concentration of the substrate 1 is increased, the width of the depletion layer below the source region 2 and the drain region 3 is reduced, and the capacitance of each of the regions 2 and 3 is also increased. There was a problem that the speed was reduced. Therefore, an object of the present invention is to provide a semiconductor device and a method of manufacturing the same that have solved the above problems.

[0007]

As a means for achieving the above object, a gate electrode formed on a semiconductor substrate having a first conductivity type with a thin gate insulating film interposed therebetween, and a gate electrode formed below the gate insulating film. A source region and a drain region having a second conductivity type provided on both sides of the gate electrode, wherein the gate insulating film, the source region, and the drain region are provided below the gate insulating film. A second region having a second conductivity type formed in the substrate so as not to be in contact with the substrate; and a second region having a first conductivity type formed between the gate insulating film and the second region. A first region having a width smaller than a total width of a depletion layer formed when a voltage is applied to the gate electrode and a depletion layer formed by a pn junction with the second region; First
Each of which has a conductivity type between the second region and the source region and the drain region, and a width of a depletion layer formed by the source region and a depletion layer formed by a pn junction with the second region. The third with a width larger than the total width
And a step of implanting an impurity having a second conductivity type into a semiconductor substrate having a first conductivity type to form a second region,
Implanting an impurity having a first conductivity type into the semiconductor substrate to form a first region on the surface side of the second region, and forming a thin gate insulating film on the surface of the semiconductor substrate; Forming a gate electrode on the gate insulating film; and using the gate electrode as a mask, forming a first conductive layer for forming a third region to be higher than the impurity concentration of the second region. Implanting an impurity having a type into a position overlapping the second region; and implanting an impurity having a second conductivity type using the gate electrode as a mask to form a source region and a drain region. It is intended to provide a method of manufacturing a semiconductor device characterized by the following.

[0008]

FIG. 1 shows the structure of a MOSFET which is a first embodiment of the semiconductor device according to the present invention, and FIG. This MOSFET is
There is a region I having the same conductivity type as the substrate 11 below the gate electrode 15, and a region II having a conductivity type opposite to that of the substrate 11 below the region I. A region III having the same conductivity type as the substrate 11 is provided between the region II and the source region 12 and between the region II and the drain region 13. Note that the substrate 11 is a region IV. Therefore, if the substrate 11 is p-type, the regions I, III and IV are p-type,
I, the source region 12, and the drain region 13 are n-type.
When the substrate 11 is n-type, the conductivity types are opposite to each other.

Each area satisfies the following conditions. The width W1 in the depth direction of the region I is made smaller than the sum of the depletion layer width Wg due to the gate bias and the depletion layer width Wj1 due to the junction of the region II (W1 <Wg + Wj).
1). The width W2 in the depth direction of the region II is arbitrary. Region III
Is larger than the width W2 in the depth direction of the region II (W3> W2). Region III horizontal width W13
Is larger than the sum of the depletion layer width Wd of the drain region 13 in the region II and the depletion layer width Wj3 of the junction of the region II (W13> Wd + Wj3). Further, as a desirable condition, the substrate concentration N4 in the region IV is adjusted to all other regions I, II, II.
I is lower than the concentrations N1, N2, and N3 (N4 <N
1, N2, N3).

[0010] These conditions have the following effects. The region I is a channel region that is in an inverted state during operation and is in charge of carrier conduction. The threshold voltage of the MOSFET is controlled by the impurity concentration of the region I.

Since the region II has a pn junction with the region I, the region I is depleted by this junction. Therefore, the region II helps to deplete the region I when a voltage is applied to the gate electrode 15 and reduces the apparent capacitance as seen from the gate electrode 15. At the same time, the threshold voltage is reduced.

The region III prevents the depletion layer of the drain region 13 from spreading and the region II from conducting to the drain region 13. Further, the region III connects the region I and the region IV to stabilize the potential of the region I.

The impurity concentration of region IV determines the capacitance of source region 12 and drain region 13. Since the punch-through is prevented in the region III, the impurity concentration in the region IV can be determined without taking this into account. The impurity concentration in the region IV is reduced to reduce the capacitance of the source region 12 and the drain region 13.

Further, as shown in FIG. 3, due to the manufacturing process, a region below the source region 12 and the drain region 13 is formed.
III may be formed with a protruding structure (second embodiment). In this case, the source region 12 and the drain region 1
3 is in contact with the source region 12
When the width W3a of the protruding portion of the region III is smaller than the width Wd of the depletion layer of the drain (W3a <Wd), the depletion layer of the drain extends to the region IV. Therefore, even in this case, the capacitance of the source region 12 and the drain region 13 can be reduced.

The MOSFET having such a structure can be manufactured as follows. The manufacturing process is shown in FIGS.
It is shown in (D). First, as shown in FIG.
A sacrificial oxide film 14a is formed on the surface of the p-type substrate 11 having an impurity concentration of 1.5 × 10 ¹⁶ cm ^−3.
B (boron) at 25 KeV, 1.5
× 10 ¹² cm ^-2 , P (phosphorus) at 160 KeV, 2.5 × 10
^{When the} implantation is performed at ¹² cm ^−2, a layer 16 into which B is implanted as a region I is formed under the sacrificial oxide film 14a, and a layer 17 into which P is implanted as a region II is formed thereunder. .
The heat treatment is performed at the same time as the heat treatment for activating the source region 12 and the drain region 13 to be described later to form the regions I and II. At this point, the heat treatment is performed to reduce the effective impurity profile. Then, as shown in FIG. 5, the region I and the region II are sequentially arranged from the front surface side of the substrate 11.
Further, it can be seen that the region IV that is the substrate 11 is formed. The horizontal axis of the graph in FIG. 5 indicates the depth from the surface of the semiconductor, and the vertical axis indicates the effective impurity amount.

Then, as shown in FIG. 4B, B, P
After the implantation (without heat treatment), a gate oxide film (gate insulating film) 14 is reattached, and then a polysilicon thin film is formed and etched to form a gate electrode 15.

Next, the source region 12 and the drain region 1
Using the difference in the diffusion coefficient with the impurity used in region 3, the region II
Form I First, as shown in FIG. 3C, more B is implanted than P implanted into the region II so as to completely cover the region II using the gate electrode 15 as a mask.

Further, as shown in FIG. 2D, when As (arsenic) for forming the source region 12 and the drain region 13 is implanted in a larger amount than B and heat treatment is performed, the structure shown in FIG. As described above, B having a large diffusion coefficient diffuses more than As to form a region III, and the MOSFET as shown in FIG.
Can be manufactured.

The region III can be formed by another method. This method will be described with reference to FIGS. 4A to 4C are performed in the same manner, and FIG. 6A shows a state in which B is implanted using the gate electrode 15 as a mask. Then, as shown in FIG.
After forming a CVD insulating film 18 of SiO _{2 on} the surface, As for forming the source region 12 and the drain region 13 is implanted. At this time, C formed on the side surface of the gate electrode 15
Since As is implanted outside of B by an amount corresponding to the thickness of the VD insulating film 18, a portion corresponding to a region III is formed as shown in FIG. Then, when the heat treatment is finally performed, the MOSFET as shown in FIG. 1 can be manufactured.

In this method, the lateral width W13 of the region III can be changed by controlling the thickness of the CVD insulating film 18, so that the width of the region III can be reduced as compared with the case where the region III is formed only by diffusion. The lateral width W13 can be easily controlled.

FIG. 7 shows another method of forming the region III.
This will be described together with (A) and (B). First, FIG.
The same process is performed up to (B). Next, as shown in FIG. 7A, B is obliquely ion-implanted using the gate electrode 15 as a mask. By this oblique ion implantation, the gate electrode 1
B is also injected below 5. Thereafter, as shown in FIG. 3B, the source region 1 is formed using the gate electrode 15 as a mask.
When As for forming the drain region 2 and the drain region 13 is implanted, a region into which B serving as the region III has been implanted remains below the gate electrode. Then, when the heat treatment is finally performed, the MOSFET as shown in FIG. 1 can be manufactured. Again,
By controlling the oblique ion implantation, the lateral width W13 of the region III can be easily controlled.

A third embodiment of the semiconductor device according to the present invention will be described with reference to the drawings. FIG. 10 is a configuration diagram showing a third embodiment of the semiconductor device of the present invention, which has an LDD structure. The characteristics of this LDD structure are described in the serial number 40501060 “Semiconductor Device” (Heisei 5
(Filed on November 9, 2012). And
In the first embodiment, the lateral width of the region III is larger than the sum of the depletion layer width of the drain region 13 of the region II and the depletion layer width of the junction with the region II. In the example, the lateral width of the region III is smaller than the sum of the depletion layer width due to the drain region 23 of the region II and the depletion layer width due to the junction with the region II. The value is larger than the total width of the depletion layer due to the junction with II. In general, the width of the depletion layer due to the drain region 13 becomes larger than the width of the depletion layer due to the source region 12 due to the action of the drain voltage. .

The structure of the MOSFET shown in FIG. 10 will be briefly described. Non-conductive side spacers 26 are provided on both sides of a gate electrode 25, and a substrate 21 is provided under the gate electrode 25 with a gate oxide film 24 interposed therebetween. There is a region I having the same conductivity type as. Then, there is a region II having a conductivity type opposite to that of the substrate 21 therebelow. A region III having the same conductivity type as the substrate 21 is provided between the region II and the source region 22 and between the region II and the drain region 23, respectively.
There is. Further, an LDD region 27 is formed between the region I and the source region 22 and between the region I and the drain region 23. Note that the substrate 21 is a region IV. Therefore, if the substrate 21 is p-type, the regions I, III, and IV are p-type, and the region II, the source region 22, and the drain region 2
3. The LDD region 27 becomes n-type. Further, when the substrate 21 is n
In the case of the molds, they have opposite conductivity types.

FIG. 11 shows a method of manufacturing this MOSFET.
This will be described together with (A) to (F). First, as shown in FIG. 3A, the impurity concentration in the region IV is 1.5 × 10 ¹⁶ cm ^−3.
A sacrificial oxide film 24a having a thickness of 500 A (angstrom) is formed on the surface of the p-type substrate 21 of FIG.
B (boron) is injected into the substrate 21 through a.
After implanting at an implantation amount of 6.8 × 10 ¹² cm ⁻² , P (phosphorus) is implanted at an implantation voltage of 105 KeV and an implantation amount of 6.3 × 10 ¹² cm ^−2.
When the implantation is performed at cm ⁻² , the implanted layer 28 of B serving as the region I is formed under the sacrificial oxide film 24 a, and further, the implanted layer 29 of P serving as the region II is formed thereunder. .
Note that the heat treatment of the impurity is performed in a source region 22 described later.
And heat treatment for activating the drain region 23 to form regions I and II.

Then, as shown in FIG.
, After removing the sacrificial oxide film 24a,
The gate oxide film 24 is re-attached to form a polysilicon thin film, which is then etched to form an n-type semiconductor having a width of 0.4 μm.
^{A +} type polysilicon gate electrode 25 is formed. Further, as shown in FIG. 3C, B is injected into the depth position where the region II is formed by using the gate electrode 25 as a mask and an injection voltage 4 is applied.
Injection is performed at 0 KeV and an injection amount of 5.0 × 10 ¹² cm ^−2.
To form Thereafter, as shown in FIG. 3D, As (arsenic) is implanted at an implantation voltage of 25 KeV and an implantation amount of 4.0 × 10 ¹³ cm ^{−2 using} the gate electrode 25 as a mask, to thereby form a layer into which B has been implanted. An n ⁻ layer 30 to be an LDD region 27 is formed on the surface side of 28.

Then, as shown in FIG.
2 μm side spacers 26 are formed on both sides of the gate electrode 25. The side spacer 26 can be formed by forming an SiO ₂ film on the entire surface and performing anisotropic etching such as RIE. In this state, as shown in FIG. 2F, As is implanted at an implantation voltage of 50 KeV and an implantation amount of 4.0 × 10 ¹³ cm ^{−2 using} the gate electrode 25 and the side spacer 26 as a mask, and the n ⁻ layer is formed. The source region 22 and the drain region 23 are formed outside the lower side of the side spacer 26 of the layer 28 into which 30 and B are implanted. Finally, by performing a heat treatment at 900 ° C. for 40 minutes, a MOSFET as shown in FIG. 10 can be manufactured.

The MOSF thus manufactured is
Gate voltage, source voltage and substrate voltage are all 0 in ET
FIG. 12 shows a potential distribution diagram based on the potential of intrinsic silicon when a drain voltage of 2 (V) is applied as (V). It should be noted that the numerals used in the figure are the numbers for indicating the contour lines of the potential shown on the right side of the figure, and are different from the reference numerals used in other figures. As can be seen from the figure, in the region II, the potential on the drain side is higher than the potential on the source side due to the influence of the drain voltage. However, since the potential of the region III near the source side is stable, the potential of the channel is also stable through the region III on the source side. As a result, no problem occurs in the characteristics of the MOSFET.

FIG. 13 shows the flow of a hole (substrate current) generated by hot electrons near the drain. In this MOSFET, since the region III is not depleted on the source side and is electrically connected to the region I, the hole generated in the drain region 23 travels along the boundary with the region II to reach the region III on the source side. Through to the substrate 21. The existence of this path prevents a kink effect in which holes accumulate in the channel region of the region I, the potential of the channel rises, and the drain current rises abnormally.

Therefore, in the first embodiment, the drain-side region III is prevented from being depleted. However, as in the third embodiment, the drain-side region III is depleted and the region II and the drain III are not depleted. Even if the connection with the region 23 is made, the characteristics of the MOSFET are stabilized unless the region III on the source side is depleted. In other words, the width of the region III may be a value larger than the sum of the width of the depletion layer formed by the source region 22 and the width of the depletion layer formed by the junction with the region II, regardless of the width of the depletion layer formed by the drain region 23. The degree of freedom in designing a semiconductor device can be increased.

[0030]

According to the semiconductor device of the present invention, even when the semiconductor device is miniaturized, the threshold voltage can be lowered without increasing the impurity concentration of the substrate. Can be.

Further, since the width of the depletion layer below the source region and the drain region does not decrease, the semiconductor device can be miniaturized without increasing the delay time or lowering the operation speed.

Further, the method of manufacturing a semiconductor device according to the present invention has an effect that a miniaturized semiconductor device having good characteristics can be manufactured.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment of a semiconductor device of the present invention.

FIG. 2 is an enlarged view of a main part showing a main part of the first embodiment shown in FIG. 1;

FIG. 3 is a configuration diagram showing a second embodiment of the semiconductor device of the present invention.

FIGS. 4A to 4E are process diagrams for explaining one embodiment of a method of manufacturing a semiconductor device according to the present invention.

FIG. 5 is a graph showing an effective impurity profile when heat treatment is performed from the state of FIG.

FIGS. 6A to 6C are process diagrams for explaining another embodiment of a method for forming a region III.

FIGS. 7A and 7B are process diagrams for explaining still another embodiment of a method for forming a region III.

FIG. 8 is a configuration diagram showing a conventional example.

FIG. 9 is a graph showing a relationship between gate voltage and drain current in a conventional example.

FIG. 10 is a configuration diagram showing a third embodiment of the semiconductor device of the present invention.

FIGS. 11A to 11F are process diagrams for explaining a method of manufacturing the semiconductor device according to the third embodiment of the present invention shown in FIG. 10;

FIG. 12 is a diagram showing a potential distribution of the third embodiment.

FIG. 13 is a diagram showing a flow of holes generated by hot electrons according to the third embodiment.

[Explanation of symbols]

1,11,21 substrate 2,12,22 source region 3,13,23 drain region 4,14,24 gate oxide film (gate insulating film) 5,15,25 gate electrode 14a, 24a sacrificial oxide film 16,28B Implanted layer (region I) 17, 29 P implanted layer (region II) 18 CVD insulating film 26 side spacer 27 LDD region 30 n ^- layer

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 29/78

Claims (6)

(57) [Claims] 1. A gate electrode formed on a semiconductor substrate having a first conductivity type with a thin gate insulating film interposed therebetween, and second conductive layers provided below the gate insulating film and on both sides of the gate electrode. Source and drain regions having a mold;
A second region having a second conductivity type formed in the substrate below the gate insulating film so as not to contact the gate insulating film and the source region and the drain region. A width of a depletion layer formed between the gate insulating film having the first conductivity type and the second region and formed when a voltage is applied to the gate electrode; A first region having a width smaller than a total width of a depletion layer formed by a pn junction with the region, and a second region having a first conductivity type and the source region and the drain region. Between the depletion layer width due to the source region and the pn between the second region.
A third region having a width larger than the sum of the width of the depletion layer due to the junction. 2. The semiconductor device according to claim 1, wherein the impurity concentration in the third region is higher than the impurity concentration in the second region. 3. The semiconductor device according to claim 1, wherein the impurity concentration of the substrate is lower than the impurity concentration of the third region, and at least a depletion layer formed by the drain region reaches the substrate. Semiconductor device. 4. A step of implanting an impurity having a second conductivity type into a semiconductor substrate having a first conductivity type to form a second region, and an step of implanting an impurity having a first conductivity type into the semiconductor substrate. Implanting to form a first region closer to the surface than the second region, forming a thin gate insulating film on the surface of the semiconductor substrate, and forming a gate electrode on the gate insulating film And a step of using the gate electrode as a mask to overlap an impurity having a first conductivity type for forming a third region with the second region so as to be higher than an impurity concentration of the second region. And forming a source region and a drain region by implanting an impurity having a second conductivity type using the gate electrode as a mask. 5. The method of manufacturing a semiconductor device according to claim 4, wherein an insulating film is formed on the semiconductor substrate and the gate electrode.
The width of the third region is controlled by the thickness of the insulating film by implanting an impurity having a second conductivity type to form a source region and a drain region. Production method. 6. A method for manufacturing a semiconductor device according to claim 4, wherein an impurity having a first conductivity type for forming a third region is implanted at a position overlapping the second region by oblique ion implantation. A method of manufacturing a semiconductor device.