JPH0794723A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PURPOSE:To reduce a threshold voltage without increasing a leak current in a fine patterning step. CONSTITUTION:A conductive region (I) of the same conductive type as that of the substrate 11 is provided under a gate, electrode 15 and a conductive region (II) of the opposite type to that of the substrate 11 is provided under the conductive region (I). Each conductive region (III) of the same conductive type as that of the substrate 11 is provided between a source region 12 and the conductive region (II) and between a drain region 13 and the conductive region (II). In addition, the substrate 11 is used as a region (IV).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a MOSFET (Metal Oxide Semico
nductor Field Effect Transistor) and its manufacturing method.

[0002]

2. Description of the Related Art In a conventional MOSFET, as shown in FIG. 8, impurities are diffused in a substrate 1 to form a source region 2 and a drain region 3, and a gate electrode 5 is provided via a gate oxide film 4. It has a different structure. When the MOSFET having such a structure is miniaturized, the distance between the source region 2 and the drain region 3 becomes narrower, and a punch-through phenomenon occurs in which conduction occurs between them. Therefore, in order to prevent this, impurities on the substrate 1 are prevented. It was necessary to increase the concentration. Therefore, when the gate voltage is applied, the width of the depletion layer under the gate electrode 5 becomes narrow, and the vertical electric field at the interface of the gate oxide film 4 increases, so that the mobility of carriers decreases and the driving capability of the transistor decreases. Was the cause.

By the way, the power supply voltage of the MOSFET tends to decrease as it is miniaturized, and the threshold voltage must be decreased accordingly. However, if the impurity concentration of the substrate 1 is increased, the threshold voltage also increases.
Therefore, an impurity having a conductivity type opposite to that of the substrate 1 is introduced into the surface of the substrate 1 to reduce the apparent threshold voltage.

[0004]

When impurities of the conductivity type opposite to that of the substrate 1 are introduced into the surface of the substrate 1, the apparent threshold voltage decreases, but the drain current (when the gate voltage is 0 V There was a problem that the (leakage current) value would increase.

As can be seen from the graph of gate voltage-drain current shown in FIG. 9, the characteristic of the S coefficient showing the gate voltage required to lower the drain current by one digit in the region below the threshold voltage is Depending on the impurity concentration of the substrate 1,
Since the impurity concentration of the substrate 1 did not change, the S coefficient did not change, and if the threshold value was simply lowered, the leak current would increase. Therefore, in order to decrease the threshold current without increasing the leak current, it is necessary to decrease the S coefficient at the same time.

Further, if the impurity concentration of the substrate 1 is increased, the width of the depletion layer under the source region 2 and the drain region 3 is also reduced, and the capacitance of each of the regions 2 and 3 is also increased. There was a problem that the speed decreased. Therefore, it is an object of the present invention to provide a semiconductor device and a method of manufacturing the same that solve the above problems.

[0007]

As means for achieving the above object, a gate electrode formed on a semiconductor substrate having a first conductivity type with a thin gate insulating film sandwiched between the gate electrode and a gate electrode below the gate insulating film. And a source region and a drain region having a second conductivity type provided on both sides of the gate electrode, the gate insulating film, the source region, and the drain region below the gate insulating film. Between the gate insulating film and the second region having the first conductivity type and the second region having the second conductivity type formed in the substrate so as not to come into contact with the second region. A first region having a width smaller than the sum of the width of the depletion layer formed when a voltage is applied to the gate electrode and the width of the depletion layer formed by the pn junction with the second region; First
Of the depletion layer formed by the source region and the depletion layer formed by the pn junction with the second region. A third width greater than the sum of the width and
And a region for forming a second region by implanting an impurity having a second conductivity type into a semiconductor substrate having a first conductivity type.
Injecting an impurity having a first conductivity type into the semiconductor substrate to form a first region on the surface side of the second region, and forming a thin gate insulating film on the semiconductor substrate surface. And a step of forming a gate electrode on the gate insulating film, and using the gate electrode as a mask, a first conductive film for forming the third region so as to have a higher impurity concentration than the second region. Implanting an impurity having a type into a position overlapping the second region, and implanting an impurity having a second conductivity type with the gate electrode as a mask to form a source region and a drain region. An object of the present invention is to provide a method for manufacturing a semiconductor device characterized by the above.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the structure of a MOSFET which is a first embodiment of the semiconductor device of the present invention is shown in FIG. 1, and an enlarged view of the essential parts thereof is shown in FIG. This MOSFET is
Below the gate electrode 15 is a region I having the same conductivity type as that of the substrate 11, and below that is a region II having a conductivity type opposite to that of the substrate 11. Further, between the region II and the source region 12 and between the region II and the drain region 13, there are regions III having the same conductivity type as the substrate 11, respectively. It should be noted that the substrate 11 is defined as a region IV. Therefore, if the substrate 11 is p-type, the regions I, III, and IV are p-type, and the region I
I, the source region 12, and the drain region 13 are n-type.
When the substrate 11 is n-type, the conductivity types are opposite to each other.

Each area satisfies the following conditions. The width W1 in the depth direction of the region I is smaller than the total of the depletion layer width Wg due to the gate bias and the depletion layer width Wj1 due to the junction of the region II (W1 <Wg + Wj.
1). The width W2 in the depth direction of the region II is arbitrary. Area III
The width W3 in the depth direction is larger than the width W2 in the depth direction of the region II (W3> W2). Region III lateral width W13
Is larger than the sum of the depletion layer width Wd due to the drain region 13 in the region II and the depletion layer width Wj3 due to the junction with the region II (W13> Wd + Wj3). Furthermore, as a desirable condition, the substrate concentration N4 in the region IV is set to all other regions I, II, II.
The concentration of I is made thinner than N1, N2, N3 (N4 <N
1, N2, N3).

Each of such conditions has the following effects. The region I is a channel region that is in an inverted state during operation and is in charge of carrier conduction. The threshold voltage of this MOSFET is controlled by the impurity concentration in the region I.

Since the region II has a pn junction with the region I, the region I is depleted by this junction. Therefore, the region II helps depletion of the region I when a voltage is applied to the gate electrode 15, and reduces the apparent capacitance seen from the gate electrode 15. At the same time, the threshold voltage is reduced.

The region III prevents the depletion layer of the drain region 13 from spreading and the region II and the drain region 13 from conducting. Further, the region III connects the regions I and IV to stabilize the potential of the region I.

The impurity concentration of the region IV determines the capacitance of the source region 12 and the drain region 13. Since the punch-through is prevented by the region III, the impurity concentration of the region IV can be determined without taking this into consideration, and the impurity concentration of the source region 12 and the drain region 13 is made low to reduce the capacitance.

Further, as shown in FIG. 3, due to the manufacturing process, a region below the source region 12 and the drain region 13 is formed.
Sometimes III is formed in a protruding structure (second embodiment). In this case, the source region 12 and the drain region 1
The impurity concentration of the region III in contact with the source region 3 is
And the capacitance of the drain region 13 is determined. When the width W3a of the protruding portion of the region III in the depth direction is smaller than the drain depletion layer width Wd (W3a <Wd), the drain depletion layer extends to the region IV. Therefore, even in this case, the capacities of the source region 12 and the drain region 13 can be reduced.

The MOSFET having such a structure can be manufactured as follows. The manufacturing process is shown in FIG.
It shows in (D). First, as shown in FIG.
The sacrificial oxide film 14a is formed on the surface of the p-type substrate 11 having an impurity concentration of 1.5 × 10 ¹⁶ cm ^−3.
B (boron) of 25 KeV, 1.5 on the substrate 11 through a
× 10 ¹² cm ^-2 , P (phosphorus) at 160 KeV, 2.5 × 10
^{After the} implantation of ¹² cm ^-2, a layer 16 of B which is a region I and a layer 16 of P that is a region II are formed under the sacrificial oxide film 14a. .
Then, the heat treatment is performed simultaneously with the heat treatment for activating the source region 12 and the drain region 13, which will be described later, to form the regions I and II. At this point, the heat treatment is performed to obtain the effective impurity profile. Then, as shown in FIG. 5, the region I and the region II are sequentially arranged from the front surface side of the substrate 11.
It can be seen that the region IV which is the substrate 11 is formed. The horizontal axis of the graph of FIG. 5 represents the depth from the surface of this semiconductor, and the vertical axis represents the effective impurity amount.

Then, as shown in FIG. 4B, B, P
After implantation (without heat treatment), the gate oxide film (gate insulating film) 14 is reattached, and then a polysilicon thin film is formed and etched to form the gate electrode 15.

Next, the source region 12 and the drain region 1
Utilizing the difference in diffusion coefficient from the impurities used in No. 3,
Form I. First, as shown in FIG. 3C, a larger amount of B than P injected into the region II is injected so as to completely cover the region II using the gate electrode 15 as a mask.

Further, as shown in FIG. 6D, when a larger amount of As (arsenic) for forming the source region 12 and the drain region 13 is implanted than in B and heat treatment is performed, the result is shown in FIG. As described above, B having a large diffusion coefficient diffuses more than As to form the region III, and the MOSFET as shown in FIG.
Can be manufactured.

The region III can also be formed by another method. This method will be described with reference to FIGS. First, FIG. 6A shows a state in which B is implanted using the gate electrode 15 as a mask in the same manner as in FIGS. 4A to 4C. Then, as shown in FIG.
After the CVD insulating film 18 of SiO ₂ is formed on the surface, As for forming the source region 12 and the drain region 13 is injected. At this time, C formed on the side surface of the gate electrode 15
Since As is injected to the outside of B by the thickness of the VD insulating film 18, a region III is formed as shown in FIG. Then, by finally performing heat treatment, a MOSFET as shown in FIG. 1 can be manufactured.

According to this method, the lateral width W13 of the region III can be changed by controlling the film thickness of the CVD insulating film 18, so that the region III of the region III can be formed as compared with the case where the region III is formed only by diffusion. The lateral width W13 can be easily controlled.

Further, another method for forming the region III is shown in FIG.
This will be described together with (A) and (B). First, FIG. 4 (A),
It is manufactured in the same manner up to (B). Next, as shown in FIG. 7A, B is obliquely ion-implanted using the gate electrode 15 as a mask. By this oblique ion implantation, the gate electrode 1
B is also injected into the lower side of 5. After that, as shown in FIG. 3B, the source region 1 is formed using the gate electrode 15 as a mask.
When 2 and As for forming the drain region 13 are implanted, a region in which B to be the region III is implanted remains under the gate electrode. Then, by finally performing heat treatment, a MOSFET as shown in FIG. 1 can be manufactured. Also in this case,
The lateral width W13 of the region III can be easily controlled by controlling the oblique ion implantation.

A third embodiment of the semiconductor device of the present invention will be described with reference to the drawings. FIG. 10 is a configuration diagram showing a third embodiment of the semiconductor device of the present invention, which has an LDD structure. The characteristics of this LDD structure are as follows: Reference number 405001060 “Semiconductor device” (1993)
(Filed on November 9, 2012). And
In the first embodiment, the lateral width of the region III is larger than the total width of the depletion layer formed by the drain region 13 and the junction of the region II in the region II. In the example, the lateral width of the region III is smaller than the sum of the depletion layer width due to the drain region 23 of the region II and the depletion layer width due to the junction with the region II, but the width of the depletion layer due to the source region 22 of the region II and the region The value is larger than the total width of the depletion layer due to the junction with II. Generally, due to the action of the drain voltage, the width of the depletion layer due to the drain region 13 is larger than the width of the depletion layer due to the source region 12, so that it can be set to the lateral width of the region III as in this embodiment. .

The structure of the MOSFET shown in FIG. 10 will be briefly described. Non-conductive side spacers 26 are provided on both sides of the gate electrode 25, and the substrate 21 is provided below the gate electrode 25 via the gate oxide film 24. There is a region I having the same conductivity type as. Below that, there is a region II having a conductivity type opposite to that of the substrate 21. Further, between the region II and the source region 22 and between the region II and the drain region 23, a region III having the same conductivity type as that of the substrate 21 is provided.
There is. Further, LDD regions 27 are formed between the regions I and the source regions 22 and between the regions I and the drain regions 23. The substrate 21 will be referred to as a region IV. Therefore, if the substrate 21 is p-type, the regions I, III, and IV are p-type, and the region II, the source region 22, and the drain region 2 are
3, the LDD region 27 becomes n-type. In addition, the substrate 21 is n
In the case of molds, the conductivity types are opposite to each other.

A method for manufacturing this MOSFET is shown in FIG.
This will be described together with (A) to (F). First, as shown in FIG. 3A, the impurity concentration of the region IV is 1.5 × 10 ¹⁶ cm ^−3.
A sacrificial oxide film 24a having a thickness of 500 A (angstrom) is formed on the surface of the p-type substrate 21 of FIG.
Inject B (boron) into the substrate 21 through a. Voltage 25 KeV
, With an implantation amount of 6.8 × 10 ¹² cm ^-2 , and then with P (phosphorus) at an implantation voltage of 105 KeV with an implantation amount of 6.3 × 10 ¹²
When the implantation is performed at cm ⁻² , a layer 28 of B which is the region I and a layer 28 of P that is the region II are formed below the sacrificial oxide film 24 a. .
The heat treatment of the impurities is performed by the source region 22 described later.
And simultaneously with the heat treatment for activating the drain region 23, regions I and II are formed.

Then, as shown in FIG.
After the sacrificial oxide film 24a is removed after the implantation of
The gate oxide film 24 is reattached to form a polysilicon thin film, which is then etched to obtain an n-type film having a width of 0.4 μm.
^{A +} type polysilicon gate electrode 25 is formed. Further, as shown in FIG. 7C, B is injected at a depth position where the region II is formed using the gate electrode 25 as a mask.
Implanted at 0 KeV and dose of 5.0 × 10 ¹² cm ^-2 ,
To form. Then, as shown in FIG. 3D, with the gate electrode 25 as a mask, As (arsenic) is implanted at an implantation voltage of 25 KeV and an implantation amount of 4.0 × 10 ¹³ cm ⁻² , and the layer in which B is implanted. An n ⁻ layer 30 to be the LDD region 27 is formed on the surface side of 28.

Then, as shown in FIG.
2 μm side spacers 26 are formed on both sides of the gate electrode 25. The side spacers 26 can be formed by forming a SiO ₂ film on the entire surface and performing anisotropic etching such as RIE. In this state, as shown in FIG. 6F, As was implanted at an implantation voltage of 50 KeV and an implantation amount of 4.0 × 10 ¹³ cm ^{-2 using} the gate electrode 25 and the side spacers 26 as a mask, and the n ⁻ layer was formed. The source region 22 and the drain region 23 are formed outside the underside of the side spacer 26 of the layer 28 into which 30 and B are implanted. Finally, by performing heat treatment at 900 ° C. for 40 minutes, a MOSFET as shown in FIG. 10 can be manufactured.

Then, the MOSF thus manufactured
Gate voltage, source voltage, and substrate voltage are all 0 in ET
FIG. 12 shows a potential distribution diagram based on the potential of intrinsic silicon when a drain voltage of 2 (V) is applied as (V). The numbers used in the figure are numbers for showing the contour lines of the potential shown on the right side of the figure, and are different from the reference numerals used in the other figures. As can be seen from the figure, in the region II, the drain side potential is higher than the source side potential due to the influence of the drain voltage. However, since the potential of the region III near the source side is stable, the potential of the channel is also stable through the region III on the source side. As a result, there is no problem in the characteristics of the MOSFET.

FIG. 13 shows the flow of holes (substrate current) generated by hot electrons near the drain. In this MOSFET, the region III is not depleted on the source side and is electrically connected to the region I. Therefore, the holes generated in the drain region 23 advance along the boundary with the region II and the region III on the source side. Through the substrate 21. The existence of this path prevents holes from accumulating in the channel region of the region I, increasing the potential of the channel, and causing a kink effect in which the drain current abnormally increases.

Therefore, in the first embodiment, the region III on the drain side is prevented from being depleted, but as in the third embodiment, the region III on the drain side is depleted and the region II and the drain are drained. Even if the region 23 is connected, the characteristics of the MOSFET are stable unless the region III on the source side is depleted. In other words, the width of the region III may be larger than the sum of the depletion layer width of the source region 22 and the depletion layer width of the junction of the region II, regardless of the depletion layer width of the drain region 23. The degree of freedom in designing the semiconductor device can be increased.

[0030]

According to the semiconductor device of the present invention, the threshold voltage can be lowered without raising the impurity concentration of the substrate even when miniaturized, so that leak current does not increase and good characteristics can be obtained. You can

Further, since the width of the depletion layer under the source region and the drain region is not reduced, the semiconductor device can be miniaturized without increasing the delay time and lowering the operation speed.

Further, the method of manufacturing a semiconductor device of the present invention has an effect that a miniaturized semiconductor device having good characteristics can be manufactured.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a first embodiment of a semiconductor device of the present invention.

FIG. 2 is an enlarged view of an essential part showing an essential part of the first embodiment shown in FIG.

FIG. 3 is a configuration diagram showing a second embodiment of the semiconductor device of the present invention.

4A to 4E are process drawings for explaining one embodiment of the method for manufacturing a semiconductor device of the present invention.

FIG. 5 is a graph showing an effective impurity profile when heat treatment is performed from the state of FIG.

6A to 6C are process charts for explaining another embodiment of the method for forming the region III.

7A and 7B are process drawings for explaining still another embodiment of the method for forming the region III.

FIG. 8 is a configuration diagram showing a conventional example.

FIG. 9 is a graph showing the relationship between gate voltage and drain current in a conventional example.

FIG. 10 is a configuration diagram showing a third embodiment of the semiconductor device of the present invention.

11A to 11F are process drawings for explaining the manufacturing method of the third embodiment of the semiconductor device of the present invention shown in FIG.

FIG. 12 is a diagram showing a potential distribution of the third embodiment.

FIG. 13 is a diagram showing a flow of holes generated by hot electrons according to the third embodiment.

[Explanation of symbols]

1, 11, 21 Substrate 2, 12, 22 Source region 3, 13, 23 Drain region 4, 14, 24 Gate oxide film (gate insulating film) 5, 15, 25 Gate electrode 14a, 24a Sacrificial oxide film 16, 28 B Injected layer (region I) 17, 29 P Injected layer (region II) 18 CVD insulating film 26 Side spacer 27 LDD region 30 n ^- layer

Claims (6)

[Claims] 1. A gate electrode formed by sandwiching a thin gate insulating film on a semiconductor substrate having a first conductivity type, and a second conductivity provided below the gate insulating film on both sides of the gate electrode. A source region and a drain region having a mold;
A second region having a second conductivity type formed in the substrate so as not to contact the gate insulating film and the source region and the drain region below the gate insulating film. A width of a depletion layer having a first conductivity type and formed between the gate insulating film and the second region when a voltage is applied to the gate electrode; A first region having a width smaller than a total width of a depletion layer formed by a pn junction with the region, and the second region having the first conductivity type, the source region and the drain region. Pn between the depletion layer formed by the source region and the second region
And a third region having a width larger than the total width of the depletion layers formed by the junction. 2. The semiconductor device according to claim 1, wherein the impurity concentration of the third region is higher than the impurity concentration of the second region. 3. The semiconductor device according to claim 1, wherein the impurity concentration of the substrate is lower than the impurity concentration of the third region, and at least the depletion layer due to the drain region reaches the substrate. Semiconductor device. 4. A step of implanting an impurity having a second conductivity type into a semiconductor substrate having a first conductivity type to form a second region, and the step of implanting an impurity having a first conductivity type into the semiconductor substrate. Injecting to form a first region on the surface side of the second region, forming a thin gate insulating film on the surface of the semiconductor substrate, and forming a gate electrode on the gate insulating film. And a position where an impurity having a first conductivity type for forming a third region is overlapped with the second region so that the impurity concentration of the second region is higher than that of the second region by using the gate electrode as a mask. And a step of implanting an impurity having a second conductivity type by using the gate electrode as a mask to form a source region and a drain region. 5. The method of manufacturing a semiconductor device according to claim 4, wherein an insulating film is formed on the semiconductor substrate and the gate electrode,
A semiconductor device characterized in that the width of the third region is controlled by the film thickness of the insulating film by implanting an impurity having the second conductivity type to form a source region and a drain region. Production method. 6. The method of manufacturing a semiconductor device according to claim 4, wherein an impurity having the first conductivity type for forming the third region is implanted at a position overlapping the second region by using oblique ion implantation. A method of manufacturing a semiconductor device, characterized in that.