JP2004039773A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve an operating breakdown voltage of a high breakdown voltage MOS transistor by suppressing the action of a parasitic bipolar transistor. <P>SOLUTION: A region p+-type buried layer 7 is disposed under an n+-type source layer 13. This buried layer 7 lowers the resistance of a region under an n+-type source layer 12. Thus, holes formed in the end of an n-type first drain layer 4 are rapidly absorbed by the layer 12 formed on the surface of a body layer 3 adjacent to the layer 7 and an n+-type source layer, and radiated out of the high breakdown transistor through a source electrode 16. Then, since a rise in the potential of the layer 3 is suppressed, the parasitic npn-type bipolar transistor is hardly turned on. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a DMOS (Diffused MOS) type high breakdown voltage transistor built in a semiconductor integrated circuit.
[0002]
[Prior art]
A high breakdown voltage MOS transistor has a high source / drain breakdown voltage (BVDS) or a high gate breakdown voltage, and is applied to an LCD driver, an EL driver, a power supply circuit, and the like.
[0003]
FIG. 11 is a cross-sectional view showing the structure of a conventional DMOS type N-channel high breakdown voltage transistor.
[0004]
An N-type well region 101 is formed on the surface of a P-type silicon substrate 100. A gate oxide film 103 and thick field oxide films 104A and 104B are formed on the surface of the P-type body region 102 on the surface of the well region 101. Is formed. Then, a gate electrode 105 extending from the gate oxide film 103 to a part of the adjacent field oxide film 104A is formed.
[0005]
An N + type source layer 106 is formed on the surface of the body layer 102 adjacent to one end of the gate electrode 105. Further, a P + layer 107 for fixing the potential of the body layer 102 is formed adjacent to the N + type source layer 106.
[0006]
Further, an N-type first drain layer 108 is formed in a surface region of the well region 101 and a region partially overlapping the surface of the body layer 102. Further, an N + type second drain layer 109 disposed on the surface of the N type first drain layer 108 is formed apart from the other end of the gate electrode 105.
[0007]
According to the above high breakdown voltage MOS transistor structure, when a high voltage is applied to the second drain layer 109, the depletion layer spreads in the N-type well region 101 and the body layer 102, and the drain electric field is relaxed. Source / drain breakdown voltage can be obtained. Further, since the N-type first drain layer 108 is provided, the on-resistance of the transistor can be reduced. In addition, since the gate electrode 105 extends from the gate oxide film 103 to a part of the adjacent field oxide film 104A, the gate electrode 105 has a structure that is strong against destruction of the gate oxide film 103.
[0008]
[Problems to be solved by the invention]
However, the above-mentioned conventional high breakdown voltage transistor has a problem that the operating breakdown voltage is low. Here, the operating breakdown voltage refers to the breakdown voltage between the source and the drain when the high breakdown voltage transistor is on and a channel current is flowing.
[0009]
[Means for Solving the Problems]
The cause is as follows according to the study by the present inventors. In FIG. 11, when a drain voltage is applied to the N + type second drain layer 109 and a gate voltage higher than a threshold voltage is applied to the gate electrode 105, the N + type source layer 106 and the N type first drain layer 108 , A channel current (electron current) flows in the channel region CH. When the drain voltage increases, the electric field at the end of the N-type first drain layer 108 increases, and electron-hole pairs are generated by impact ionization. The holes generated at the end of the N-type first drain layer 108 are released into the body layer 102 and become a drift current. Then, the potential of the body layer 102 increases.
[0010]
On the other hand, as shown in FIG. 11, a parasitic NPN-type bipolar transistor is formed. The emitter of the parasitic NPN bipolar transistor is an N + type source layer 106, the base is a P type body layer 102, and the collector is an N type well region 101.
[0011]
When holes generated at the end of the N-type first drain layer 108 are released into the body layer 102 and the potential of the body layer 102 increases, the base potential of the parasitic NPN bipolar transistor increases. Conventionally, a P + layer 107 for fixing the potential of the body layer 102 is formed adjacent to the N + type source layer 106, but this is insufficient to fix the potential of the body layer 102, and the parasitic NPN The bipolar transistor turns on.
[0012]
Then, a large parasitic current flows between the N + type second drain layer 109 and the N + type source layer 106. Therefore, the operating withstand voltage of the high withstand voltage transistor decreases.
[0013]
Therefore, in the present invention, as shown in FIG. 9, a P + type buried layer 7 for absorbing holes generated inside a high breakdown voltage transistor is arranged in a region below an N + type source layer 12. It is. The P + type buried layer 7 lowers the resistance of the region below the N + type source layer 13.
[0014]
Therefore, holes generated inside the high-breakdown-voltage transistor are quickly absorbed through the P + -type buried layer 7 and the P + -type layer 12 formed on the surface of the body layer 3 adjacent to the N + -type source layer. Released outside the transistor. Then, an increase in the potential of the body layer 3 is suppressed, so that the parasitic NPN-type bipolar transistor is less likely to be turned on. Thereby, the operating withstand voltage of the high withstand voltage transistor is improved.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, the semiconductor device and the method for fabricating the semiconductor device according to the first embodiment of the present invention will be described with reference to the drawings.
[0016]
First, as shown in FIG. 1, an N-type well region 2 is formed on a surface of a P-type silicon substrate 1 by ion implantation and thermal diffusion. Here, the ion implantation is performed, for example, under the conditions of phosphorus ( ³¹ P ⁺ ) at an acceleration energy of 140 to 160 KeV and a dose of 5 × 10 ¹² / cm ² . Thereafter, thermal diffusion is performed at 1200 ° C. for about 15 hours.
[0017]
Next, as shown in FIG. 2, a P-type body layer 3 and an N-type first drain layer 4 are formed. The N-type first drain layer 4 partially overlaps the surface of the P-type body layer 3. Here, the ion implantation for forming the P-type body layer 3 is performed by using a photoresist layer (not shown) as a mask, for example, using boron ( ¹¹ B ⁺ ) at an acceleration energy of 80 KeV and a dose amount of 1.5 × 10 ¹³ / cm ² . Perform under conditions. The ion implantation for the first drain layer 4 formed of N-type, an acceleration energy 160KeV as a mask a photoresist layer (not shown), for example, arsenic ⁽⁷⁵ As ^+), dose amount 2 × ¹⁰ 12 / ^cm 2, Subsequently, phosphorus ( ³¹ P ⁺ ) is performed under the conditions of an acceleration energy of 100 KeV and a dose of 1 × 10 ¹² / cm ² . After the above ion implantation, thermal diffusion is performed at 1100 ° C. for about 4 hours.
[0018]
Next, as shown in FIG. 3, a second ion implantation is performed on the P-type body layer 3 using the photoresist layer 5 as a mask. This is to prevent the short channel effect of the high breakdown voltage transistor by increasing the concentration of the channel region CH of the P-type body layer 3. This ion implantation is performed, for example, boron ^{(11 B +)} of an acceleration energy of 120 KeV, dose of 2 × ¹⁰ of ^{13 / cm 2 ~3 × 10 13} / cm 2 conditions.
[0019]
Next, as shown in FIG. 4, using the photoresist layer 6 as a mask, ions are implanted into the P-type body layer 3 to form a P + -type buried region 7 deep from the surface of the P-type body layer 3. This ion implantation is performed, for example, boron ^{(11 B +)} acceleration energy 100KeV～150KeV, under the conditions of dose amount 1 × ¹⁰ 14 / cm ^2. This ion implantation can be used also as an ion implantation step for forming a channel stopper region below a field oxide film to be formed later.
[0020]
Next, as shown in FIG. 5, the field oxide films 8A and 8B are formed by using the LOCOS (Local Oxidation Of Silicon) method. The field oxide film is generally formed for element isolation. In this semiconductor device, the field oxide film is used to improve the breakdown voltage of the high breakdown voltage transistor. The thickness varies depending on the target breakdown voltage, but is about 300 nm to 1100 nm. In this step, the P + type buried region 7 is diffused to a wider region in the P type body layer 3.
[0021]
Next, as shown in FIG. 6, a predetermined region of field oxide film 8A is partially etched to expose the surface of P-type body layer 3, and is thermally oxidized to form gate oxide film 9. The thickness varies depending on the target breakdown voltage of the gate breakdown voltage of the transistor, but is about 15 nm to 250 nm. Field oxide films 8A and 8B have a considerably larger thickness than gate oxide film 9. Then, a gate electrode 10 is formed by depositing a polysilicon layer on the front surface by using the LPCVD method and selectively etching the polysilicon layer. One end of the gate electrode 10 is arranged near the end of the P + type buried region 7. The other end of the gate electrode 10 is formed to extend from above the gate oxide film 9 to a part of the field oxide film 8A.
[0022]
Next, as shown in FIG. 7, a photoresist layer 11 for masking a region where the N + type second drain layer is to be formed is formed, ion-implanted, and superposed on the surface of the P + type buried layer 7 to form P + The layer 12 is formed. The P + layer 12 serves to fix the potential of the P-type body layer 3 in cooperation with the P + -type buried layer 7 as described later.
[0023]
The ion implantation may be also used the ion implantation for source and drain formation of the P-channel transistor, for example, boron ^{(11 B +)} of an acceleration energy of 30 KeV, implanted at dose of 2 × ¹⁰ 15 / cm ² of about conditions.
[0024]
Next, as shown in FIG. 8, an N + type source layer 12 and an N + type second drain layer 14 are formed by ion implantation. The N + type source layer 12 is formed adjacent to the P + layer 12 while being aligned with one end of the gate electrode 10 using the photoresist layer 15 as a mask. Then, the P + type buried layer 7 is arranged in a region below the N + type source layer 12. The N + -type second drain layer 14 is formed on the surface of the N-type first drain layer between the field oxide films 8A and 8B.
[0025]
In this ion implantation, for example, phosphorus ( ³¹ P ⁺ ) is implanted under the conditions of a dose of 1 × 10 ¹⁴ / cm ² and an acceleration energy of 70 KeV, and arsenic ( ⁷⁵ As ⁺ ) is further implanted with a dose of 6 × 10 ¹⁵ / cm ^2. , At an acceleration energy of 80 KeV.
[0026]
Then, as shown in FIG. 9, a BPSG film 16 is deposited as an interlayer insulating film by a CVD method. Thereafter, a contact hole is formed on a boundary region between the P + layer 12 and the N + type source layer 13 and on the N + type second drain layer 14, and a source electrode 17 and a drain electrode 18 are formed.
[0027]
According to the semiconductor device completed in this manner, the region P + type buried layer 7 below the N + type source layer 13 is arranged. The P + type buried layer 7 lowers the resistance of the region below the N + type source layer 12. For this reason, the holes generated at the end of the N-type first drain layer 4 are removed from the P + -type layer formed on the surface of the body layer 3 adjacent to the P + -type buried layer 7 and the N + -type source layer. The light is quickly absorbed by the semiconductor substrate 12 and is emitted to the outside of the high breakdown voltage transistor through the source electrode 16. Then, an increase in the potential of the body layer 3 is suppressed, so that the parasitic NPN-type bipolar transistor is less likely to be turned on. Thereby, the operating withstand voltage of the high withstand voltage transistor is improved.
[0028]
FIG. 10 is a diagram showing the relationship between the operating breakdown voltage of the above-described high breakdown voltage transistor and the amount of boron dose of ion implantation for forming the P + type buried layer 7. As is apparent from this figure, the operating withstand voltage is improved as the boron dose amount is increased.
[0029]
In the above embodiment, an N-channel MOS transistor has been described. However, the present invention can be similarly applied to a P-channel MOS transistor.
[0030]
【The invention's effect】
According to the present invention, since the region P + type buried layer 7 below the N + type source layer 13 is arranged, the holes generated at the end of the N type first drain layer 4 will be It is absorbed by the buried layer 7 and emitted outside. As a result, it is possible to prevent the action of the parasitic bipolar transistor and improve the operating withstand voltage of the high withstand voltage transistor.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a semiconductor device and a method for fabricating the same according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating a semiconductor device and a method for fabricating the same according to an embodiment of the present invention.
FIG. 3 is a sectional view illustrating the semiconductor device and the method for fabricating the same according to the embodiment of the present invention.
FIG. 4 is a sectional view illustrating the semiconductor device and the method for fabricating the same according to the embodiment of the present invention.
FIG. 5 is a sectional view showing the semiconductor device and the method for manufacturing the same according to the embodiment of the present invention;
FIG. 6 is a sectional view showing the semiconductor device and the method for manufacturing the same according to the embodiment of the present invention;
FIG. 7 is a sectional view showing the semiconductor device and the method for manufacturing the same according to the embodiment of the present invention;
FIG. 8 is a sectional view illustrating the semiconductor device and the method for fabricating the semiconductor device according to the embodiment of the present invention.
FIG. 9 is a sectional view illustrating the semiconductor device and the method for fabricating the semiconductor device according to the embodiment of the present invention.
FIG. 10 is a diagram showing the relationship between the operating breakdown voltage of the high breakdown voltage transistor according to the embodiment of the present invention and the amount of ion implantation dose for forming the P + type buried layer 7;
FIG. 11 is a sectional view showing a semiconductor device according to a conventional example.

Claims (4)

A semiconductor substrate of the first conductivity type, a well region of the second conductivity type provided on the surface of the semiconductor substrate, a body layer of the first conductivity type provided on the surface of the well region of the second conductivity type; A gate insulating film disposed on the surface of the body layer; a gate electrode disposed on the gate insulating film; and a second conductive layer disposed on the surface of the body layer adjacent to one end of the gate electrode. Source layer, a buried layer of a first conductivity type having a higher concentration than the body layer disposed in a region below the source layer, and partially overlaps a surface region of the well region and a surface of the body layer. A first drain layer of a second conductivity type disposed in a region to be formed, and a second drain layer of a second conductivity type disposed on a surface of the first drain layer and separated from the other end of the gate electrode. A semiconductor device comprising: 2. The semiconductor device according to claim 1, wherein an insulating film thicker than the gate insulating film is disposed on a surface of the first drain layer, and the gate electrode extends over a part of the thick insulating film. Forming a body layer of the first conductivity type on a surface of the semiconductor substrate of the first conductivity type and a drain layer of the second conductivity type partially overlapping the body layer;
Forming a buried layer of a first conductivity type at a higher concentration than the body layer in the body layer by ion implantation;
Forming a gate insulating film on the surface of the body layer;
Forming a gate electrode on the gate insulating film;
Forming a first conductivity type body layer potential fixing layer by ion implantation on the surface of the body layer adjacent to one end of the gate electrode;
Forming a source electrode adjacent to the body layer potential fixing layer and forming a second conductivity type second drain layer on the surface of the semiconductor substrate apart from the gate electrode by ion implantation. A method for manufacturing a semiconductor device, comprising: Forming a body layer of the first conductivity type on a surface of the semiconductor substrate of the first conductivity type and a drain layer of the second conductivity type partially overlapping the body layer;
Forming a buried layer of a first conductivity type at a higher concentration than the body layer in the body layer by ion implantation;
Forming a field oxide film on the surface of the body layer;
Forming a gate insulating film in a region where the field oxide film is partially etched;
Forming a gate electrode extending over a portion of the gate insulating film and the field oxide film;
Forming a first conductivity type body layer potential fixing layer by ion implantation on the surface of the body layer adjacent to one end of the gate electrode;
Forming a source electrode adjacent to the body layer potential fixing layer and forming a second conductivity type second drain layer on the surface of the semiconductor substrate apart from the gate electrode by ion implantation. A method for manufacturing a semiconductor device, comprising:

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