JP2015149355A - Semiconductor element and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor element and a manufacturing method of the same, which can efficiently reduce on-resistance and reduce field concentration occurring at a corner part of an element isolation film.SOLUTION: A middle voltage semiconductor element HV1 (HV2) according to the present embodiment comprises: an Si substrate 1 including a drift layer 25 and a drift layer 7; a gate oxide film 33 formed on a channel region 5 sandwiched between the drift layer 25 and the drift layer 27; a gate electrode 35 formed on the gate oxide film 33; a source electrode 49 formed on the drift layer 25; a drain electrode 51 formed on the drift layer 27; and a LOCOS oxide film 23 which is formed on the drift layer 25 and the drift layer 27 and continues to the gate oxide film 33. In a depth direction of the Si substrate 1, a surface 33a of the gate oxide film 33 is provided at a position the same with a surface 23a of the LOCOS oxide film 23 or at a deep position farther from the gate electrode 35 than the surface 23a of the LOCOS oxide film 23.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  A conventional technique of a MOS (Metal-Oxide-Semiconductor) transistor in which a voltage of about tens to hundreds of tens of volts is applied to the gate electrode, that is, a so-called gate medium voltage MOS transistor (hereinafter also referred to as “medium voltage semiconductor element”). Is disclosed in Patent Document 1, for example. Hereinafter, a general structure of a medium voltage semiconductor device according to the prior art will be briefly described with reference to FIG.

  FIG. 15 is a cross-sectional view schematically showing the structure of a conventional medium voltage semiconductor device. As shown in FIG. 15, the medium withstand voltage semiconductor element HV3 according to the related art includes a silicon (Si) substrate 1, and a well layer 3 is formed on the Si substrate 1. In the well layer 3, a drift layer 25 and a drift layer 27 are formed separately from each other. The drift layers 25 and 27 are sometimes called a source region and a drain region, respectively. The drift layers 25 and 27 are configured to include high-concentration regions 37 and 39 each having a higher impurity ion concentration (concentration of impurity ions contributing to conductivity) than the surroundings. The high concentration regions 37 and 39 are formed in the surface layer portions (upper side in the drawing) of the drift layers 25 and 27. A source electrode 49 and a drain electrode 51 are connected to the high concentration regions 37 and 39 through tungsten (W) plugs 45 and 47, respectively, and a voltage is applied to the drift layers 25 and 27 through these electrodes, respectively. . The drift layers 25 and 27 often have different impurity ion concentrations in the depth direction of the Si substrate 1 (the vertical direction in the drawing).

  Between the drift layers 25 and 27, there is a region 5 (hereinafter also referred to as “channel region”) that becomes a channel. On the channel region 5, an intermediate breakdown voltage gate oxide film (hereinafter also simply referred to as “gate oxide film”) 33 is formed. An element isolation film 23 that is continuous with the gate oxide film 33 is formed between the gate oxide film 33 and the high concentration regions 37 and 39. Further, on the gate oxide film 33, an intermediate withstand voltage gate electrode (hereinafter also simply referred to as “gate electrode”) 35 is formed. A voltage is applied to the gate electrode 35 during the operation of the medium voltage semiconductor element HV3. Note that the arrow from the high concentration region 37 to the high concentration region 39 shown in FIG. 15 indicates the current path R2 during the operation of the medium withstand voltage semiconductor element HV3.

International Publication No. 2006/018974

  As shown in FIG. 15, the surface 33 a on the Si substrate 1 side of the gate oxide film 33 is provided closer to the gate electrode 35 (upper side in the drawing) than the surface 23 a on the Si substrate 1 side of the element isolation film 23. That is, in the depth direction of the Si substrate 1, the surface 33 a of the gate oxide film 33 and the surface 23 a of the element isolation film 23 are provided at positions separated from each other. Therefore, carriers (for example, electrons) pass through regions having different depths in the drift layers 25 and 27 during the operation of the medium withstand voltage semiconductor element HV3. That is, the current path R2 meanders in the thickness direction of the Si substrate 1 (up and down), and the impurity ion concentration in the current path R2 is nonuniform. If the impurity ion concentration is non-uniform in the current path R2, the amount of current is affected by a region having a high resistance, that is, a low impurity ion concentration. For this reason, the medium voltage semiconductor element HV3 has a problem that it is difficult to reduce so-called on-resistance.

  Further, as described above, since the surface 33a of the gate oxide film 33 and the surface 23a of the element isolation film 23 are provided in the depth direction of the Si substrate 1, the gate oxide film of the element isolation film 23 is provided. On the 33 side, a corner 23 b is easily formed due to a step between the surface 23 a of the element isolation film 23 and the surface 33 a of the gate oxide film 33. Therefore, when a voltage is applied to the gate electrode 35, there is a problem that electric field concentration tends to occur at the corner portion 23b. Note that when electric field concentration occurs in the corner 23b, the semiconductor element may be deteriorated or damaged.

  Accordingly, the present invention has been made in view of the above problems, and a semiconductor device capable of efficiently reducing on-resistance and reducing electric field concentration occurring at a corner of the device isolation film, and a method for manufacturing the same. The purpose is to provide.

  In order to solve the above problems, one embodiment of the present invention includes a semiconductor substrate including a drain region and a source region, and gate oxidation formed over a channel region sandwiched between the drain region and the source region. A gate electrode formed on the gate oxide film; a drain electrode formed on a part of the drain region; a source electrode formed on a part of the source region; An element isolation film that is formed so as to cover an end portion on the channel region side and an end portion on the channel region side of the source region, and is continuous with the gate oxide film, and includes the gate oxide film and the element In the depth direction from the main surface of the semiconductor substrate, which is the formation surface of the isolation film, to the back surface of the semiconductor substrate, the surface of the gate oxide film on the semiconductor substrate side is the semiconductor of the element isolation film. The same position as the substrate-side surface, or a semiconductor element provided at a deep position apart from the gate electrode from the semiconductor substrate side surface of the isolation layer.

In the above semiconductor element, the element isolation film may be a LOCOS oxide film.
In the semiconductor device, the gate oxide film may be a thermal oxide film.
Further, in the semiconductor element, in the depth direction, the surface of the gate oxide film on the semiconductor substrate side is provided at a position farther from the gate electrode than the surface of the element isolation film on the semiconductor substrate side. It may be.

Further, in the semiconductor element, in the depth direction, the surface of the gate oxide film on the semiconductor substrate side is included in the drain region and the source region, respectively, and has a concentration peak of impurity ions contributing to conductivity. It may be provided at the same position as the position.
According to another aspect of the present invention, a step of forming a first drain region and a first source region in a first element formation region included in a semiconductor substrate, the first drain region and the first source region A first channel region sandwiched between the first channel region, an end of the first drain region on the first channel region side, and an end of the first source region on the first channel region side integrally covering the first channel region. Forming a single element isolation film; removing the first element isolation film formed on the first channel region to expose the first channel region; and exposing the first channel region. A step of forming a first gate oxide film continuous with the first element isolation film; a step of forming a first gate electrode on the first gate oxide film; and after forming the first gate electrode, A first drain current is formed on the first drain region. Forming a a method for manufacturing a semiconductor device having a step of forming a first source electrode, the said first source region.

  According to another aspect of the present invention, a second conductivity type impurity is implanted into a first element formation region included in a first conductivity type semiconductor substrate, and a first well layer is formed in the first element formation region. A step of forming a first element isolation film on a part of the first well layer, and an impurity of the first conductivity type in a part of the first well layer via the first element isolation film. Implanting and forming a body layer including a first channel region in the first well layer; removing the first element isolation film formed on the first channel region; and Exposing the first channel region, forming a first gate oxide film continuous with the first element isolation film on the exposed first channel region, and forming a first gate electrode on the first gate oxide film And forming the first gate electrode after forming the first gate electrode. That is, a step of forming a first drain electrode on a first drain region that is one region facing each other across the first channel region and forming a first source electrode on a first source region that is the other region. And a method for manufacturing a semiconductor device.

In the method for manufacturing a semiconductor element, in the step of exposing the first channel region, the first element isolation film may be removed only on the first channel region.
In the method of manufacturing a semiconductor device, in the step of forming the first gate oxide film, the semiconductor is formed from a main surface of the semiconductor substrate which is a formation surface of the first gate oxide film and the first element isolation film. In the depth direction toward the back surface of the substrate, the surface of the first gate oxide film on the semiconductor substrate side is at the same position as the surface of the first element isolation film on the semiconductor substrate side, or on the first element isolation film. The formation of the first gate oxide film may be continued until reaching a deep position away from the first gate electrode from the surface on the semiconductor substrate side.

  In the method of manufacturing a semiconductor device, in the step of forming the first gate oxide film, a surface of the first gate oxide film on the semiconductor substrate side in the depth direction is the first drain region and The formation of the first gate oxide film may be continued until reaching the same position as the concentration peak of impurity ions that are included in the first source region and contribute to conductivity.

  In the method of manufacturing a semiconductor element, the first element isolation film may be formed in a part of a second element formation region that is included in the semiconductor substrate and is different from the first element formation region simultaneously with the step of forming the first element isolation film. After the step of forming a two-element isolation film and the step of forming the first gate oxide film, an impurity of the first conductivity type or the second conductivity type is introduced into the second element formation region, and a second well layer is formed. Forming a second gate insulating film in the second element formation region after the step of forming the second well layer and before the step of forming the first gate electrode, Simultaneously with the step of forming the first gate electrode, after the step of forming the second gate electrode on the second gate insulating film and the step of forming the second gate electrode, the first drain electrode and the first gate electrode are formed. Step of forming one source electrode And simultaneously forming the second drain region and the second source region in the second element formation region exposed from under the second gate electrode, and forming the first drain electrode and the first source electrode. And a step of forming a second drain electrode on the second drain region and forming a second source electrode on the second source region.

In the method of manufacturing a semiconductor element, in the step of forming the first element isolation film, a LOCOS is formed after forming a SiN film on a region where the first source electrode and the first drain electrode are formed. The first element isolation film may be formed by oxidation.
In the method of manufacturing a semiconductor device, in the step of forming the first element isolation film, the region on which the first source electrode and the first drain electrode are formed, and the second gate insulating film The first element isolation film and the second element isolation film may be formed by forming a SiN film on the second drain region and the second source region and then performing LOCOS oxidation.

  According to one embodiment of the present invention, on-resistance can be efficiently reduced, and electric field concentration occurring in a corner portion of an element isolation film can be reduced.

It is sectional drawing which shows the structure of the semiconductor device which concerns on 1st Embodiment. FIG. 6 is a manufacturing process cross-sectional view illustrating the manufacturing method of the semiconductor device according to the first embodiment in the order of processes. FIG. 6 is a manufacturing process cross-sectional view illustrating the manufacturing method of the semiconductor device according to the first embodiment in the order of processes. It is sectional drawing which shows the structure of the semiconductor device which concerns on 2nd Embodiment. It is manufacturing process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment in process order. It is manufacturing process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment in process order. It is sectional drawing which shows the structure of the semiconductor device which concerns on 3rd Embodiment. It is manufacturing process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment in process order. It is manufacturing process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment in process order. It is manufacturing process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment in process order. It is sectional drawing which shows the structure of the semiconductor device which concerns on 4th Embodiment. It is manufacturing process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 4th Embodiment in order of a process. It is manufacturing process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 4th Embodiment in order of a process. It is manufacturing process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 4th Embodiment in order of a process. It is sectional drawing for demonstrating a subject.

Embodiments of the present invention will be described below with reference to the drawings. Note that, in each drawing, the same reference numerals are given to portions having the same configuration and the same function, and repeated description thereof is omitted.
<First Embodiment>
(Constitution)
FIG. 1 is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1, the semiconductor device 100 according to the present embodiment is a semiconductor device including a medium withstand voltage semiconductor element HV1. The medium withstand voltage semiconductor element HV1 includes a P-type Si substrate 1, and a P-type well layer 3 is formed on the Si substrate 1. In the well layer 3, an N-type source-side drift layer (hereinafter simply referred to as “drift layer”) 25 and an N-type drain-side drift layer (hereinafter also simply referred to as “drift layer”). 27 are separated from each other. Further, the well layers 3 are respectively located immediately below the drift layers 25 and 27. Hereinafter, for convenience, the interface between the drift layer 25 and the well layer 3 is referred to as “interface 25a”, and the interface between the drift layer 27 and the well layer 3 is referred to as “interface 27a”.

  The drift layers 25 and 27 are configured to include high concentration regions 37 and 39 having a higher impurity ion concentration than the surroundings. The high concentration regions 37 and 39 are formed in the surface layer portion of the drift layers 25 and 27. Has been. The broken lines shown in the drift layers 25 and 27 indicate the highest impurity ion concentration region (that is, the peak position of the impurity ion concentration) in the drift layers 25 and 27.

  Between the drift layers 25 and 27, a region 5 (hereinafter also referred to as “channel region”) 5 that becomes a channel when the medium withstand voltage semiconductor element HV1 operates is formed. A gate oxide film 33 having a thickness of about 1500 mm is formed immediately above the channel region 5. More specifically, the gate oxide film 33 covers the channel region 5, and both end portions of the gate oxide film 33 cover the end portions of the drift layers 25 and 27 on the channel region 5 side, respectively. The gate oxide film 33 is preferably a thermal oxide film.

  On the drift layers 25 and 27, LOCOS oxide films 21 and 23 having a thickness of about 4000 mm are formed as element isolation films. In addition, contact holes 44 and 46 for joining the source electrode 49 and the drain electrode 51 to the drift layers 25 and 27, respectively, are formed between the LOCOS oxide films 21 and 23. The end of the LOCOS oxide film 23 on the gate oxide film 33 side is integrated with the gate oxide film 33, respectively.

  Here, the Si substrate 1 on which the gate oxide film 33 and the LOCOS oxide films 21 and 23 are formed (the surface of the Si substrate 1 located on the upper side of the drawing) to the back surface of the Si substrate 1 (the Si located on the lower side of the drawing). A direction toward the surface of the substrate 1 is defined as a “depth direction”. In this depth direction, the surface 33a of the gate oxide film 33 on the Si substrate 1 side is provided at a position deeper than the surface 23a of the LOCOS oxide film 23 on the Si substrate 1 side. In other words, in the depth direction, the surface 33 a of the gate oxide film 33 is provided closer to the interfaces 25 a and 27 a than the surface 23 a of the LOCOS oxide film 23. In other words, in the depth direction, the surface 23 a of the LOCOS oxide film 23 is provided closer to the gate electrode 35 than the surface 33 a of the gate oxide film 33.

  The surface 33a of the gate oxide film 33 is preferably provided at the same depth as the impurity ion concentration peak positions (positions indicated by broken lines) in the drift layers 25 and 27, but up to the same depth as the interfaces 25a and 27a. If there is, it can be provided. Further, the surface 33 a of the gate oxide film 33 may be provided at the same depth as the surface 23 a of the LOCOS oxide film 23. That is, it is most preferable to provide both the surface 33a of the gate oxide film 33 and the surface 23a of the LOCOS oxide film 23 at the peak position of the impurity ion concentration.

  On part of the gate oxide film 33 and the LOCOS oxide film 23, a gate electrode 35 made of polysilicon is formed. More specifically, the gate electrode 35 covers the gate oxide film 33, and each of the end portions (end portions located in the left-right direction in the drawing) of the gate electrode 35 is on the end portion of the LOCOS oxide film 23 on the gate oxide film 33 side. Covering. Thus, by providing the end portions of the gate electrode 35 on the LOCOS oxide film 23 having a thickness larger than that of the gate oxide film 33, it is possible to prevent the electric field from concentrating on the gate oxide film 33, and thus the semiconductor element. It is possible to improve the pressure resistance. On the LOCOS oxide film 23, a sidewall 41 in contact with the side surface of the gate electrode 35 is formed. A voltage is applied to the gate electrode 35 during the operation of the medium withstand voltage semiconductor element HV1.

  The interlayer insulating film 43 is formed so as to cover the gate electrode 35, the sidewall 41, and the LOCOS oxide films 21 and 23. In the interlayer insulating film 43, W plugs 45 and 47 that penetrate the interlayer insulating film 43 and are electrically connected to the high concentration regions 37 and 39 are formed, respectively. A source electrode 49 and a drain electrode 51 that are electrically connected to the W plugs 45 and 47 are formed on the interlayer insulating film 43, respectively. Note that the source electrode 49 and the drain electrode 51 are formed of an aluminum (Al) alloy.

  During operation of the medium withstand voltage semiconductor element HV1, a current flows along the current path R1. This current path R1 has a smaller amount of change in the substrate depth direction (the vertical direction in the drawing) than the current path R2 of the medium voltage semiconductor device HV3 according to the prior art shown in FIG. That is, in the current path R1, the meandering of the path is reduced compared to the current path R2. Further, the medium withstand voltage semiconductor device HV1 has less step between the surface 23a of the element isolation film 23 and the surface 33a of the gate oxide film 33 than the medium withstand voltage semiconductor device HV3. Therefore, it is difficult to form corners on the surface 23 a of the element isolation film 23 and the surface 33 a of the gate oxide film 33 to the extent that an electric field concentrates when a voltage is applied to the gate electrode 35.

(Modification)
In the present embodiment, the NMOS transistor (that is, the transistor in which the N type drift layers 25 and 27 are formed in the P type well layer 3) has been described, but the present invention is not limited to this. For example, it may be a PMOS transistor (that is, a transistor in which a P-type drift layer is formed in an N-type well layer).

(Production method)
Next, a method for manufacturing the semiconductor device 100 according to the first embodiment will be described with reference to FIGS.
2 and 3 are cross-sectional views of manufacturing steps showing the order of steps of the method of manufacturing a semiconductor device according to the first embodiment of the present invention. In the method for manufacturing the semiconductor device 100 according to the present embodiment, first, a P-type Si substrate 1 is prepared. Next, a P-type impurity is ion-implanted into the Si substrate 1. In this ion implantation process, for example, boron is used as a P-type impurity. The dose amount for ion implantation is 1E + 12 to 5E + 12 cm ⁻² . Thereafter, heat is applied to the Si substrate 1, and the impurity ions implanted into the Si substrate 1 are thermally diffused. In this way, as shown in FIG. 2A, the P-type well layer 3 is formed in the surface layer portion of the Si substrate 1.

Next, as shown in FIG. 2B, the channel region 5 included in the well layer 3 is covered with a photoresist 7. For example, the photoresist 7 is formed by patterning a photoresist film (not shown) formed so as to cover the well layer 3 by a photolithography method. Subsequently, N-type impurities are ion-implanted into the surface layer portion of the well layer 3 using the photoresist 7 as a mask. Thus, impurity ion implanted layers 9 and 11 are formed. In this ion implantation process, arsenic or phosphorus is used as an N-type impurity. The dose amount for ion implantation is 1E + 12 to 5E + 12 cm ⁻² . In the above-described ion implantation, the channel region 5 is covered with the photoresist 7, so that no N-type impurity is implanted into the channel region 5.

Next, as shown in FIG. 2C, the photoresist 7 is removed, and an oxide film 13 covering the entire surface of the impurity ion implanted layers 9 and 11 and the channel region 5 is formed. The oxide film 13 is a film made of, for example, SiO ₂ . Subsequently, a silicon nitride (SiN) film (not shown) that covers the entire surface of the oxide film 13 is formed by a CVD (Chemical Vapor Deposition) method. The formed SiN film has a thickness of about 1200 mm. Thereafter, the above-described SiN film is patterned so as to cover regions (hereinafter also referred to as “contact hole forming regions”) 44a and 46a in which contact holes 44 and 46 are formed as shown in FIG. Thus, the SiN film 15 is formed. As a method for patterning the SiN film, for example, reactive ion etching (RIE), which is dry etching, can be given.

  Next, a thermal oxidation process using the SiN film 15 as a mask is performed. By this thermal oxidation treatment, an element isolation film (thermal oxide film) is formed in a region not covered with the SiN film 15. Examples of the thermal oxidation method include a LOCOS (Local Oxidation of Silicon) method. FIG. 2D shows element isolation films (hereinafter also referred to as “LOCOS oxide films”) 21 and 23 formed by the LOCOS method. The LOCOS oxide films 21 and 23 have a thickness of about 4000 mm. In addition, LOCOS oxide films 21 and 23 are formed by the thermal oxidation, and N-type impurities existing in the impurity ion implantation layers 9 and 11 are thermally diffused, and drift layers 25 and 27 are formed in the well layer 3 respectively. It is formed. Note that both end portions of the SiN film 15 protrude from the substrate back side (lower side in the drawing) toward the substrate main surface side (upper side in the drawing). This is because, when the LOCOS oxide films 21 and 23 are formed, the end portions of the SiN film 15 are pushed up from the substrate back side toward the substrate main surface side by the end portions of the LOCOS oxide films 21 and 23 (so-called bird's beaks). is there. Note that a portion of the oxide film 13 remains immediately below the SiN film 15.

  Next, the LOCOS oxide films 21 and 23 and the SiN film 15 are covered with a photoresist 29. Subsequently, as shown in FIG. 2E, an opening 31 is formed in the photoresist 29 so as to expose the surface of the LOCOS oxide film 23 located above the channel region 5. For example, a lithography method can be used to form the opening 31. Thereafter, the LOCOS oxide film 23 is etched using the photoresist 29 as a mask so that the channel region 5 is exposed. At this time, the LOCOS oxide film 23 is etched in the substrate depth direction while being side-etched. When the channel region 5 is exposed, it is preferable to remove the LOCOS oxide film 23 only on the channel region 5 using a technique such as anisotropic etching. The LOCOS oxide film 23 is etched using, for example, buffered hydrofluoric acid.

Next, the photoresist 29 is removed. Subsequently, as shown in FIG. 3A, a gate oxide film 33 is formed on the channel region 5 by performing thermal oxidation treatment on the exposed surface of the channel region 5.
When the gate oxide film 33 is formed, the surface 33a of the oxide film 33 is located at the same position as the surface 23a of the LOCOS oxide film 23 or in the depth direction from the main surface of the Si substrate 1 to the back surface of the Si substrate. The formation of the gate oxide film 33 is continued until reaching a deeper position away from the gate electrode 33 than the surface 23a of the oxide film 23. More preferably, formation of the gate oxide film 33 is continued until the surface 33a of the gate oxide film 33 reaches the same position as the concentration peak of impurity ions contained in the drift layers 25 and 27 in the substrate depth direction. To do.

  The gate oxide film 33 thus formed is integrated with the end portion of the LOCOS oxide film 23 on the gate oxide film 33 side. The gate oxide film 33 has a thickness of about 1500 mm. Thereafter, the SiN film 15 and the oxide film 13 are sequentially removed. For example, the SiN film 15 is removed by immersing the substrate in a hot phosphoric acid solution. The oxide film 13 is removed by immersing the substrate in hydrofluoric acid. FIG. 3B shows a state in which the SiN film 15 and the oxide film 13 are sequentially removed.

Next, as shown in FIG. 3C, a gate electrode 35 made of polysilicon is formed. The gate electrode 35 can be formed, for example, by forming a polysilicon film (not shown) so as to cover the entire surface of the Si substrate 1 and then etching the polysilicon film.
Next, sidewalls 41 are formed on the side surfaces of the gate electrode 35 (side surfaces located in the horizontal direction of the drawing). Thereafter, N-type impurities are ion-implanted into the drift layers 25 and 27 using the LOCOS oxide films 21 and 23 as a mask. In this ion implantation process, arsenic or phosphorus is used as an N-type impurity. The dose amount for ion implantation is 1E + 15 to 1E + 16 cm ⁻² . Thus, the high concentration regions 37 and 39 are formed in the drift layers 25 and 27.

In the subsequent steps, electrical connection is performed using a standard multilayer wiring process. That is, as shown in FIG. 3D, an interlayer insulating film 43 is formed, holes are formed through the interlayer insulating film 43 with the high-concentration regions 37 and 39 as bottom surfaces, and an electrode material ( For example, W) is embedded. In this way, W plugs 45 and 47 electrically connected to the drift layers 25 and 27 are formed.
Finally, a metal wiring film (not shown) is formed on the interlayer insulating film 43 on which the W plugs 45 and 47 are formed, and the metal wiring film is patterned. Thus, the source electrode 49 and the drain electrode 51 electrically connected to the W plugs 45 and 47 are formed.

Through the above steps, the semiconductor device 100 including the semiconductor element HV1 shown in FIG. 1 is completed.
In this embodiment, the drift layers 25 and 27 correspond to the (first) source region and the (first) drain region of the present invention. The LOCOS oxide film 23 corresponds to the (first) element isolation film of the present invention. Further, the region shown in the drawing (that is, the formation region of the semiconductor element HV1) corresponds to the first element formation region of the present invention.
(Modification)
In the present embodiment, the manufacturing method of the NMOS transistor has been described, but the present invention is not limited to this. Using the manufacturing method according to this embodiment, for example, a PMOS transistor can be manufactured by changing the polarity of the impurity to be implanted.

Second Embodiment
(Constitution)
FIG. 4 is a cross-sectional view showing a configuration example of a semiconductor device according to the second embodiment of the present invention. As shown in FIG. 4, the semiconductor device 101 according to the present embodiment is a semiconductor device including a medium withstand voltage semiconductor element HV2. The structure of the medium voltage semiconductor element HV2 is different from the structure of the medium voltage semiconductor element HV1 described above in that it includes the drift layers 59 and 61 and the body layer 54, but the other structures are substantially the same. Accordingly, the drift layers 59 and 61 and the body layer 54 which are different from the medium withstand voltage semiconductor element HV1 will be described, and the description of the rest will be omitted. The body layer 54 includes a (first) channel region on the gate oxide film 33 side.

  The medium breakdown voltage semiconductor element HV2 includes a P-type Si substrate 1, and N-type drift layers 59 and 61 are formed on the Si substrate 1 so as to be separated from each other. The drift layers 59 and 61 are configured to include high-concentration regions 37 and 39, respectively, and the high-concentration regions 37 and 39 are formed in the surface layer portion of the drift layers 59 and 61. Here, the well layer 3 described in the first embodiment does not exist immediately below the drift layers 59 and 61.

  A P-type body layer 54 is formed between the drift layers 59 and 61. A gate oxide film 33 having a thickness of about 1500 mm is formed immediately above the body layer 54. In the substrate depth direction, the surface 33 a of the gate oxide film 33 is provided at a position deeper than the surface 23 a of the LOCOS oxide film 23. In other words, in the depth direction, the surface 33 a of the gate oxide film 33 is provided closer to the Si substrate 1 than the surface 23 a of the LOCOS oxide film 23. In other words, in the depth direction, the surface 23 a of the LOCOS oxide film 23 is provided closer to the gate electrode 35 than the surface 33 a of the gate oxide film 33.

  During the operation of the medium withstand voltage semiconductor element HV2, a current flows along the current path R1. This current path R1 has a smaller amount of change in the substrate depth direction (the vertical direction in the drawing) than the current path R2 of the medium voltage semiconductor device HV3 according to the prior art shown in FIG. That is, in the current path R1, the meandering of the path is reduced compared to the current path R2. Further, in the medium withstand voltage semiconductor device HV2, the level difference between the surface 23a of the element isolation film 23 and the surface 33a of the gate oxide film 33 is reduced as compared with the medium withstand voltage semiconductor device HV3. Therefore, it is difficult to form corners on the surface 23 a of the element isolation film 23 and the surface 33 a of the gate oxide film 33 to the extent that an electric field concentrates when a voltage is applied to the gate electrode 35.

(Production method)
Next, a method for manufacturing the semiconductor device 101 according to the second embodiment will be described with reference to FIGS.
5 and 6 are cross-sectional views of manufacturing steps showing the order of steps of the method of manufacturing the semiconductor device 101 according to the second embodiment of the present invention. In the method for manufacturing the semiconductor device 101 according to this embodiment, first, a P-type Si substrate 1 is prepared. Next, N-type impurities are ion-implanted into the surface layer portion of the Si substrate 1. In this ion implantation process, arsenic or phosphorus is used as an N-type impurity. The dose amount for ion implantation is 1E + 12 to 5E + 12 cm ⁻² . Thereafter, heat is applied to the Si substrate 1 to thermally diffuse the N-type impurity ions implanted into the Si substrate 1. Thus, as shown in FIG. 5A, an N-type drift layer 53 is formed on the Si substrate 1.

Next, as shown in FIG. 5B, the oxide film 13 is formed so as to cover the entire surface of the drift layer 53. The oxide film 13 is a film made of, for example, SiO ₂ . Subsequently, an SiN film (not shown) that covers the entire surface of the drift layer 53 is formed by a CVD method. The formed SiN film has a thickness of about 1200 mm. Thereafter, the SiN film is patterned so as to cover the contact hole formation regions 44a and 46a, respectively. Thus, the SiN film 15 is formed. An example of the SiN film patterning method is RIE.

  Next, a thermal oxidation process using the SiN film 15 as a mask is performed. By this thermal oxidation treatment, an element isolation film (thermal oxide film) is formed in a region not covered with the SiN film 15. Examples of the thermal oxidation method include a LOCOS method. FIG. 5C shows the LOCOS oxide films 21 and 23 formed as the element isolation films. The formed LOCOS oxide films 21 and 23 have a thickness of about 4000 mm. Note that both end portions of the SiN film 15 protrude from the substrate back side (lower side in the drawing) toward the substrate main surface side (upper side in the drawing). This is because, when the LOCOS oxide films 21 and 23 are formed, the end portions of the SiN film 15 are pushed up from the substrate rear surface side to the substrate main surface side by the end portions of the LOCOS oxide films 21 and 23. Note that a portion of the oxide film 13 remains immediately below the SiN film 15.

Next, the LOCOS oxide films 21 and 23 and the SiN film 15 are covered with a photoresist 29. Subsequently, an opening 31 is formed in the photoresist 29 so as to expose the surface of the LOCOS oxide film 23 located above the region (hereinafter also referred to as “body region”) 57 to be the body layer 54. For example, a lithography method can be used to form the opening 31. Thereafter, P-type impurities are ion-implanted into the body region 57 through the LOCOS oxide film 23. In this ion implantation process, for example, boron is used as a P-type impurity. The dose amount for ion implantation is 1E + 12 to 1E + 13 cm ⁻² . In the above ion implantation, the P-type impurity is not implanted into the region covered with the photoresist 29. Thus, the body layer 54 is formed as shown in FIG. In addition, by forming the body layer 54, drift layers 59 and 61 that face each other with the body layer 54 interposed therebetween are formed.

  Next, as shown in FIG. 5E, the LOCOS oxide film 23 is etched using the photoresist 29 as a mask so that the body layer 54 is exposed. At this time, the LOCOS oxide film 23 is etched in the substrate depth direction while being side-etched. The LOCOS oxide film 23 is etched using, for example, buffered hydrofluoric acid. Further, when exposing the body layer 54, it is preferable to remove the LOCOS oxide film 23 only on the body layer 54 using a technique such as anisotropic etching.

Next, the photoresist 29 is removed. Subsequently, as shown in FIG. 6A, a gate oxide film 33 is formed on the body layer 54 by performing a thermal oxidation process on the exposed surface of the body layer 54. The gate oxide film 33 thus formed is integrated with the end portion of the LOCOS oxide film 23 on the gate oxide film 33 side.
When the gate oxide film 33 is formed, the surface 33a of the oxide film 33 is located at the same position as the surface 23a of the LOCOS oxide film 23 or in the depth direction from the main surface of the Si substrate 1 to the back surface of the Si substrate. The formation of the gate oxide film 33 is continued until reaching a deeper position away from the gate electrode 33 than the surface 23a of the oxide film 23. More preferably, the formation of the gate oxide film 33 is continued until the surface 33a of the gate oxide film 33 reaches the same position as the concentration peak of impurity ions contained in the drift layers 59 and 61 in the substrate depth direction. To do.

The gate oxide film 33 thus formed is integrated with the end portion of the LOCOS oxide film 23 on the gate oxide film 33 side. The gate oxide film 33 has a thickness of about 1500 mm.
The steps after the formation of the gate oxide film 33 are the same as those described in the first embodiment, and the steps shown in FIGS. 6B to 6D are the same as those shown in FIGS. These correspond to the steps shown in d). That is, as shown in FIG. 6B, the SiN film 15 and the oxide film 13 are sequentially removed. Next, as shown in FIG. 6C, the gate electrode 35 is formed on the LOCOS oxide film 23 and the gate oxide film 33. Next, as shown in FIG. 6D, sidewalls 41, high-concentration regions 37 and 39, an interlayer insulating film 43, W plugs 45 and 47, a source electrode 49, and a drain electrode 51 are sequentially formed.

Through the above steps, the semiconductor device 101 including the semiconductor element HV2 shown in FIG. 4 is completed.
In this embodiment, the drift layers 59 and 61 correspond to the (first) source region and the (first) drain region of the present invention. The LOCOS oxide film 23 corresponds to the (first) element isolation film of the present invention. Further, the region shown in the drawing (that is, the formation region of the semiconductor element HV2) corresponds to the first element formation region of the present invention.

<Third Embodiment>
(Constitution)
FIG. 7 is a cross-sectional view showing a configuration example of a semiconductor device according to the third embodiment of the present invention. As shown in FIG. 7, the semiconductor device 102 according to the present embodiment is a semiconductor device provided with a medium breakdown voltage semiconductor element HV1 and a low breakdown voltage semiconductor element LV on the same substrate. Here, the structure of the medium voltage semiconductor element HV1 according to the present embodiment is the same as the structure of the medium voltage semiconductor element HV1 described in the first embodiment. Therefore, in the present embodiment, only the structure of the low breakdown voltage semiconductor element LV will be described, and the description of the structure of the medium breakdown voltage semiconductor element HV1 will be omitted. Hereinafter, for convenience, the formation region of the medium breakdown voltage semiconductor element HV1 included in the Si substrate 1 is referred to as “region RH”, and the formation region of the low breakdown voltage semiconductor element LV is referred to as “region RL”.

[Low voltage semiconductor device LV]
The region RL is element-isolated by a LOCOS oxide film 65 on which a P-type Si substrate 1 is formed. A low breakdown voltage semiconductor element LV is formed in this region RL. A P-type well layer 67 is formed on the Si substrate 1 in the region RL. In the well layer 67, a source region 81 and a drain region 83 are arranged to face each other with a channel region 69 therebetween (hereinafter, both regions are also referred to as “source / drain regions 81, 83”). ). Low concentration regions 77 and 79 having a lower impurity ion concentration than the source / drain regions 81 and 83 are formed on the channel region 69 side of the source / drain regions 81 and 83. The low concentration regions 77 and 79 are formed in the surface layer portion of the well layer 67. The source / drain regions 81 and 83 and the low concentration regions 77 and 79 are regions having N-type conductivity. That is, the low breakdown voltage semiconductor element LV is a semiconductor element having a so-called LDD (Lightly Doped Drain) structure.

  A low breakdown voltage gate oxide film (hereinafter also simply referred to as “gate oxide film”) 71 having a film thickness of, for example, about 130 mm is formed immediately above the channel region 69. A low breakdown voltage gate electrode (hereinafter also simply referred to as “gate electrode”) 73 made of polysilicon is formed immediately above the gate oxide film 71. A voltage is applied to the gate electrode 73 during the operation of the low breakdown voltage semiconductor element LV.

Side walls 75 are formed on the side surfaces (side surfaces located in the horizontal direction of the drawing) of the gate oxide film 71 and the gate electrode 73, respectively. Immediately below the sidewall 75, low concentration regions 77 and 79 are located.
The interlayer insulating film 43 is formed so as to cover the gate electrode 73 and the sidewall 75. In the interlayer insulating film 43, W plugs 85 and 87 that penetrate the interlayer insulating film 43 and are electrically connected to the source / drain regions 81 and 83 are formed, respectively. A source electrode 89 and a drain electrode 91 electrically connected to the W plugs 85 and 87 are formed on the interlayer insulating film 43, respectively. During operation of the low breakdown voltage semiconductor element LV, voltages are applied to the source / drain regions 81 and 83 via the source electrode 89 and the drain electrode 91, respectively. Note that the source electrode 89 and the drain electrode 91 are made of an Al alloy.

(Production method)
Next, a method for manufacturing the semiconductor device 102 according to the third embodiment will be described with reference to FIGS.
8 to 10 are manufacturing process cross-sectional views illustrating the order of processes in the method of manufacturing a semiconductor device according to the third embodiment of the present invention. In each drawing, the left side shows a region RH, and the right side shows a region RL. That is, the medium withstand voltage semiconductor element HV1 is formed on the left side of the drawing, and the low withstand voltage semiconductor element LV is formed on the right side of the drawing. Note that the method of manufacturing the medium voltage semiconductor element HV1 according to the present embodiment is the same as the method of manufacturing the medium voltage semiconductor element HV1 described in the first embodiment. Therefore, the method of manufacturing the medium withstand voltage semiconductor element HV1 will be described by omitting as appropriate.

  In the method for manufacturing the semiconductor device 102 according to the present embodiment, first, a P-type Si substrate 1 is prepared. Next, a P-type impurity is ion-implanted into the Si substrate 1 in the region RH. At this time, P-type impurities are not ion-implanted into the Si substrate 1 in the region RL. Thereafter, heat is applied to the Si substrate 1 to thermally diffuse the P-type impurity ions implanted into the Si substrate 1. Thus, as shown in FIG. 8A, the well layer 3 is formed on the Si substrate 1 in the region RH.

Next, as shown in FIG. 8B, N-type impurities are ion-implanted into the surface layer portion of the well layer 3 using the photoresist 7 as a mask. Thus, impurity ion implantation regions 9 and 11 are formed. At this time, N-type impurities are not ion-implanted into the Si substrate 1 in the region RL.
Next, as shown in FIG. 8C, the photoresist 7 is removed, and an oxide film 13 is formed so as to cover the entire surface of the Si substrate 1. That is, the oxide films 13 are formed on the surfaces of the impurity ion implantation regions 9 and 11 and the channel region 5 in the region RH and the surface of the Si substrate 1 in the region RL, respectively. The oxide film 13 is a film made of, for example, SiO ₂ . Subsequently, the SiN films 15 and 63 are formed so as to cover the contact hole forming regions 44a and 46a in the region RH and a part of the region RL (second gate insulating film, second drain region, and second source region). Form.

  Next, a thermal oxidation process using the SiN films 15 and 63 as a mask is performed. By this thermal oxidation treatment, LOCOS oxide films 21, 23, and 65 are formed in regions not covered with the SiN films 15 and 63. FIG. 9A shows the LOCOS oxide films 21, 23, and 65 formed by the thermal oxidation process. Note that a part of the oxide film 13 remains immediately below the SiN films 15 and 63.

  Next, a photoresist 29 is formed so as to cover the LOCOS oxide films 21, 23 and 65 and the SiN films 15 and 63. Subsequently, as shown in FIG. 9B, an opening 31 is formed in the photoresist 29 so as to expose the surface of the LOCOS oxide film 23 located above the channel region 5 in the region RH. Thereafter, the LOCOS oxide film 23 is etched using the photoresist 29 as a mask so that the channel region 5 in the region RH is exposed. Note that the LOCOS oxide film 65 in the region RL is not etched because it is covered with the photoresist 29.

  Next, the photoresist 29 is removed. Subsequently, as shown in FIG. 9C, a medium oxidation gate oxide film 33 is formed on the channel region 5 in the region RH by performing a thermal oxidation process on the surface of the channel region 5 in the region RH. Thereafter, the SiN films 15 and 63 and the oxide film 13 are sequentially removed. FIG. 10A shows a state where the SiN films 15 and 63 and the oxide film 13 are sequentially removed.

Next, P-type impurities are ion-implanted into the surface layer portion of the Si substrate 1 in the region RL. In this ion implantation process, for example, boron is used as a P-type impurity. The dose amount for ion implantation is 1E + 12 to 1E + 13 cm ⁻² . Thereafter, heat is applied to the Si substrate 1 to thermally diffuse the P-type impurity ions implanted into the region RL. In this ion implantation step, P-type impurities are not ion-implanted into the Si substrate 1 in the region RH. Thus, the well layer 67 is formed in the region RL as shown in FIG.

  Next, a gate oxide film 71 is formed on the channel region 69 in the region RL. Subsequently, as shown in FIG. 10B, the gate electrode 35 is formed on the gate oxide film 33 and the LOCOS oxide film 23 in the region RH, and at the same time, the gate electrode 73 is formed on the gate oxide film 71 in the region RL. Form. More specifically, first, a thermal oxide film (not shown) is formed so as to cover the region RL. Subsequently, a polysilicon film (not shown) is formed so as to cover the region RH and the region RL. Thereafter, the polysilicon film is patterned to form gate electrodes 35 and 73 in the region RH and the region RL. Then, the gate oxide film 71 is formed by patterning the thermal oxide film in the region RL using the gate electrode 73 formed in the region RL as a mask.

Next, using the gate electrode 73 and the gate oxide film 71 as a mask, N-type impurities are ion-implanted into the surface layer portion of the well layer 67 in the region RL. In this ion implantation process, arsenic or phosphorus is used as an N-type impurity. The dose amount for ion implantation is 1E + 13 to 1E + 14 cm ⁻² . Thus, the low concentration regions 77 and 79 are formed in the well layer 67. Note that, in the above-described ion implantation, an N-type impurity is not implanted into the region RH, but may be implanted. Subsequently, sidewalls 41 and 75 are formed on both side surfaces of the gate electrodes 35 and 73, respectively. Thereafter, N-type impurities are ion-implanted into the drift layers 25 and 27 using the LOCOS oxide films 21 and 23 as a mask, and at the same time, N well is added to the well layer 67 in the region RL using the gate electrode 73 and the sidewall 75 as a mask. Ions of type impurities are implanted. Thus, as shown in FIG. 10C, the high concentration regions 37 and 39 are formed in the drift layers 25 and 27, and the source / drain regions 81 and 83 are formed in the well layer 67, respectively.

  In the subsequent steps, electrical connection is performed using a standard multilayer wiring process. That is, as shown in FIG. 10C, the interlayer insulating film 43 is formed, and the holes having the bottom surfaces of the high concentration regions 37 and 39 and the source / drain regions 81 and 83 are formed through the interlayer insulating film 43. Each of these holes is filled with an electrode material (for example, W). As a result, W plugs 45, 47, 85, 87 that are electrically connected are formed in the drift layers 25, 27 and the source / drain regions 81, 83, respectively.

Finally, a metal wiring film (not shown) is formed on the interlayer insulating film 43 on which the W plugs 45, 47, 85, 87 are formed, and the metal wiring film is patterned. Thus, source electrodes 49 and 89 and drain electrodes 51 and 91 electrically connected to the W plugs 45, 47, 85, and 87 are formed.
Through the above steps, the semiconductor device 102 including the medium breakdown voltage semiconductor element HV1 and the low breakdown voltage semiconductor element LV shown in FIG. 7 on the same substrate is completed.

  In this embodiment, the region RL (the formation region of the low breakdown voltage semiconductor element LV) corresponds to the second element formation region of the present invention. The LOCOS oxide film 65 corresponds to the second element isolation film of the present invention. The well layer 67 corresponds to the second well layer of the present invention. The gate insulating film 71 and the gate electrode 73 correspond to the second gate insulating film and the second gate electrode of the present invention. The source region 81 and the low concentration region 77 correspond to the second source region of the present invention. The drain region 83 and the low concentration region 79 correspond to the second drain region of the present invention. The source electrode 89 and the drain electrode 91 correspond to the second source electrode and the second drain electrode of the present invention.

(Modification)
In the present embodiment, the method of manufacturing the low breakdown voltage semiconductor element LV that is an NMOS transistor while manufacturing the medium breakdown voltage semiconductor element HV1 has been described. However, the present invention is not limited to this. By using the manufacturing method according to the present embodiment, for example, by changing the polarity of the impurity to be implanted, the medium withstand voltage semiconductor element HV1 can be manufactured and the low withstand voltage semiconductor element that is a PMOS transistor can be manufactured.

<Fourth embodiment>
(Constitution)
FIG. 11 is a cross-sectional view showing a configuration example of a semiconductor device according to the fourth embodiment of the present invention. As shown in FIG. 11, the semiconductor device 103 according to the present embodiment is a semiconductor device provided with a medium breakdown voltage semiconductor element HV2 and a low breakdown voltage semiconductor element LV on the same substrate. Here, the structure of the medium voltage semiconductor element HV2 according to the present embodiment is the same as the structure of the medium voltage semiconductor element HV2 described in the second embodiment. The structure of the low breakdown voltage semiconductor element LV according to the present embodiment is the same as the structure of the low breakdown voltage semiconductor element LV described in the third embodiment. That is, the semiconductor device 103 according to the present embodiment is obtained by mounting the medium withstand voltage semiconductor element HV2 described in the second embodiment and the low withstand voltage semiconductor element LV described in the third embodiment on the same substrate. Therefore, in the present embodiment, the description of the structures of the medium withstand voltage semiconductor element HV2 and the low withstand voltage semiconductor element LV is omitted. Hereinafter, for convenience, the formation region of the medium breakdown voltage semiconductor element HV2 included in the Si substrate 1 is referred to as “region RH”, and the formation region of the low breakdown voltage semiconductor element LV is referred to as “region RL”.

(Production method)
Next, a method for manufacturing the semiconductor device 103 according to the fourth embodiment will be described with reference to FIGS.
12 to 14 are manufacturing process cross-sectional views illustrating the order of processes in the method of manufacturing a semiconductor device according to the fourth embodiment of the present invention. In each drawing, the left side shows a region RH, and the right side shows a region RL. That is, the medium withstand voltage semiconductor element HV2 is formed on the left side of the drawing, and the low withstand voltage semiconductor element LV is formed on the right side of the drawing. Note that the method for manufacturing the medium voltage semiconductor element HV2 according to the present embodiment is the same as the method for manufacturing the medium voltage semiconductor element HV2 described in the second embodiment. Therefore, the method of manufacturing the medium withstand voltage semiconductor element HV2 will be described by omitting as appropriate.

  In the method for manufacturing the semiconductor device 103 according to the present embodiment, first, a P-type Si substrate 1 is prepared. Next, N-type impurities are ion-implanted into the surface layer portion of the Si substrate 1 in the region RH. At this time, N-type impurities are not ion-implanted into the Si substrate 1 in the region RL. Thereafter, heat is applied to the Si substrate 1 to thermally diffuse the N-type impurity ions implanted into the Si substrate 1. Thus, as shown in FIG. 12A, the N type drift layer 53 is formed on the Si substrate 1 in the region RH.

Next, as shown in FIG. 12B, an oxide film 13 is formed so as to cover the entire surface of the Si substrate 1. That is, the oxide film 13 is formed on the surface of the drift layer 53 in the region RH and the surface of the Si substrate 1 in the region RL. The oxide film 13 is a film made of, for example, SiO ₂ . Subsequently, the SiN films 15 and 63 are formed so as to cover the contact hole forming regions 44a and 46a in the region RH and a part of the region RL (second gate insulating film, second drain region, and second source region). Form.

Next, a thermal oxidation process using the SiN films 15 and 63 as a mask is performed. By this thermal oxidation treatment, LOCOS oxide films 21, 23, and 65 are formed in regions not covered with the SiN films 15 and 63. FIG. 12C shows the LOCOS oxide films 21, 23, and 65 formed by the thermal oxidation process.
Next, the LOCOS oxide films 21, 23 and 65 and the SiN films 15 and 63 are covered with a photoresist 29. Subsequently, as shown in FIG. 13A, an opening 31 is formed in the photoresist 29 in the region RH so as to expose the surface of the LOCOS oxide film 23 located above the channel region 5 in the region RH. To do. Thereafter, P-type impurities are ion-implanted into the body region 57 through the LOCOS oxide film 23. Thus, the body layer 54 is formed in the drift layer 53. In the above-described ion implantation, no P-type impurity is implanted into the region covered with the photoresist 29.

Next, as shown in FIG. 13B, the LOCOS oxide film 23 is etched using the photoresist 29 as a mask so that the channel region 5 in the region RH is exposed. Note that the LOCOS oxide film 65 in the region RL is not etched because it is covered with the photoresist 29.
Next, the photoresist 29 is removed. Subsequently, as shown in FIG. 13C, a gate oxide film 33 is formed on the body layer 54 by performing a thermal oxidation process on the surface of the body layer 54.

  The steps after the formation of the gate oxide film 33 are the same as those described in the third embodiment, and the steps shown in FIGS. 14A to 14C are the same as those shown in FIGS. These correspond to the steps shown in c). That is, as shown in FIG. 14A, the SiN films 15 and 63 and the oxide film 13 formed in the region RH and the region RL are sequentially removed. Then, a well layer 67 is formed in the region RL. Then, as shown in FIG. 14B, after forming the gate oxide film 71 in the region RL, the gate electrodes 35 and 73 are formed in the region RH and the region RL. Then, as shown in FIG. 14C, low concentration regions 77 and 79 are formed in the region RL, and high concentration regions 37 and 39 and source / drain regions 81 and 83 are formed in the region RH and the region RL, respectively. Finally, an interlayer insulating film 43, W plugs 45, 47, 85, 87, source electrodes 49, 89, and drain electrodes 51, 91 are sequentially formed in the region RH and the region RL.

Through the above steps, the semiconductor device 103 including the medium breakdown voltage semiconductor element HV2 and the low breakdown voltage semiconductor element LV shown in FIG. 11 on the same substrate is completed.
In this embodiment, the region RL (the formation region of the low breakdown voltage semiconductor element LV) corresponds to the second element formation region of the present invention. The LOCOS oxide film 65 corresponds to the second element isolation film of the present invention. The well layer 67 corresponds to the second well layer of the present invention. The gate insulating film 71 and the gate electrode 73 correspond to the second gate insulating film and the second gate electrode of the present invention. The source region 81 and the low concentration region 77 correspond to the second source region of the present invention. The drain region 83 and the low concentration region 79 correspond to the second drain region of the present invention. The source electrode 89 and the drain electrode 91 correspond to the second source electrode and the second drain electrode of the present invention.

(Modification)
In the present embodiment, the method of manufacturing the low withstand voltage semiconductor element LV that is an NMOS transistor while manufacturing the medium withstand voltage semiconductor element HV2 has been described. However, the present invention is not limited to this. By using the manufacturing method according to the present embodiment, for example, by changing the polarity of the impurity to be implanted, the medium breakdown voltage semiconductor element HV2 can be manufactured and the low breakdown voltage semiconductor element that is a PMOS transistor can be manufactured.

(Effect of embodiment)
The above-described embodiment has the following effects.
(1) In the above-described embodiments, the surface 33 a of the gate oxide film 33 is located at the same position as the surface 23 a of the LOCOS oxide film 23 in the depth direction from the main surface of the Si substrate 1 to the back surface of the Si substrate 1. Alternatively, the LOCOS oxide film 23 is provided at a deeper position away from the gate electrode 35 than the surface 23 a of the LOCOS oxide film 23. Therefore, the step between the surface 33a of the gate oxide film 33 and the surface 23a of the LOCOS oxide film 23 can be reduced in the depth direction as compared with the prior art. By doing so, since the current passes through a substantially constant depth in the drift layers 25 and 27, the uniformity of the impurity ion concentration in the current path R1 can be improved. Therefore, the impurity ion concentration in the current path R1 can be easily optimized, and the on-resistance can be efficiently reduced.

  Further, by reducing the step between the surface 33a of the gate oxide film 33 and the surface 23a of the LOCOS oxide film 23 in the depth direction, an angle at which the electric field concentrates on the gate oxide film 33 side of the LOCOS oxide film 23 is obtained. The part is difficult to be formed. For this reason, even when a voltage is applied to the gate electrode 35, it is possible to reduce electric field concentration occurring at the corner 23b of the LOCOS oxide film 23. Therefore, deterioration and breakage of the semiconductor element due to the electric field concentration can be reduced.

(2) In the above-described embodiments, since the element isolation film is the LOCOS oxide film 21, it is possible to easily form an element isolation film with high pressure resistance.
(3) In each of the above embodiments, since the gate oxide film 33 is a thermal oxide film, the surface 33a of the gate oxide film 33 is located at the same position as the surface 23a of the LOCOS oxide film 23, or the LOCOS oxide film. 23 can be easily provided at a position farther from the gate electrode 35 than the surface 23a of the surface 23a.

(4) In the above-described embodiments, the surface 33a of the gate oxide film 33 is provided at a deeper position away from the gate electrode 35 than the surface 23a of the LOCOS oxide film 23 in the depth direction of the Si substrate 1. It has been. For this reason, the surface 33a of the gate oxide film 33 can be brought close to the position of the impurity ion concentration peak contained in the drift layers 25 and 27, respectively. For this reason, the uniformity of the impurity ion concentration in the current path R1 can be increased, and the on-resistance can be efficiently reduced.

(5) In the above embodiments, in the depth direction of the Si substrate 1, the surface of the gate oxide film 33 is at the same position as the position of the concentration peak of impurity ions contained in the drift layers 25 and 27, respectively. Is provided. By doing so, the impurity ion concentration in the current path R1 is optimized, and the on-resistance can be efficiently reduced.

(6) In the above-described embodiments, the LOCOS oxide film 23 formed on the channel region 5 is removed to expose the channel region 5, and then the LOCOS oxide film 23 is formed on the channel region 5. A gate oxide film 33 is formed. Therefore, the step between the surface 33a of the gate oxide film 33 and the surface 23a of the LOCOS oxide film 23 can be reduced in the depth direction as compared with the prior art. By doing so, since the current passes through a substantially constant depth in the drift layers 25 and 27, the uniformity of the impurity ion concentration in the current path R1 can be improved. Therefore, the impurity ion concentration in the current path R1 can be easily optimized, and the on-resistance can be efficiently reduced.

Further, by reducing the step between the surface 33a of the gate oxide film 33 and the surface 23a of the LOCOS oxide film 23 in the depth direction, an angle at which the electric field concentrates on the gate oxide film 33 side of the LOCOS oxide film 23 is obtained. The part is difficult to be formed. For this reason, even when a voltage is applied to the gate electrode 35, it is possible to reduce electric field concentration occurring at the corner 23b of the LOCOS oxide film 23. Therefore, deterioration and breakage of the semiconductor element due to the electric field concentration can be reduced.
(7) In the above-described embodiments, the LOCOS oxide film 23 is removed only on the channel region 5 when the channel region 5 is exposed. Therefore, the intermediate breakdown voltage gate oxide film 33 can be selectively formed only in the channel region 5.

(8) In each of the above-described embodiments, when forming the gate oxide film 33, the surface 33 a of the gate oxide film 33 is the surface 23 a of the LOCOS oxide film 23 in the depth direction of the Si substrate 1. The formation of the gate oxide film 33 is continued until it reaches the same position as that of the LOCOS oxide film 23 or a position deeper than the gate electrode 35 from the surface 23a of the LOCOS oxide film 23. Therefore, the step between the surface 33a of the gate oxide film 33 and the surface 23a of the LOCOS oxide film 23 can be reduced in the depth direction as compared with the prior art. By doing so, since the current passes through a substantially constant depth in the drift layers 25 and 27, the uniformity of the impurity ion concentration in the current path R1 can be improved.
Further, by reducing the step between the surface 33a of the gate oxide film 33 and the surface 23a of the LOCOS oxide film 23 in the depth direction, an angle at which the electric field concentrates on the gate oxide film 33 side of the LOCOS oxide film 23 is obtained. The part is difficult to be formed.

(9) In each of the above-described embodiments, when forming the gate oxide film 33, the surface 33 a of the gate oxide film 33 is formed on the drift layers 25 and 27 in the depth direction of the Si substrate 1, respectively. The formation of the gate oxide film 33 is continued until it reaches the same position as the concentration peak of the impurity ions contained. For this reason, the impurity ion concentration in the current path R1 is optimized, and the on-resistance can be efficiently reduced.

(10) According to the above embodiment, a semiconductor device in which the medium withstand voltage semiconductor element HV1 (HV2) and the low withstand voltage semiconductor element LV are mixedly mounted on the same substrate can be manufactured. More specifically, the gate electrode 35 of the medium withstand voltage semiconductor element HV1 (HV2) and the gate electrode 73 of the low withstand voltage semiconductor element LV can be formed simultaneously. Further, the source electrode 49 and the drain electrode 51 of the medium withstand voltage semiconductor element HV1 (HV2) and the source electrode 89 and the drain electrode 91 of the low withstand voltage semiconductor element LV can be formed simultaneously. For this reason, when manufacturing a semiconductor device in which the medium breakdown voltage semiconductor element HV1 (HV2) and the low breakdown voltage semiconductor element LV are mixedly mounted on the same substrate, the number of manufacturing steps can be reduced as compared with the prior art.
(11) In the above embodiment, the LOCOS oxidation is performed after the SiN films 15 and 63 are formed, and the LOCOS oxide films 21, 23, and 65 are formed. For this reason, the LOCOS oxide films 21, 23, 65 can be formed in a predetermined region with increased reliability.

<Others>
The present invention is not limited to the embodiment described above. Based on the knowledge of those skilled in the art, design changes and the like can be made to the embodiments, and such a modified embodiment is also included in the scope of the present invention. In other words, the present invention can be implemented with various modifications within the scope of the gist. In the drawings, positional relationships such as up, down, left and right are based on the positional relationships shown in the drawings unless otherwise specified. Further, the dimensional ratios in the drawings are not limited to the illustrated ratios.

1 Si substrate 3, 67 well layer 5, 69 channel region 7, 29 photoresist 9, 11 impurity ion implantation layer 13 oxide film 15, 63 SiN film 21, 23, 65 LOCOS oxide film (element isolation film)
23a, 33a Surface 23b Corners 25, 27, 53, 59, 61 Drift layer 25a, 27a Interface 31 Opening 33, 71 Gate oxide film (thermal oxide film)
35, 73 Gate electrodes 37, 39, High concentration regions 41, 75 Side walls 43 Interlayer insulating films 44, 46 Contact holes 44a, 46a Contact hole forming regions 45, 47, 85, 87 W plugs 49, 89 Source electrodes 51, 91 Drain electrode 54 Body layer 57 Body region 77, 79 Low concentration region 81 Source region 83 Drain region 100, 101, 102, 103 Semiconductor device RH, RL regions HV1, HV2, HV3 Medium breakdown voltage semiconductor element LV Low breakdown voltage semiconductor elements R1, R2 Current path

Claims (13)

A semiconductor substrate comprising a drain region and a source region;
A gate oxide film formed on a channel region sandwiched between the drain region and the source region;
A gate electrode formed on the gate oxide film;
A drain electrode formed in a part on the drain region;
A source electrode formed in a part on the source region;
An element isolation film formed so as to cover an end portion of the drain region on the channel region side and an end portion of the source region on the channel region side, and continuous with the gate oxide film,
In the depth direction from the main surface of the semiconductor substrate, which is the formation surface of the gate oxide film and the element isolation film, to the back surface of the semiconductor substrate, the surface of the gate oxide film on the semiconductor substrate side is the element isolation film A semiconductor element provided at the same position as the surface on the semiconductor substrate side, or at a deeper position away from the gate electrode than the surface on the semiconductor substrate side of the element isolation film.   The semiconductor element according to claim 1, wherein the element isolation film is a LOCOS oxide film.   The semiconductor element according to claim 1, wherein the gate oxide film is a thermal oxide film.   The surface of the gate oxide film on the semiconductor substrate side in the depth direction is provided at a deeper position away from the gate electrode than the surface of the element isolation film on the semiconductor substrate side. 4. The semiconductor element according to any one of 3.   In the depth direction, the surface of the gate oxide film on the semiconductor substrate side is included in the drain region and the source region, respectively, and is provided at the same position as the concentration peak of impurity ions contributing to conductivity. The semiconductor device according to any one of claims 1 to 4. Forming a first drain region and a first source region in a first element formation region included in the semiconductor substrate;
A first channel region sandwiched between the first drain region and the first source region; an end of the first drain region on the first channel region side; and the first channel region of the first source region. Forming a first element isolation film integrally covering the side end portion;
Removing the first element isolation film formed on the first channel region to expose the first channel region;
Forming a first gate oxide film continuous with the first element isolation film on the exposed first channel region;
Forming a first gate electrode on the first gate oxide film;
Forming a first drain electrode on the first drain region and forming a first source electrode on the first source region after forming the first gate electrode. Injecting a second conductivity type impurity into the first element formation region included in the first conductivity type semiconductor substrate, and forming a first well layer in the first element formation region;
Forming a first isolation layer on a portion of the first well layer;
Injecting the first conductivity type impurity into a part of the first well layer through the first element isolation film to form a body layer including a first channel region in the first well layer;
Removing the first element isolation film formed on the first channel region to expose the first channel region;
Forming a first gate oxide film continuous with the first element isolation film on the exposed first channel region;
Forming a first gate electrode on the first gate oxide film;
After the formation of the first gate electrode, a first drain electrode is formed on a first drain region which is one of the first well layers facing each other across the first channel region, and in the other region Forming a first source electrode on a certain first source region. A method for manufacturing a semiconductor device.   8. The method of manufacturing a semiconductor device according to claim 6, wherein in the step of exposing the first channel region, the first element isolation film is removed only on the first channel region.   In the step of forming the first gate oxide film, in the depth direction from the main surface of the semiconductor substrate, which is the formation surface of the first gate oxide film and the first element isolation film, to the back surface of the semiconductor substrate, The surface of the first gate oxide film on the semiconductor substrate side is the same position as the surface of the first element isolation film on the semiconductor substrate side or the surface of the first element isolation film on the semiconductor substrate side. 9. The method of manufacturing a semiconductor device according to claim 6, wherein the formation of the first gate oxide film is continued until reaching a deep position away from the electrode.   In the step of forming the first gate oxide film, in the depth direction, the surface of the first gate oxide film on the semiconductor substrate side is included in the first drain region and the first source region, respectively, 10. The method of manufacturing a semiconductor device according to claim 6, wherein the formation of the first gate oxide film is continued until reaching the same position as the position of the concentration peak of impurity ions contributing to the property. Simultaneously with the step of forming the first element isolation film, forming a second element isolation film in a part of the second element formation region included in the semiconductor substrate and different from the first element formation region;
After the step of forming the first gate oxide film, introducing the first conductivity type or the second conductivity type impurity into the second element formation region to form a second well layer;
Forming a second gate insulating film in the second element formation region after the step of forming the second well layer and before the step of forming the first gate electrode;
Forming the second gate electrode on the second gate insulating film simultaneously with the step of forming the first gate electrode;
After the step of forming the second gate electrode and before the step of forming the first drain electrode and the first source electrode, a second drain is formed in the second element formation region exposed from below the second gate electrode. Forming a region and a second source region;
A step of forming a second drain electrode on the second drain region and a second source electrode on the second source region simultaneously with the step of forming the first drain electrode and the first source electrode; Furthermore, the manufacturing method of the semiconductor element as described in any one of Claims 6-10 which has further.   In the step of forming the first element isolation film, a SiN film is formed on a region where the first source electrode and the first drain electrode are formed, and then LOCOS oxidation is performed to form the first element isolation film. The manufacturing method of the semiconductor element as described in any one of Claim 6 to 10 formed.   In the step of forming the first element isolation film, the second gate insulating film, the second drain region, and the second source region are formed on a region where the first source electrode and the first drain electrode are formed. 12. The method of manufacturing a semiconductor element according to claim 11, wherein a SiN film is formed and then LOCOS oxidation is performed to form the first element isolation film and the second element isolation film.

Images