JPH08264775A - High breakdown voltage mos transistor and its manufacture - Google Patents

Abstract

PURPOSE: To enable miniaturizing and flattening of a high breakdown voltage MOS transistor, by forming a gate region by burying a poly silicon layer in a hole, via a gate oxide film formed in the bottom of the hole formed by penetrating an LPCOS oxide film. CONSTITUTION: As interlayer insulating films, an SiO2 film 19 1500Å thick and a BPSG film 20 6000Å thick are laminated on the whole surface of a substrate by an LPCVD method. After contact holes are formed on P<+> type drain diffusion layers 15, 17 and P<+> type source diffusion layers 16, 18, an aluminum layer is formed and etched, and Al electrodes are formed in the contact holes. In a high breakdown voltage MOS transistor manufactured in the above manner, a channel region can be formed right under the LOCOS oxide film 4, fine structure is realized, breakdown voltage of about 40V can be obtained between a source and a drain. Since a poly silicon layer is buried in the LOCOS oxide film, flattening is enabled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to miniaturization of high breakdown voltage MOS transistors.

[0002]

2. Description of the Related Art A high withstand voltage transistor of this type will be described with reference to FIGS. Reference numeral 51 shown in FIG. 11 is a semiconductor substrate of one conductivity type, for example, an N type silicon substrate, on which an SiO 2 film 52 is formed.
Then, boron ions (11B +) are implanted into the substrate 51 using the resist film 53 as a mask to form a P- type ion implantation region 54.

Next, after removing the resist film 53, thermal diffusion is performed at about 1200 ° C., and as shown in FIG.
-Form the type diffusion layer 55. Then, after removing the SiO2 film 52, thermal oxidation is performed at about 900 ° C. to form an SiO2 film 56 on the substrate 51 as shown in FIG. 13, and the SiN film having a film thickness of about 1000 Å is formed on the SiO2 film 56. The film 57 is formed. The P- type diffusion layer 5
5, the resist film 58 having an opening at a desired position above is used as a mask to perform field oxidation, and as shown in FIG. 14, a LOCOS oxide film 59 having a film thickness of about 6000Å.
To form.

Then, after removing the SiN film 57, a gate oxide film 60 having a film thickness of about 400 Å is formed as shown in FIG. 15, and a polysilicon layer 61 having a film thickness of about 4000 Å is formed thereon. After that, POCl3 is used as a diffusion source and phosphorus is diffused at about 950 ° C., and then the polysilicon layer 61 is patterned. Next, as shown in FIG. 16, with the polysilicon layer 61 as a mask, BF2 + ions are accelerated at an acceleration voltage of 80 KeV and an implantation amount of 3E15 / cm2 (3
E15 means 3 times 10 to the 15th power. The same applies hereinafter. Implantation is performed under the conditions of (1) to form a P + type region 62.

Subsequently, as shown in FIG. 17, an SiO2 film 63 having a film thickness of about 1500Å and a B film having a film thickness of about 6000Å are formed as an interlayer insulating film on the entire surface of the substrate by the LPCVD method.
The PSG film 64 is laminated. And the P + type region 62
There is a type in which an aluminum layer is formed after forming a contact hole on the top and etching is performed to form an Al electrode 65 in the contact hole.

As described above, in the conventional high breakdown voltage MOS transistor, since the P--type diffusion layer as the voltage relaxation region is formed on the entire lower surface of the LOCOS oxide film, the LOCOS is concerned.
The area of the oxide film could not be miniaturized.

[0007]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a high breakdown voltage MOS transistor which can be miniaturized.

[0008]

Therefore, the present invention provides a gate oxide film formed at the bottom of a hole formed so as to penetrate a LOCOS oxide film formed on a semiconductor substrate of one conductivity type, and And a gate region formed by burying a polysilicon layer in the hole via a gate oxide film.

The present invention also relates to a LOCOS oxide film formed on a semiconductor substrate of one conductivity type, a gate oxide film formed at the bottom of a hole formed so as to penetrate the LOCOS oxide film, A channel region formed below the gate oxide film and a gate region formed by burying a polysilicon layer in the hole via the gate oxide film are provided.

Further, according to the present invention, a LOCOS oxide film formed on a semiconductor substrate of one conductivity type, a gate oxide film formed at the bottom of a hole penetrating the LOCOS oxide film, A channel region formed below the gate oxide film, a low-concentration source / drain diffusion layer formed adjacent to the channel region, and a polysilicon layer embedded in the hole through the gate oxide film. The formed gate region is provided.

The present invention also provides a step of forming a LOCOS oxide film on a semiconductor substrate of one conductivity type, a step of forming low concentration source / drain diffusion layers on both sides of the LOCOS oxide film, and a step of forming the LOCOS oxide film. The LO in the center of the film
A step of forming a hole so as to penetrate the COS oxide film, a step of forming a gate oxide film at the bottom of the hole, and a step of burying a polysilicon layer in the hole via the gate oxide film. I have.

[0012]

With the above structure, in the high withstand voltage MOS transistor of the present invention, since the channel region can be formed immediately below the LOCOS oxide film, miniaturization can be achieved. Further, since the polysilicon layer to be the gate region is embedded in the LOCOS oxide film, it becomes possible to flatten.

[0013]

An embodiment of the present invention will be described in detail below with reference to the drawings. In this embodiment, a high voltage MOS transistor (formed on the left side in the drawing) and a normal MOS transistor (formed on the right side in the drawing) are simultaneously manufactured. It will be described with reference to the drawings.

Reference numeral 1 shown in FIG. 1 is a semiconductor substrate of one conductivity type, for example, an N-type silicon substrate.
After forming a SiN film having a film thickness of about 1000 Å on the SiO 2 film 2 having a film thickness of 0 Å, the SiN film 3 is etched by using a resist film (not shown) as a mask to remove the portion where the SiN film 3 is removed. Approximately 7,000Å after field oxidation
A LOCOS oxide film 4 having a film thickness of is formed.

Next, as shown in FIG. 2, after removing the SiN film 3, boron ions () are formed through a resist film 5 having an opening on a low-concentration drain / source diffusion layer forming region of a high breakdown voltage MOS transistor which will be described later. 11B +) is implanted under the conditions of an accelerating voltage of 140 KeV and an implantation amount of 1E14 / cm @ 2 to form a first ion implantation region 6 immediately below the LOCOS oxide film 4 except a channel region forming position described later. Subsequently, diffusion is performed to form a P- type drain diffusion layer 7 and a P- type source diffusion layer 8 as shown in FIG.

Next, as shown in FIG. 4, the LOCOS oxide film 4 is anisotropically etched through a resist film 9 having an opening with a width of about 1 μm on the LOCOS oxide film 4 on the high breakdown voltage MOS transistor side. Then, a polysilicon burying hole 10 is formed through the LOCOS oxide film 4 and etching is completed on the substrate surface. The embedded hole 10
The width of the groove is about half of the polysilicon film thickness, which is the channel length. For example, when the width is 1 μm, the polysilicon film thickness is about 5000 Å.

Next, after removing the resist film 9 and the SiO2 film 2 as shown in FIG.
A gate oxide film 11 having a film thickness of 0Å is formed. Then, as shown in FIG. 6, boron ions (11B +) are implanted over the entire surface of the substrate under the conditions of an accelerating voltage of 35 KeV and an implantation dose of 2E12 / cm2 for adjusting the threshold voltage, and phosphorus ions for preventing short channels. (31P +) is implanted under the conditions of an accelerating voltage of 200 KeV and an implantation dose of 1E12 / cm @ 2 to form the second ion implantation region 12. Then, a polysilicon layer having a thickness of about 5000Å is formed on the entire surface of the substrate, and phosphorus is diffused at about 950 ° C. using PoCl 3 as a diffusion source. Then, as shown in FIG. 7, after forming the polysilicon layer 13 on the substrate, a resist film 14 is formed on the polysilicon layer 13 on the gate oxide film 11 in the normal MOS transistor formation region, and the resist film 14 is formed. Is used as a mask to etch the polysilicon layer 13. As a result, as shown in FIG. 8, the polysilicon layer 1 is formed in the polysilicon buried hole 10 and on the normal MOS transistor formation region.
3 remains.

Next, after removing the resist film 14, FIG.
As shown in, BF2 + ions are accelerated by about 80 Ke.
V +, the implantation amount is 3E15, and high-concentration P + type drain diffusion layers 15, 17 and P + type source diffusion layer 16,
18 is formed. Then, as shown in FIG. 10, about 1500 is formed on the entire surface of the substrate as an interlayer insulating film by the LPCVD method.
A SiO2 film 19 having a film thickness of Å and a BPSG film 20 having a film thickness of approximately 6000Å are laminated. Then, the P + type drain diffusion layers 15 and 17 and the P + type source diffusion layers 16 and 1
After forming a contact hole on each of the eight, an aluminum layer is formed and etched to form Al in the contact hole.
The electrode 21 is formed.

Through the above steps, a high breakdown voltage MOS transistor and a normal MOS transistor are simultaneously formed.
Further, in the high withstand voltage MOS transistor manufactured as described above, a channel region can be formed immediately below the LOCOS oxide film 4 as shown in FIG.
As compared with a P-type diffusion layer serving as a voltage relaxation region formed on the entire lower surface of the S oxide film, it is possible to achieve miniaturization and a source-drain breakdown voltage of about 40V.

Further, looking only at the high breakdown voltage transistor of the present invention, since the polysilicon layer to be the gate region is buried in the LOCOS oxide film, it becomes possible to flatten it.

[0021]

As described above, since the channel region can be formed directly under the LOCOS oxide film in the high withstand voltage MOS transistor of the present invention, the P-type diffusion layer as the voltage relaxation region is formed under the entire surface of the conventional LOCOS oxide film. It can be miniaturized compared to things. Further, since the polysilicon layer to be the gate region is buried in the LOCOS oxide film, it is possible to flatten it.

Furthermore, a high voltage MOS transistor and a normal MOS transistor can be formed at the same time.

[Brief description of drawings]

FIG. 1 is a first cross-sectional view showing a manufacturing process of a high breakdown voltage MOS transistor of the present invention.

FIG. 2 is a second cross-sectional view showing the manufacturing process of the high breakdown voltage MOS transistor of the present invention.

FIG. 3 is a third cross-sectional view showing the manufacturing process of the high breakdown voltage MOS transistor of the present invention.

FIG. 4 is a fourth cross-sectional view showing the manufacturing process of the high breakdown voltage MOS transistor of the present invention.

FIG. 5 is a fifth cross-sectional view showing the manufacturing process of the high breakdown voltage MOS transistor of the present invention.

FIG. 6 is a sixth cross-sectional view showing the manufacturing process of the high breakdown voltage MOS transistor of the present invention.

FIG. 7 is a seventh cross-sectional view showing the manufacturing process of the high breakdown voltage MOS transistor of the present invention.

FIG. 8 is an eighth cross-sectional view showing the manufacturing process of the high breakdown voltage MOS transistor of the present invention.

FIG. 9 is a ninth cross-sectional view showing the manufacturing process of the high breakdown voltage MOS transistor of the present invention.

FIG. 10 is a tenth cross-sectional view showing the manufacturing process of the high breakdown voltage MOS transistor of the present invention.

FIG. 11 is a cross-sectional view of a conventional high voltage MOS transistor.

FIG. 12 is a cross-sectional view of a conventional high voltage MOS transistor.

FIG. 13 is a cross-sectional view of a conventional high voltage MOS transistor.

FIG. 14 is a cross-sectional view of a conventional high voltage MOS transistor.

FIG. 15 is a cross-sectional view of a conventional high voltage MOS transistor.

FIG. 16 is a cross-sectional view of a conventional high voltage MOS transistor.

FIG. 17 is a cross-sectional view of a conventional high voltage MOS transistor.

Claims (4)

[Claims] 1. An L formed on a semiconductor substrate of one conductivity type.
A gate oxide film formed at the bottom of a hole formed so as to penetrate the OCOS oxide film; and a gate region formed by burying a polysilicon layer in the hole through the gate oxide film. A high breakdown voltage MOS transistor characterized in that. 2. An L formed on a semiconductor substrate of one conductivity type.
The OCOS oxide film, the gate oxide film formed at the bottom of the hole formed to penetrate the LOCOS oxide film, the channel region formed below the gate oxide film, and the gate oxide film. A high breakdown voltage MOS transistor having a gate region formed by burying a polysilicon layer in the hole. 3. An L formed on a semiconductor substrate of one conductivity type.
An OCOS oxide film, a gate oxide film formed at the bottom of a hole formed so as to penetrate the LOCOS oxide film, a channel region formed below the gate oxide film, and adjacent to the channel region. Low concentration sauce formed
A high breakdown voltage MOS transistor comprising a drain diffusion layer and a gate region formed by burying a polysilicon layer in the hole via the gate oxide film. 4. A step of forming a LOCOS oxide film on a semiconductor substrate of one conductivity type, a step of forming low concentration source / drain diffusion layers on both sides of the LOCOS oxide film, and a center of the LOCOS oxide film. A hole to penetrate the LOCOS oxide film, a step of forming a gate oxide film at the bottom of the hole, and a polysilicon layer embedded in the hole through the gate oxide film. High withstand voltage MOS characterized by having steps
Manufacturing method of transistor.