JP2008153346A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method which can achieve a power management semiconductor device and an analog semiconductor device which are low cost, can be shortened in manufacturing period, use less power, and have a high driving performance and a high accuracy. <P>SOLUTION: In the manufacturing method for a power management semiconductor device and an analog semiconductor device which include a CMOS, the resistance of a drain region is reduced at surge input by expanding upwards a silicon region which constitutes a lightly doped drain and thermal destruction is suppressed by suppressing a local increase in temperature. Consequently, a power management semiconductor device and an analog semiconductor device with a higher degree of freedom in designing a transistor can be achieved. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device that requires low voltage operation, low power consumption, and high driving capability, particularly a voltage detector (Voltage Detector, hereinafter referred to as VD), a constant voltage regulator (Voltage Regulator, hereinafter referred to as VR), and a switching regulator. The present invention relates to a power management semiconductor device such as (Switching Regulator, hereinafter referred to as SWR) and a manufacturing method thereof.

  The prior art will be described with reference to FIG.

  FIG. 2 is a schematic cross-sectional view in order of steps showing a conventional method for manufacturing a semiconductor device.

In FIG. 2A, a P-type semiconductor substrate 21, for example, a boron-doped semiconductor substrate having an impurity concentration of 20 Ωcm to 30 Ωcm, a P well 22, for example, boron is added from 1 × 10 ¹¹ atoms / cm ² to 1 × 10 ^13. A diffusion layer is formed by implanting ions at a dose of atoms / cm ² and annealing at 1000 to 1200 ° C. for several hours to several tens of hours. From the field insulating film 23, for example, several thousand Å in thickness by the LOCOS method. After the 1 μm thermal oxide film is formed, the insulating film in the region where the MOS transistor is to be formed is removed, and a gate insulating film 24, for example, a thermal oxide film having a thickness of 10 nm to 100 nm is formed. Ion implantation for adjusting the impurity concentrations of the P-type semiconductor substrate 1 and the P well 22 is performed before the gate insulating film 24 is formed or after the gate insulating film 24 is formed.

  Next, in FIG. 2B, polycrystalline silicon is deposited on the gate insulating film 24, impurities are introduced by pre-deposition or ion implantation, and patterning is performed, thereby forming a polycrystalline silicon gate 25 serving as a gate electrode. .

Subsequently, at a certain distance from the polycrystalline silicon gate 25, the source and drain high concentration regions 26, for example, As to reduce the sheet resistance, is preferably at a concentration of 1 × 10 ¹⁴ to 1 × 10 ¹⁶ atoms / cm ² . Ion implantation. Subsequently, the source and drain low-concentration regions 27, for example, phosphorus, for example, are ion-implanted at a concentration of preferably 1 × 10 ¹² to 1 × 10 ¹⁴ atoms / cm ² by self-alignment using the polycrystalline silicon gate 25 as a mask.

  Next, in FIG. 2C, an interlayer insulating film 28 is deposited to a thickness of about 200 nm to 800 nm.

Next, in FIG. 2D, a contact hole 29 for connecting the source and drain high concentration region 26 to the wiring is formed. Subsequently, when the wiring metal is formed and patterned by sputtering or the like, the wiring metal 30 and the surface of the high concentration source / drain region 26 are connected through the contact hole 29. (For example, see Non-Patent Document 1)
Kazuo Maeda, “First Semiconductor Process”, Industrial Research Committee, December 10, 2000, p30

  In the semiconductor device according to the above-described conventional manufacturing method, in order to ensure a certain degree of high junction breakdown voltage, surface breakdown breakdown voltage, snapback breakdown voltage, or low impact ionization rate, a drain region having a lower concentration is formed. There is a case where the ESD withstand voltage is decreasing and the ESD withstand voltage standard cannot be satisfied.

  That is, each important characteristic of the transistor and the ESD withstand voltage may not be compatible, and there is a problem that the transistor size must be increased to meet the characteristics and standards, while the increase in cost must be accepted.

  In general, the coverage of the wiring metal in the contact region is not good, and is generally about 20% of the wiring thickness on the flat portion. This is a factor that limits the current density. As a result, it is difficult to flow a large current with a small area. The present invention has been made paying attention to the above points, and the present invention is to form a transistor with a small area while satisfying a sufficient ESD withstand voltage, low cost and short TAT (Turn Around Time), An object of the present invention is to provide a manufacturing method capable of realizing a semiconductor device with low parasitic resistance and high accuracy.

In order to solve the above problems, the present invention uses the following means.
(1) A step of forming a thin oxide film region on a first conductivity type semiconductor layer on a semiconductor substrate, and a thermal oxide film thicker than the thin oxide film in a specific region on the first conductivity type semiconductor layer Forming a region having a high semiconductor surface and a region having a low semiconductor surface by removing all of the thermal oxide film on the semiconductor layer of the first conductivity type; and Forming a gate insulating film on the type semiconductor layer, forming a gate electrode on the gate insulating film, introducing an impurity into the gate electrode, and in the first conductive type semiconductor layer Forming a first impurity diffusion layer having a first concentration of a second conductivity type to be a source and a drain from directly under the gate electrode to a region having a high height of the semiconductor surface; and a second conductivity type second Second impurity diffusion with a concentration of Between the first impurity diffusion layer and the second impurity diffusion layer, a step of forming an interlayer insulating film on the semiconductor substrate, and an electrical connection between the first impurity diffusion layer and the second impurity diffusion layer. Forming a contact hole for connection in a region having a high height on the semiconductor surface, depositing a wiring metal, and connecting the first and second impurity diffusion layers and the wiring metal through the contact hole; And a method of manufacturing a semiconductor device having an electrical connection step.
(2) Thermal oxidation is performed so that the difference in height between the two regions of the semiconductor surface having a high height and a low region is 0.1 μm to 1 μm.
(3) The thick oxide film forming step is a LOCOS method using a silicon nitride film.
(4) The silicon nitride film has a thickness of 10 nm to 200 nm.

  As described above, the present invention provides a method for manufacturing a power management semiconductor device or an analog semiconductor device including a CMOS, by providing a convex portion on a part of a silicon surface, and forming a low-concentration drain region in a MOS transistor here. The volume of the low-concentration drain region expands, contributing to the reduction of drain resistance during normal circuit operation, and suppressing the temperature rise of the drain low-concentration region at the time of ESD surge input, thereby suppressing the thermal destruction of silicon. Since this is possible, the ESD withstand voltage is improved. Accordingly, the degree of freedom in setting the concentration of the drain low concentration region is increased, and it becomes easy to realize desired transistor characteristics. Furthermore, the step coverage is improved in order to make contact with the wiring metal at the convex portion, and it is possible to flow a larger current than in the past even in the same area.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a schematic cross-sectional flow showing a first embodiment of a method of manufacturing a semiconductor device according to the present invention.

In FIG. 1A, a P-type semiconductor substrate 1, for example, a boron-doped semiconductor substrate having an impurity concentration of 20 Ωcm to 30 Ωcm, and a P well 2, for example, boron is added from 1 × 10 ¹¹ atoms / cm ² to 1 × 10 ^13. A diffusion layer is formed by ion implantation at a dose of atoms / cm ² and annealing at 1000 to 1200 ° C. for several hours to tens of hours. Here, the process of forming the P well in the P-type semiconductor substrate is shown, but the same applies to the case of forming the P well in the N-type semiconductor substrate. The conductivity type of the substrate is not related to the essence of the present invention.

Subsequently, a thick oxide film 3, for example, a thermal oxide film having a thickness of 0.2 μm to 2 μm is formed by the LOCOS method. At this time, the thick oxide film 3 is not formed in the contact formation scheduled region 4. The thickness of the oxide film formed here is set so as to satisfy a desired ESD withstand voltage. That is, as the oxide film is formed thicker, the ESD withstand voltage is improved as a result. When the thick oxide film 3 is formed, the thickness of the nitride film (not shown) provided on the contact formation planned region 4 is preferably 10 nm to 200 nm, and is formed under the nitride film. The film thickness of the thin oxide film is preferably 10 nm to 40 nm, but by adjusting these film thicknesses, the shape and height of the contact with a convex silicon surface formed in the next step is After that, as shown in FIG. 1B, when the silicon oxide film on the surface is completely removed by wet etching, the silicon convex portion 5 is completed. At this time, the height of the silicon convex portion 5 is about half of the above-described thick oxide film, and is 0.1 μm to 1 μm.

  Subsequently, as shown in FIG. 1C, a field insulating film 6, for example, a thermal oxide film having a film thickness of several thousand to 1 μm is formed by the LOCOS method, and then the insulating film in the region for forming the MOS transistor is removed. Then, a gate insulating film 7, for example, a thermal oxide film having a thickness of 10 nm to 100 nm is formed. Ion implantation for adjusting the impurity concentrations of the P-type semiconductor substrate 1 and the P well 2 is performed before the gate insulating film 7 is formed or after the gate insulating film 7 is formed. Subsequently, polycrystalline silicon is deposited on the gate insulating film 7, impurities are introduced by predeposition or ion implantation, and patterning is performed, so that a polycrystalline silicon gate 8 serving as a gate electrode is formed.

Subsequently, as shown in FIG. 1D, the source and drain high-concentration regions 9 such as As are separated from the polycrystalline silicon gate 8 by a certain distance, preferably 1 × 10 6 in order to reduce the sheet resistance. Ions are implanted at a concentration of ¹⁴ to 1 × 10 ¹⁶ atoms / cm ² . Subsequently, the polycrystalline silicon gate 8 is used as a mask, and the source and drain lightly doped regions 10, for example, phosphorus, are ion-implanted at a concentration of preferably 1 × 10 ¹² to 1 × 10 ¹⁴ atoms / cm ² by self-alignment.

  Subsequently, the interlayer insulating film 6 is deposited so as to have a thickness of about 200 nm to 800 nm.

  Next, in FIG. 1D, a contact hole 11 for connecting the source and drain regions to the wiring is formed on the silicon protrusion 5. Thereafter, when the wiring metal 12 is formed by sputtering and patterned, the wiring metal 12 and the source and drain surfaces are connected through the contact holes 11.

Sectional schematic cross-sectional view showing a first embodiment of a method of manufacturing a semiconductor device according to the present invention Schematic sectional view in order of steps showing a conventional method of manufacturing a semiconductor device

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 P-type semiconductor substrate 2 P well 3 Thick oxide film 4 Contact formation area 5 Silicon convex part 6 Field insulating film 7 Gate insulating film 8 Polycrystalline silicon gate 9 Source and drain high concentration area | region 10 Source and drain low concentration area | region 11 Contact Hole 12 Wiring metal 13 Interlayer insulating film 21 P-type semiconductor substrate 22 P well 23 Field insulating film 24 Gate insulating film 25 Polycrystalline silicon gate 26 Source and drain high concentration region 27 Source and drain low concentration region 28 Interlayer insulating film 29 Contact hole 30 Wiring metal

Claims (5)

Forming a thin oxide film region on a semiconductor layer of a first conductivity type on a semiconductor substrate;
Forming a thermal oxide film thicker than the thin oxide film in a specific region on the semiconductor layer of the first conductivity type;
Removing all of the thermal oxide film on the semiconductor layer of the first conductivity type to form two regions of a high and low semiconductor surface,
Forming a gate insulating film on the first conductivity type semiconductor layer;
Forming a gate electrode on the gate insulating film;
Introducing an impurity into the gate electrode;
A first impurity diffusion layer having a second conductivity type first concentration serving as a source and a drain is formed in the first conductivity type semiconductor layer from directly under the gate electrode to a region where the semiconductor surface is high. Process,
Forming a second impurity diffusion layer having a second concentration of the second conductivity type at a position in contact with the first impurity diffusion layer;
Forming an interlayer insulating film on the semiconductor substrate;
Forming a contact hole in the region having a high height of the semiconductor surface for establishing electrical connection with the first impurity diffusion layer and the second impurity diffusion layer;
A method of manufacturing a semiconductor device, comprising: depositing a wiring metal, and electrically connecting the first and second impurity diffusion layers and the wiring metal through the contact hole.   2. The method of manufacturing a semiconductor device according to claim 1, wherein thermal oxidation is performed such that a difference in height between two regions of a high surface and a low region of the semiconductor surface is 0.1 μm to 1 μm. .   3. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the thick oxide film is a LOCOS method using a silicon nitride film.   4. The method of manufacturing a semiconductor device according to claim 3, wherein the thickness of the silicon nitride film is 10 nm to 200 nm. A semiconductor substrate;
A semiconductor region of a first conductivity type provided on the surface of the semiconductor substrate, the first conductivity type semiconductor region having two regions of a region having a high semiconductor surface and a region having a low height;
A gate insulating film provided on the semiconductor region of the first conductivity type;
A gate electrode provided on the gate insulating film;
A first impurity diffusion having a first concentration of a second conductivity type provided as a source and a drain provided immediately under the gate electrode in the first conductivity type semiconductor region to a region having a high semiconductor surface height Layers,
A second impurity diffusion layer having a second concentration of the second conductivity type provided at a position in contact with the first impurity diffusion layer;
An interlayer insulating film provided on the semiconductor substrate;
A contact hole for electrical connection with the first impurity diffusion layer and the second impurity diffusion layer provided in a region where the height of the semiconductor surface is high;
A semiconductor device comprising a wiring metal electrically connected to the first and second impurity diffusion layers through the contact hole.

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