JP2864593B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a complementary MO.
The present invention relates to a method for manufacturing a semiconductor device having an S transistor (hereinafter, referred to as a CMOS transistor).

[Conventional technology]

Wells and channel stoppers of a conventional semiconductor device having a CMOS transistor are formed by a plurality of steps of photolithography.

3 (a) to 3 (e) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a conventional method of manufacturing a semiconductor device.

As shown in FIG. 3 (a), a silicon oxide film 2 is formed to a thickness of 50 nm on the surface of a P-type silicon substrate 1, a photoresist film 31 is applied on the silicon oxide film 2 and patterned. Using the film 31 as a mask, phosphorus ions are ion-implanted to form a phosphorus ion-implanted layer 9 on the surface of the P-type silicon substrate 1.

Next, as shown in FIG. 3B, a photoresist film 31 is formed.
Is removed, a photoresist film 32 is coated on the silicon oxide film 2 and patterned, and boron ions are ion-implanted using the photoresist film 32 as a mask to form a phosphorus ion-implanted layer 9.
Boron ion implanted layer on the surface of P-type silicon substrate 1 other than
Form 12.

Next, as shown in FIG.
Is removed, and impurities in the phosphorus ion implanted layer 9 and the boron ion implanted layer 12 are diffused by heat treatment to form an N-type well 11 and a P-type well 15.

Next, as shown in FIG.
Silicon nitride films 3a and 3b are deposited on the substrate and selectively etched to form a mask corresponding to an element formation region on each of the N-type well 11 and the P-type well 15. Next, a photoresist film 3 is formed on the surface including the silicon nitride films 3a and 3b.
3 is applied and patterned, and a hole is formed in the region of the P-type well 15. Next, boron ions are implanted using the photoresist film 33 and the silicon nitride film 3 as a mask to form a boron ion implanted layer 13 on the surface of the P-type well.

Next, as shown in FIG.
Is removed, a field oxide film 14 is formed by a selective oxidation method using the silicon nitride films 3a and 3b as a mask, and a channel stopper 16 is formed by partitioning an element formation region and activating the boron ion implantation layer 13.

[Problems to be solved by the invention]

The above-described conventional method of manufacturing a semiconductor device requires two photolithography steps to form an N-type well and a P-type well, and further requires an additional photolithography step to form a channel stopper. It is. This photolithography process is the process with the most man-hours.
A single photolithography process is not preferable in terms of cost and yield.

In addition, the impurity concentration in a portion where the N-type well, the P-type well and the channel stopper contact each other is different due to misalignment in the photolithography process. Therefore, the well breakdown voltage and the latch-up resistance, which are affected by the impurity concentration, differ for each manufacturing lot or each semiconductor chip, and in order to ensure sufficient latch-up resistance, a large space is required between the N-channel and P-channel MOS transistors. And there is a problem that the improvement of the degree of integration is hindered.

[Means for solving the problem]

According to the method of manufacturing a semiconductor device of the present invention, a first silicon nitride film is selectively formed on an oxide film provided on one main surface of a semiconductor substrate of one conductivity type to form first and second element formation regions. Forming a mask corresponding to the above, and sequentially depositing a first silicon oxide film, a polycrystalline silicon film, a second silicon oxide film, and a second silicon nitride on a surface including the first silicon nitride film. And providing the second silicon nitride film in a region including the first silicon nitride film on the first element formation region by using a photoresist film selectively provided on the second silicon nitride film as a mask. Silicon nitride film and second
Selectively etching and removing the silicon oxide film, and ion-implanting an impurity of a reverse conductivity type using the photomask as a mask to form a well of a reverse conductivity type on the surface of the semiconductor substrate in the first element formation region. Removing the photoresist film, oxidizing the polycrystalline silicon film using the second silicon nitride film as a mask to form a third silicon oxide film, and using the third silicon oxide film as a mask A step of sequentially etching and removing the second silicon nitride film, the second silicon oxide film, and the polycrystalline silicon film; and ion-implanting one conductivity type impurity using the third silicon oxide film as a mask. Forming a well of one conductivity type on the surface of the semiconductor substrate in the second element formation region; and forming the first silicon nitride film on the second element formation region. Forming a channel stopper made shallow ion implantation of impurity of one conductivity type as a disk,
A step of sequentially removing the third silicon oxide film and the first silicon oxide film; and selectively oxidizing a surface of the semiconductor substrate using the first silicon nitride film as a mask to form the first and second element formation regions. Forming a field oxide film for partitioning the substrate.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

1 (a) to 1 (i) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a first embodiment of the present invention.

First, as shown in FIG. 1A, a silicon oxide film 2 is formed to a thickness of 50 nm on a P-type silicon substrate 1, and a silicon nitride film is deposited on the silicon oxide film 2 to a thickness of 0.2 μm. Then, selective etching is performed by photolithography to form silicon nitride films 3a and 3b serving as masks in regions corresponding to the first and second element formation regions.

Next, as shown in FIG.
20 nm thick silicon oxide film 4 on the surface including a and 3b and thickness
A polycrystalline silicon film 5 of 0.1 to 0.2 μm is sequentially deposited, and a 20 nm thick silicon oxide film 6 is further formed on the polycrystalline silicon film 5.
And a silicon nitride film 7 having a thickness of 0.1 μm is sequentially deposited.

Next, as shown in FIG.
A photoresist film 8 is applied thereon and patterned, and the silicon nitride film 7 and the silicon oxide film 6 are sequentially etched and removed using the photoresist film 8 as a mask. next,
Phosphorus ion acceleration energy 500keV, dose 1-5 ×
Ion implantation is performed at 10 ¹³ cm ⁻² to form a phosphorus ion implantation layer 9.

Next, as shown in FIG.
Is removed, the polycrystalline silicon film 5 is thermally oxidized using the silicon nitride film 7 as a mask so that the silicon oxide film 10
It is formed to a thickness of 0.4 μm. The heat treatment at this time activates the phosphorus ion implanted layer 9 to form the N-type well 11.

Next, as shown in FIG.
And the silicon oxide film 6 and the polycrystalline silicon film 5 are sequentially removed by etching, and boron ions are accelerated using the silicon oxide film 10 as a mask at an acceleration energy of 300 keV and a dose of 1-5.
Ion implantation is performed at × 10 ¹³ cm ⁻² to form a boron ion implantation layer 12.

Next, as shown in FIG.
Using the silicon nitride film 3b as a mask, boron ions are implanted at an acceleration energy of 30 keV and a dose of 0.5 to 2 × 10 ¹³ cm ⁻² to form a boron ion implanted layer 13.

Next, as shown in FIG.
Then, the silicon oxide film 4 and the silicon oxide film 2 are sequentially etched and removed using buffered hydrofluoric acid.

Next, as shown in FIG.
Using the a and 3b as masks, the surface of the P-type silicon substrate 1 is thermally oxidized to form a field oxide film 14 having a thickness of 1.0 μm.
The first and second element formation regions are partitioned. By the heat treatment at this time, the boron ion implanted layers 12 and 13 are activated, and the P-type well 15 and the channel stopper 16 are formed.

Next, as shown in FIG.
a, 3b and the silicon oxide film 2 are sequentially etched and removed, and the surface of the element formation region is thermally oxidized to form a gate oxide film 17, and the gate electrodes 18a, 18a,
18b, the gate electrodes 18a and 18b are respectively used as masks to selectively form the P ⁺ diffusion layer 19 in the N-type well and the N ⁺ -type diffusion layer 20 in the P-type well in a self-aligned manner. An aluminum electrode which is provided with an interlayer insulating film 21 on the surface including 18b and which is connected to each of the P ⁺ type diffusion layer 19 and the N ⁺ type diffusion layer 20 of the contact opening provided in the interlayer insulating film 21
22 is selectively provided to form a CMOS.

2 (a) and 2 (b) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a second embodiment.

As shown in FIG. 2A, a groove having a depth of 5 μm is selectively formed on the surface of the P-type silicon substrate 1, and a silicon oxide film 23 is deposited on the surface including the groove to fill the groove. Then, the silicon oxide film 23 is buried in the trench by etching back.
Next, a silicon oxide film 2 and a silicon nitride film are sequentially deposited on the entire surface, and the silicon nitride film is selectively etched to form silicon nitride films 3a and 3b serving as masks in a region corresponding to an element formation region.

Next, as shown in FIG. 2 (b), an N-type well 11, a P-type well 15, a channel stopper 16 and a field oxide film 14 are formed according to the same steps as in the first embodiment to form an element. Partition the area. Thereafter, a CMOS can be formed according to the same steps as in the first embodiment.

In this embodiment, since a groove is formed between the N-type well and the P-type well, there is an advantage that the breakdown voltage of the well can be improved, the latch-up resistance can be improved, and the degree of integration can be further improved.

〔The invention's effect〕

As described above, the present invention utilizes the selective oxidation of the polycrystalline silicon film when forming the N-type well, the P-type well, and the channel stopper, thereby requiring three photolithography steps in the past. A single photolithography process is required. Therefore, the number of steps can be significantly reduced, and the manufacturing cost can be reduced. Further, since the number of steps is reduced, there is an effect that occurrence of defects occurring in the steps can be suppressed and the yield can be improved.

In addition, since the oxide film used as a mask for ion implantation of impurities is formed by selective oxidation of polycrystalline silicon, the stress applied to the substrate is reduced and the generation of crystal defects can be suppressed as compared with the case where the silicon substrate is selectively oxidized. It has the effect of.

Further, since the N-type well, the P-type well and the channel stopper are formed in a self-aligned manner, the alignment margin required in the conventional three photolithography steps is no longer necessary, and therefore, the P-channel MOS transistor and the N-channel MOS transistor are not formed. The distance between the channel MOS transistors can be reduced,
There is an effect that the degree of integration can be improved.

Further, since the N-type well, the P-type well and the channel stopper are formed in a self-aligning manner, the respective impurity concentrations of the portions where the N-type well, the P-type well and the channel stopper are in contact are always kept the same, and Pressure resistance and CM
OS-specific variations in latch-up tolerance are reduced. Therefore, even when the distance between the P-channel MOS transistor and the N-channel MOS transistor is reduced, latch-up resistance can be ensured, and a highly reliable semiconductor device manufacturing method can be realized.

[Brief description of the drawings]

1 (a) to 1 (i) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a first embodiment of the present invention, and FIGS. 2 (a) and 2 (b) are second views of the present invention. FIG. 3A is a sectional view of a semiconductor chip shown in the order of steps for explaining the embodiment of FIG.
FIGS. 1E to 1E are cross-sectional views of a semiconductor chip shown in a process order for describing an example of a conventional method for manufacturing a semiconductor device. 1 .... P-type silicon substrate, 2 .... Silicon oxide film, 3a, 3
b ... silicon nitride film, 4 ... silicon oxide film, 5 ...
Polycrystalline silicon film, 6 silicon oxide film, 7 silicon nitride film, 3 photoresist film, 9 phosphorus ion implantation layer, 10 silicon oxide film, 11 N-type well, 1
2,13 ... boron ion implantation layer, 14 ... field oxide film, 15 ... P-type well, 16 ... channel stopper, 17
…… Gate oxide film, 18… Gate electrode, 19… P ⁺ type diffusion layer, 20 …… N ⁺ type diffusion layer, 21 …… Interlayer insulating film, 22 …… Aluminum electrode, 23 …… Silicon oxide film, 31,32,33 …… Photoresist film.

Claims (1)

(57) [Claims] 1. A first silicon nitride film is selectively formed on an oxide film provided on one main surface of a semiconductor substrate of one conductivity type to form a mask corresponding to first and second element formation regions. Forming a first silicon oxide film, a polycrystalline silicon film, a second silicon oxide film, and a second silicon nitride on the surface including the first silicon nitride film, respectively; Using the photoresist film selectively provided on the second silicon nitride film as a mask, the second silicon nitride film and the second silicon nitride film in a region including the first silicon nitride film on the first element formation region; Selectively etching and removing the silicon oxide film of step (2), and ion-implanting impurities of the opposite conductivity type using the photomask as a mask to form a well of the opposite conductivity type on the surface of the semiconductor substrate in the first element formation region. Forming process And forming a third silicon oxide film by oxidizing the polycrystalline silicon film a second silicon nitride film to remove the photoresist film as a mask,
A step of sequentially etching and removing the second silicon nitride film, the second silicon oxide film, and the polycrystalline silicon film using the third silicon oxide film as a mask, and one step using the third silicon oxide film as a mask. Forming a well of one conductivity type on the surface of the semiconductor substrate in the second element formation region by ion-implanting impurities of a conductivity type;
Forming a channel stopper by shallow ion implantation of one conductivity type impurity using the first silicon nitride film on the element formation region as a mask; and forming the third silicon oxide film and the first silicon oxide film Sequentially removing, and selectively oxidizing the surface of the semiconductor substrate using the first silicon nitride film as a mask to form a field oxide film for partitioning the first and second element formation regions. A method for manufacturing a semiconductor device.