JP3034351B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device which is intended to improve the degree of integration of an element and to flatten the patterning of an upper layer of the element.

[0002]

2. Description of the Related Art FIG. 6 is a process sectional view showing an example of a conventional method for manufacturing a MOSFET. At present, these manufacturing methods are widely applied to LDD (Lightly Doped Drain Structure) structures and the like.
3P. 392-395.

First, as shown in FIG. 6A, a field oxide film 2 is formed on a silicon single crystal semiconductor substrate (hereinafter abbreviated as a substrate) 1 by a normal selective oxidation method (LOCOS method). Active area 51 and field area 5
Separate 2.

After that, as shown in FIG. 6B, a gate oxide film 3 and a gate electrode 4 of the transistor are formed on the entire surface, and then patterned by a photolithography technique or the like.

Then, using the gate electrode 4 as a mask, for example, in the case of an N-channel transistor, an impurity such as arsenic is ion-implanted to form the source / drain formation region of the substrate 1 as shown in FIG. A high-concentration impurity diffusion layer 5 is formed on the whole in a self-aligned manner.

[0006]

However, in the above-mentioned conventional method for manufacturing a MOSFET, since the source / drain formation region exists on the substrate, it is difficult to increase the degree of integration of the transistor formation region itself. was there.

Further, in a semiconductor device in which a transistor manufactured by a conventional manufacturing method is used as a lowermost wiring layer, for example, a stacked capacitor type DRAM, an upper insulating film layer and an upper wiring layer are separated from a gate electrode. However, there is a problem that good patterning cannot be performed because a step is generated due to the height of the substrate.

The present invention solves the problems of the prior art described above in that the integration degree of the transistor formation region itself cannot be increased and that the patterning of the transistor upper layer cannot be performed well. Is provided.

[0009]

In order to solve the above-mentioned problems, the present invention provides a method of manufacturing a semiconductor device, comprising: forming a trench in a substrate;
A step of forming a gate oxide film and a gate electrode, and a step of forming a source / drain diffusion layer by introducing an impurity of a conductivity type opposite to that of a substrate into a side wall of a trench are introduced.

[0010]

According to the present invention, in the method of manufacturing a semiconductor device, the above steps are introduced, so that the gate oxide film formed on the bottom of the trench and the gate electrode are used as a mask to self-align with the inner wall of the trench. By injecting an impurity of the conductivity type opposite to that of the substrate and forming the source / drain diffusion layers in the trench, the element can be miniaturized, and a step is formed when a wiring pattern is formed on the substrate. Therefore, the problem can be eliminated.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the method for manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings. 1 (a) to 1
FIG. 2C is a sectional view of the first step of the embodiment, and FIG.
2 (a) to 2 (c) are cross-sectional views of the process at the second stage, and FIG.
3 (a) to 3 (b) are cross-sectional views of steps in the third stage.

First, as shown in FIG. 1A, a P-type silicon single crystal semiconductor substrate (hereinafter abbreviated as a substrate) 10
An oxide film 102 serving as a mask for forming a trench is formed on at least 6000.degree.

Next, by photolithography, a contact for forming the trench 103 is opened and patterned with a resist (not shown), and the oxide film 102 is etched using this as a mask.

Next, the resist is removed, the substrate 101 is etched using the patterned oxide film 102 as a mask, and a trench 103 is formed with a depth of about 10 μm or less.

Next, as shown in FIG. 1B, a gate insulating film 104 is formed on the entire trench side wall by thermal oxidation to a thickness of 200 to 200 nm.
Then, a polysilicon layer 105 is formed on the entire surface by a thickness of 1000 to 300 °, as shown in FIG.
Deposit about 0 ° by a CVD (Chemical Vapor Deposition) method.

Next, FIG. 2 (a) to FIG.
In the process steps, a photoresist is applied to the entire surface, and the photoresist is exposed and developed with an appropriate exposure.
In this case, a positive photoresist is used.

As a result, as shown in FIG. 2A, a photoresist 106 which is not fully exposed and is not dissolved is selectively formed at the bottom of the trench, and patterning with the resist is performed in a self-aligned manner without performing mask alignment. Done.

Thereafter, as shown in FIG. 2B, the polysilicon layer 105 and the gate insulating film 104 are etched using RIE (reactive ion etching) using the photoresist pattern 106 as a mask.
Transistor gate insulating film 104a, gate electrode 10
5a is formed.

Next, after removing the photoresist 106,
As shown in FIG. 2C, an impurity such as arsenic is implanted into the source / drain diffusion layer 1 by a so-called oblique ion implantation method in which ions are implanted under a certain angle to the substrate 101.
09.

Next, FIG. 3A and FIG.
Entering the process steps, first, as shown in FIG.
An insulating film 107 such as an oxide film is formed over the entire surface by a CVD method. Thereafter, as shown in FIG. 3B, only the insulating film 107 on the gate electrode 105a is selectively etched and removed by RIE.

Next, the remaining trench is replaced by a polysilicon film or a metal wiring layer 108 such as tungsten.
It is buried by the method D and is bonded to the gate electrode 105a.
At this time, the insulating film 107 used in FIG. 3A functions as an insulating film for the trench side wall source / drain diffusion layer 109.

Thereafter, although not shown, an intermediate insulating film, a metal pattern for wiring, and a protective insulating film are sequentially formed in a laminated state by a normal process technique to complete a semiconductor device.

When this embodiment is applied to a DRAM cell or the like, an example is shown in FIG. 4 because it is necessary to distinguish between a source and a drain and to separate the cell from an adjacent cell. 1A to 3B are sectional views taken along the line A-A1 shown in FIG.
FIG. 5 shows a section taken along the line -B1.

In FIG. 5, reference numeral 201 denotes a substrate (FIGS.
Reference numerals 101) and 202 in FIG. 3B denote insulating oxide films, which are formed by so-called trench isolation in which a trench is formed in a substrate and then the insulating film is buried.

It is needless to say that the present invention is not limited to the NMOSFET, but is widely applied to other semiconductor devices for miniaturization.

[0026]

As described above in detail, according to the present invention, a gate insulating film, a gate electrode, and a source / drain extension layer of a transistor are formed inside a trench formed in a substrate. This is advantageous for miniaturization, and furthermore, it is possible to self-align insulation other than the gate electrode, source / drain diffusion layer, and gate electrode portion, and to simplify the working process.

Further, in order to form an element inside the substrate,
When forming a wiring pattern on a substrate upper layer, there is no step at the stage of forming the transistor, and the wiring layer,
Flattening in forming an insulating film or the like can be achieved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a first step in a method of manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 2 is a process sectional view of a second step of the embodiment.

FIG. 3 is a process sectional view of a third step in the embodiment.

FIG. 4 is an explanatory diagram of an application example of the embodiment to a DRAM cell or the like.

FIG. 5 is a sectional view taken along line BB1 of FIG. 4;

FIG. 6 is a cross-sectional view showing a manufacturing process of a conventional MOSFET.

[Explanation of symbols]

 Reference Signs List 101 substrate 102 oxide film 103 trench 104 gate insulating film 104a gate insulating film 105 polysilicon layer 105a source / drain diffusion layer 106 photoresist 107 insulating film 108 metal wiring

Claims (1)

(57) [Claims] A step of forming a trench in the surface of the semiconductor substrate, a step of forming an insulating film on the surface of the semiconductor substrate in the trench, a step of forming a silicon film on the surface of the insulating film, and filling the trench. Applying a positive resist film on the surface of the semiconductor substrate so that a portion of the positive resist film in the trench becomes an insufficiently light-exposed region and completely exposing the positive resist film on the other semiconductor substrate surface Exposing and developing the positive resist film with an amount of light, and etching the silicon film and the insulating film using the positive resist film remaining in the insufficiently light-sensitive region in the trench as a mask to form a gate at the bottom of the trench. Forming an insulating film and a gate electrode; and implanting impurities into sidewalls of the trench to form source and drain diffusion layers. The method of manufacturing a semiconductor device according to claim and.