JP3259439B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and
The present invention relates to an OS type or MIS type semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, semiconductor devices, especially semiconductor memory devices, have been increasingly miniaturized and highly integrated. For this reason, the spacing between individual MOS (MIS) transistors and the size of contact holes have also been reduced to the submicron region. An example of a memory cell of a static RAM miniaturized as described above is disclosed in the following document (Nikkei Micro Devices, June 1991, p. 47).
(C of FIG. 7).

A conventional method of manufacturing a semiconductor device having a MOS transistor in which a sidewall spacer (hereinafter, sidewall) is formed on a silicon substrate is as follows.

In FIG. 2, a silicon oxide film layer 202 is formed on a semiconductor substrate 201 containing a first conductivity type impurity by a thermal oxidation method. C on the silicon oxide film layer 202
A polycrystalline silicon film formed by the VD method is deposited, the polycrystalline silicon film is patterned using a photoresist, and dry-etched to form a polycrystalline silicon wiring layer 203. The photoresist is removed by sulfuric acid stripping, and the polysilicon wiring layer 203 is used as a mask,
The first diffusion layer 204 is formed by injecting a second conductivity type impurity by ion implantation and thermally diffusing it. Next, an insulating film layer is formed on the entire surface of the semiconductor substrate 1 containing the first conductivity type impurity by using the CVD method, and the sidewall 205 is formed by etching using an anisotropic etching method. Next, a second diffusion layer 206 is formed by injecting an impurity of a second conductivity type at a higher concentration than the first diffusion layer 204 by ion implantation and thermally diffusing the same.

[0005]

FIG. 3 is a characteristic diagram showing the resistance of a diffusion layer when the distance between the adjacent polysilicon wiring layers 203 is reduced in order to miniaturize the device.

As can be seen from FIG. 3, when the distance between the polysilicon wiring layers 203 is reduced to 1.0 μm or less, the resistance of the second diffusion layer 206 formed between the polysilicon wiring layers 203 increases rapidly. I do.

The opening of a contact hole formed in a subsequent step is also reduced in the distance between the polysilicon wiring layer 203 and the polysilicon wiring layer 203.
Since the second diffusion layer 206 must be drawn out of the polycrystalline silicon wiring layer 203, the distance to the opening becomes longer,
Further, the resistance of the second diffusion layer 206 increases.

As described above, a high resistance is applied to the transistor in the memory cell portion, so that the operation speed of the transistor decreases, and the operation of the memory cell portion becomes unstable because the capability of the transistor decreases. Become.

In order to solve the above problem, as a means for forming a diffusion layer immediately below a sidewall formed between adjacent polysilicon wiring layers, a photoresist is used immediately after the formation of the polysilicon wiring layer. There is a method of patterning, introducing impurities only in the polycrystalline silicon wiring layer, forming sidewalls, patterning again using photoresist, and introducing impurities into other portions. Must be performed twice, and the number of process steps increases, which is not reasonable.

Therefore, in the present invention, the adjacently formed M
By reducing the resistance of a diffusion layer region common to OS-type transistors, a reduction in transistor performance is suppressed, the operation of a memory cell unit is stabilized, and a rational manufacturing method is provided without increasing the number of process steps. It is in.

[0011]

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a gate electrode having a multi-layered structure, comprising at least one or more layers. Forming a lower portion of the gate electrode; forming an upper portion of at least one layer of the gate electrode on the lower portion of the gate electrode; and forming first and second portions having different widths on side surfaces of the electrode. 2) a step of forming a sidewall spacer and a step of forming an impurity region in the semiconductor substrate after the formation of the sidewall spacer. Further, the upper part of the gate electrode is formed on the lower part of the gate electrode and on the semiconductor substrate.

[0012]

[0013]

[0014]

[0015]

Next, one embodiment of the present invention will be described in detail for each manufacturing process with reference to element sectional views.

FIG. 1 (c) shows the M formed by applying the present invention.
FIG. 14 is a sectional view of the final step of the OS-type transistor. In addition, regarding the symbol in the figure, 101 is a P-type silicon substrate, 102 is a silicon oxide film layer, 103 is a lower gate electrode, 104
Is an upper layer gate electrode, 105 is a source and drain region made of a low concentration N-type impurity, 106 is a first sidewall, 107 is a second sidewall, 108 is a drain region made of a high concentration N-type impurity, and 109 is a high concentration N-type impurity. This is a source region made of N-type impurities.

First, a silicon oxide film layer 102 of about 20 nm is formed on a P-type semiconductor substrate 101 having a specific resistance of 10 to 100 Ω in an oxidizing atmosphere at 1000 ° C. for 20 minutes.
Next, polycrystalline silicon is deposited to a thickness of 50 to 100 nm using a CVD method.
After depositing the photoresist, applying a photoresist and patterning the photoresist using a projection exposure method, the lower gate electrode 103 is formed by dry etching.
Deposit about 300 nm. After applying a photoresist and patterning the photoresist using a projection exposure method, the upper gate electrode 104 is formed by dry etching. This state is shown in FIG. Hereinafter, the lower gate electrode 103 and the upper gate electrode 104 are collectively referred to as a gate electrode.

Next, for example, phosphorus is implanted at a dose of about 1 × 10 ¹¹ to 1 × 10 ¹⁴ / cm ² at an energy of 20 to 40 KeV using the gate electrode as a mask by ion implantation, thereby forming a low-concentration N-type impurity. Source and drain region 1
05 is formed.

Thereafter, a first side wall 106 and a second side wall 107 are formed on the side surfaces of the gate electrode by depositing a silicon oxide film of about 100 nm to 1000 nm by CVD and performing anisotropic etching. Here, the width of the sidewall is smaller than that of the second sidewall 107 due to a difference in thickness between the gate electrode 103 of the lower layer and the gate electrode 104 of the upper layer. . This state is shown in FIG.

Finally, implantation is performed under the condition that the gate electrode and the second side wall 107 are used as a mask and the first side wall 106 is transmitted. For example, for arsenic, 1 × 10 ¹⁴ to 1 × 1 at an energy of 40 to 100 KeV
Implantation of about 0 ¹⁶ / cm ² is desirable. By the above-described implantation, a source region 107 made of a high-concentration N-type impurity and a drain region 108 made of a high-concentration N-type impurity are formed.
This state is the final step sectional view of the present invention in FIG. 1 (c).

In an embodiment of the present invention, the upper gate electrode 104 is formed on the lower gate electrode and the P gate electrode.
In this method, the lower gate electrode 10 is formed on the silicon substrate 101.
In the step of dry-etching 3, the lower gate electrode 10 is formed on the damaged gate oxide film 102.
4, the gate breakdown voltage of the MOS transistor deteriorates.

Therefore, if the end of the upper gate electrode 104 on the source region 107 side due to the high-concentration N-type impurity is made coincident with the end of the lower gate electrode 103, the MOS transistor as described above is formed. The gate breakdown voltage does not deteriorate. Further, since the second sidewall is formed on the side surface of the lower gate electrode 103 and the side surface of the upper gate electrode 104, the degree of freedom of the process at the time of implanting the diffusion layer is increased as compared with that described in the embodiment of the present invention. I do.

In the embodiment of the present invention, the case where the width of the sidewall on the side surface of the lower gate electrode 103 is formed smaller than the width of the sidewall on the side surface of the upper gate electrode 104 will be described. However, depending on conditions such as the ratio of the difference in film thickness between the lower gate electrode 103 and the upper gate electrode 104 and the overetching time in anisotropic etching, the side wall on the side surface of the lower gate electrode 103 may be used. Can also be completely eliminated.

In the present invention, the gate electrode of the MOS transistor has a two-layer structure of a polycrystalline silicon film. However, the gate electrode of the MOS transistor is not limited to two layers, but may be any number of layers. The layer constituting the gate electrode may be any semiconductor layer as long as it is not an insulating film layer.

In the present invention, phosphorus is used for the source and drain regions with low concentration of N-type impurities, and arsenic is used for source and drain regions with high concentration of N-type impurities. However, the impurities are not limited to phosphorus and arsenic. Any impurities may be combined as long as they are impurities. Further, although the present invention describes an N-channel MOS transistor using a P-type semiconductor substrate, a P-channel MOS transistor using an N-type semiconductor substrate may be used.

[0026]

According to the method of manufacturing a semiconductor device of the present invention as described above, the impurity region disposed on the side of the narrow side wall spacer is also formed immediately below the sidewall. Resistance can be reduced.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing an embodiment of the present invention.

FIG. 2 is a longitudinal sectional view showing a conventional semiconductor device.

FIG. 3 is a characteristic diagram showing diffusion layer resistance in a conventional semiconductor device.

[Explanation of symbols]

101: P-type silicon substrate 102, 202 ... Silicon oxide film layer 103: Lower gate electrode 104, 203 ... Upper gate electrode 105, 204 ... Source by low concentration N-type impurity , Drain region 106 ... first sidewall 107 ... second sidewall 108 ... source region 109 by high concentration N-type impurity 109 ... drain region 201 by high concentration N-type impurity Silicon substrate having one conductivity type impurity 203: polycrystalline silicon wiring layer 204: first diffusion layer 205: side wall 206: second diffusion layer

Claims (2)

(57) [Claims] 1. A method of manufacturing a semiconductor device having a gate electrode having a multi-layered structure, comprising: forming at least one or more layers under the gate electrode having the multi-layered structure; Forming an upper portion of at least one layer of the gate electrode on the lower portion, forming first and second sidewall spacers having different widths on side surfaces of the electrode, Forming a impurity region in the semiconductor substrate after the spacer is formed. 2. The method of manufacturing a semiconductor device according to claim 1, wherein said upper part of said gate electrode is formed on said lower part of said gate electrode and on said semiconductor substrate. Manufacturing method.