JP2906460B2 - Method of manufacturing complementary MOS semiconductor device - Google Patents

Description

The present invention relates to a method of manufacturing a complementary MOS semiconductor device,
In particular, the present invention relates to a method for manufacturing a complementary MOS semiconductor device in which an n-channel MOS transistor (hereinafter, referred to as nMOS) has a so-called LDD (Lightly Doped Drain) structure.

[Prior Art] This type of conventional semiconductor device has been manufactured through various steps shown in FIG. That is, a p-type well layer 2 is formed in an n-type semiconductor substrate 1, and a field oxide film 3 for separating elements is formed on the substrate surface.

Gate electrodes 5a and 5b are formed on an n-type semiconductor substrate 1 with a gate oxide film 4 interposed therebetween.

A p-channel MOS transistor (hereinafter, referred to as pMOS) region is covered with a resist 15, and phosphorus is ion-implanted to form a first source / drain region 9a (FIG. 4A).

The resist 15 is removed, and an oxide film is formed and anisotropic RIE (R
The spacers 6a, 6b are formed on the side walls of the gate electrodes 5a, 5b by eactive ion etching).

The pMOS region is covered with a resist 16 and arsenic is ion-implanted to form a second source / drain region 9b [FIG. 4 (b)].

After removing the resist 16, the nMOS region is covered with the resist 17, and boron is ion-implanted to form the source / drain region 8 (FIG. 4C).

Thereafter, the resist 17 is removed, and a MOS semiconductor device is manufactured through a commonly used process.

[Problem to be Solved by the Invention] In the conventional complementary MOS semiconductor device described above, the second source / drain region 9b of the nMOS and the source / drain region 8 of the pMOS have the same thickness of the spacers 6a and 6b, respectively. Are formed by implanting arsenic or boron using the gate electrodes 5a and 5b having the mask as masks. However, between arsenic and boron, the diffusion coefficient of boron is one order of magnitude greater than that of arsenic. As a result, boron diffuses more in the lateral direction, so that the effective channel length is shortened on the pMOS side, and the short channel effect becomes remarkable. Therefore, the conventional complementary MO
In the S semiconductor device, it is difficult to increase the density due to the restriction on miniaturization on the pMOS side. Further, in the conventional semiconductor device, the overlapping portion of the source / drain region and the gate electrode becomes large on the pMOS side, so that the parasitic capacitance increases and the operation speed of the transistor decreases. Further, in the conventional manufacturing method, many man-hours are required, for example, three photolithography steps are required after the gate electrode is formed and the manufacturing steps of the MOS transistors of both conductivity types are completed.

[Means for Solving the Problems] A method of manufacturing a complementary MOS semiconductor device according to the present invention comprises the steps of: (a) forming a first region on a semiconductor substrate, which is an n-channel MOS transistor formation region; Forming first and second gate electrodes on the two regions with a gate insulating film interposed therebetween; and (b) depositing a first insulating film on the entire surface and forming a first insulating film on the second region.
(C) introducing a low concentration of n-type impurity into the first region using the first gate electrode as a mask; (D) depositing a second insulating film on both sides and etching back the same to form a first n-type diffusion layer on the side surfaces of the first gate electrode from the second insulating film. And a first insulating film that covers the second region on the side surface of the second gate electrode, and remains on the side surface of the second gate electrode during the etch back. Forming a second spacer composed of a second insulating film; and (e) introducing an n-type impurity at a high concentration using the first gate electrode, the first spacer, and the first insulating film as a mask. Forming a second n-type diffusion layer in the first region; and (f) forming a second mask material in the first region. After coating with the second
Forming a p-type diffusion layer in the second region by introducing a p-type impurity using the mask material, the second gate electrode and the second spacer as a mask.

Reference Example Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view showing a first reference example of the present invention.
As shown in the figure, a p-type well layer 2 serving as an nMOS formation region is formed in a surface region of an n-type semiconductor substrate 1, and a field oxide film 3 for element isolation is formed on the substrate 1. . Gate electrodes 5a and 5b are further formed on the semiconductor substrate 1 and insulated by a gate oxide film 4.
A first spacer 6 is provided on the side wall of the gate electrode 5a in the OS region.
A second spacer 7 is formed on the side wall of the gate electrode 5b in the pMOS region. As shown in FIG. 1, the thickness of the second spacer 7 is formed to be thicker than that of the first spacer 6. NM in the surface area of the semiconductor substrate
First n-type diffusion layer 9a forming LDD structure in OS region
And the second n-type diffusion layer 9b, and in the pMOS region,
The mold diffusion layers 8 are respectively formed. With this structure, in the pMOS, the spread of the p-type diffusion layer 8 in the channel direction is suppressed, and the occurrence of the short channel effect is also suppressed.

FIGS. 2A to 2E are cross-sectional views of a semiconductor device for explaining a manufacturing process according to a second reference example of the present invention.

FIG. 2 (a) shows a commonly used complementary MO.
According to the method for manufacturing an S semiconductor device, a p-type well layer 2 which is an nMOS formation region is formed in a surface region of an n-type semiconductor substrate 1, and a field oxide film 3 for element isolation is formed on the semiconductor substrate 1.
And the gate electrodes 5a and 5b insulated by the gate oxide film 4, and then the pMOS region is masked with a resist 11 by a normal photoresist process, and the nMOS region has an LDD structure of n ⁻
FIG. 5 is a diagram showing a state in which a first n-type diffusion layer 9a serving as a diffusion layer is formed.

Subsequently, the resist 11 is removed, and the entire surface of the semiconductor substrate is subjected to CVD.
A first oxide film 21 is deposited to a thickness of 2000 ° by the method [FIG. 2 (b)].

Next, the pMOS region is masked with a resist 12 to remove anisotropic RI.
Etchback is performed by E to leave the first oxide film 21 on the side wall of the gate electrode 5a of the nMOS, thereby forming a first spacer 6 serving as a mask for ion implantation. Next, arsenic is ion-implanted using the gate electrode 5a, the first spacer 6, the field oxide film 3 and the resist 12 as a mask to form a second n-type diffusion layer 9b.
[FIG. 2 (c)].

Subsequently, the resist 12 is removed, and the entire surface of the semiconductor substrate is subjected to CVD.
A second oxide film 22 is deposited to a thickness of 1000 ° by the method [FIG. 2 (d)].

Next, the nMOS region is masked with a resist 13 so that
Etchback is performed by RIE to leave the first oxide film 21 and the second oxide film 22 on the side walls of the gate electrode 5b of the pMOS, thereby forming the second spacer 7 serving as a mask for ion implantation.
Next, boron is ion-implanted using the gate electrode 5b, the second spacer 7, the field oxide film 3 and the resist 13 as a mask to form a p-type diffusion layer 8 (FIG. 2E).

Thereafter, the resist 13 is peeled off to obtain the semiconductor device of the present reference example. In the complementary MOS semiconductor device formed in this manner, the thickness of the oxide pus spacer formed on the side wall of the gate electrode is 2,000 mm in the nMOS region, and is 2,000 in the pMOS region.
3000Å.

3 (a) to 3 (d) are cross-sectional views of a semiconductor device for explaining a manufacturing process according to one embodiment of the present invention.

FIG. 3A shows that after forming gate electrodes 5a and 5b through the same manufacturing process as that of the second reference example, a third oxide film 23 having a thickness of 2000 .ANG. It is a figure showing the state where it accumulated.

Subsequently, the pMOS region is masked with the resist 14, and the third oxide film 23 in the nMOS region is removed by wet etching using buffered hydrofluoric acid. Next, the gate electrode of the nMOS
5a, the field oxide film 3, and the resist 14 are used as a mask to ion-implant phosphorus to form a first n ^-type diffusion layer having an LDD structure.
A mold diffusion layer 9a is formed [FIG. 3 (b)].

Next, the resist 14 is peeled off, and a fourth
The oxide film 24 is deposited to a thickness of 2000 ° by the CVD method (FIG. 3C).

Then, etch back by anisotropic RIE,
An oxide film of approximately 2000 mm is etched. as a result,
In the nMOS region, the first spacer 6 is formed with the fourth oxide film 24 remaining only on the side wall of the nMOS gate electrode 5a.
In the region, the second spacer 7 is formed by the third oxide film 23 and the fourth oxide film 24 remaining on the side wall of the pMOS gate electrode 5b.

Next, a field oxide film 3 and an nM
OS gate electrode 5a, first spacer 6, and third oxide film
Arsenic is ion-implanted using the mask 23 to form a second n-type diffusion layer 9b. Next, the nMOS region is masked with a photoresist (not shown), and the third region is masked using the field oxide film 3, the gate electrode 5b of the pMOS, and the second spacer 7 as a mask.
Then, boron ions are implanted through the oxide film 23 to form a p-type diffusion layer 8 (FIG. 3D). In this case, by properly selecting the energy of boron ion implantation, boron penetrates the third oxide film 23 and the pMOS gate electrode 5b.
And it can be made to be blocked by the second spacer 7.

In the manufacturing method according to this embodiment, arsenic can be implanted for forming the second n-type diffusion layer 9b using the third oxide film 23 as a mask, so that the ordinary photoresist process can be omitted once. Can be.

[Effects of the Invention] As described above, according to the present invention, the spacer formed on the side wall of the pMOS gate electrode is formed to be thicker than the spacer formed on the side wall of the nMOS gate electrode. For example, the difference in the diffusion coefficient between boron for forming the source / drain of pMOS and arsenic for forming the source / drain of nMOS is offset, and the reduction in the effective channel length due to lateral diffusion is reduced by pMOS. And nMOS. For this reason, the limit of miniaturization limited by pMOS is released, and miniaturization equivalent to nMOS can be performed.

According to the present invention, furthermore, the overlap between the gate electrode and the source / drain region in the pMOS is reduced, so that the parasitic capacitance is reduced and the operation of the transistor is sped up. Further, according to the present invention, after the formation of the gate electrode, two photolithography steps and two film forming steps are performed to form the two conductive types.
Since a MOS transistor can be formed, the manufacturing process is simplified, and a complementary MOS semiconductor device can be provided at low cost.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a first reference example of the present invention. FIGS. 2 (a) to 2 (e) are cross-sectional views of a semiconductor device for explaining manufacturing steps of the second reference example of the present invention. Fig. 3 (a)
4A to 4D are cross-sectional views of a semiconductor device for explaining a manufacturing process according to an embodiment of the present invention, and FIGS. 4A to 4C are cross-sectional views of a semiconductor device for explaining a conventional manufacturing process. It is sectional drawing. DESCRIPTION OF SYMBOLS 1 ... n-type semiconductor substrate, 2 ... p-type well layer, 31 ... field oxide film, 4 ... gate oxide film, 5a, 5b ... gate electrode, 6 ... 1st spacer, 6a, 6b ... …Spacer,
7 ... second spacer, 8 ... p-type diffusion layer, 9a ... first
N-type diffusion layer, 9b... Second n-type diffusion layer, 11-17... Resist, 21-24... First-fourth oxide film.

Claims (1)

(57) [Claims] (A) On a first region of a semiconductor substrate which is an n-channel MOS transistor forming region and on a p-channel MOS transistor
Forming a first and a second gate electrode on a second region, which is a transistor formation region, with a gate insulating film interposed therebetween; and (b) depositing a first insulating film on the entire surface and forming a second insulating film on the second region. First
(C) introducing a low concentration of n-type impurity into the first region using the first gate electrode as a mask; (D) depositing a second insulating film over the entire surface and etching it back to form a second insulating film on the side surface of the first gate electrode. A first spacer is formed, a first insulating film covering the second region on a side surface of the second gate electrode, and a first insulating film remaining on the side surface of the second gate electrode during the etch back. (E) forming a second spacer composed of the first insulating film and the first gate electrode, the first spacer and the first insulating film as masks, and introducing a high concentration of n-type impurities. Forming a second n-type diffusion layer in one region; and (f) forming a first inclined region with a second mask material. After coating with the second
Forming a p-type diffusion layer in the second region by introducing a p-type impurity using the mask material, the second gate electrode, and the second spacer as a mask. Manufacturing method.