JPH0584064B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a complementary semiconductor device, and in particular to a method for manufacturing a complementary semiconductor device in which the process for forming source and drain regions of n-channel and p-channel transistors is improved. It concerns the method.

[Technical background of the invention]

As is well known, complementary MOS semiconductor devices (hereinafter referred to as
CMOS (abbreviated as CMOS) is a device in which an n-channel transistor and a p-channel transistor are formed on the same substrate. Recently, miniaturization technology for CMOS has been rapidly established, and along with this, higher performance and higher integration have been achieved. Specifically, CMOS with a channel length of 1 μm or less is being developed. In such fine CMOS, the electric field between the source and drain regions (especially the electric field between the source and drain regions in n-channel transistors) becomes extremely large, and problems arise due to electrons and holes generated in this high electric field. Occur. For example, there is a fluctuation (increase) in the threshold voltage due to electrons injected into the gate oxide film, and an abnormal increase in substrate current due to holes injected into the semiconductor substrate.

For this reason, conventional methods for manufacturing CMOS having a structure that alleviates the high electric field between the source and drain regions have been proposed. This will be explained below with reference to FIGS. 2a-g.

First, an n-type silicon substrate 1 with crystal orientation (100)
A p-type semiconductor layer (p-well) 2 is selectively formed therein. Subsequently, after forming a field oxide film 3 as an element isolation region on the substrate 1 and the p-well 2, an oxide film is formed on the island-shaped element region of the substrate 1 and the p-well 2 separated by the field oxide film 3. form. Subsequently, a phosphorus-doped polycrystalline silicon film, for example, is deposited on the entire surface and patterned to form gate electrodes 4 and 5 on the oxide film in each element region.
are formed, respectively, and the oxide films are selectively etched away using the gate electrodes 4 and 5 as masks to form gate oxide films 6 and 7 (as shown in FIG. 1A).

Next, after forming a resist pattern 8 covering the element region side of the substrate 1 by photolithography, using the resist pattern 8, gate electrode 4, and field oxide film 3 as masks, an n-type impurity, such as phosphorus, is applied at an accelerating voltage of 20 keV and at a dose. A low concentration phosphorus ion implantation layer 9 ₁ is formed by implanting ions at an amount of 1×10 ¹³ cm ⁻² ,
9 ₂ (as shown in Figure b). Subsequently, the resist pattern 8 is removed, and a resist pattern 10 covering the n-well 2 side is again formed by photolithography.
After forming the resist pattern 10, the gate electrode 5, and the field oxide film 3 as masks, p
Boron ion-implanted layers 11 ₁ and 11 ₂ are formed by ion-implanting a type impurity, for example, boron, at an acceleration voltage of 40 keV and a dose of 1×10 ¹⁵ cm ^-2 (as shown in FIG. 3C).

Next, after removing the resist pattern 10,
After a CVD-SiO ₂ film 12 having a thickness of, for example, 4000 Å is deposited on the entire surface, heat treatment is performed in a nitrogen atmosphere at, for example, 900° C. for 30 minutes. As a result, the phosphorus ion implantation layers 9 ₁ , 9 ₂ are activated to form low concentration n ^- type diffusion layers 13 ₁ , 13 ₂ as shown in _FIG . 11 ₂ is activated to form p ⁺ type source and drain regions 14 and 15. Subsequently, the CVD-SiO ₂ film 12 is removed by etching to the extent of the film thickness of the CVD-SiO ₂ film 12 using a reactive ion etching method (RIE method), and the side surfaces of the gate between the gate electrode 4 and the gate oxide film 6 are removed. , a wall body 16 is formed by leaving the SiO ₂ film 12 on the side surfaces of the gate electrode 5 and the gate oxide film 7, respectively (as shown in the figure e).

Next, a resist pattern (not shown) covering the element region side of the substrate 1 is again formed by photolithography, and then the resist pattern, the gate electrode 4,
Using the wall body 16 and the field oxide film 3 as a mask, an n-type impurity such as arsenic is ion-implanted at an acceleration voltage of 40 keV and a dose of 3×10 ¹⁵ cm ⁻² . Thereafter, the resist pattern is removed, and heat treatment is performed in a nitrogen atmosphere at 900° C. to activate the arsenic ion implantation layer and form high concentration n ⁺ type diffusion layers 17 ₁ and 17 ₂ . As a result, a source region 18 consisting of the n ^- type diffusion layer 13 ₁ and the n ⁺ type diffusion layer 17 ₁ is formed, and a drain region 19 consisting of the n ^- type diffusion layer 13 ₂ and the n ⁺ type diffusion layer 17 ₂ is formed. is formed.
Next, an SiO ₂ film 20 is deposited on the entire surface, a contact hole 21 is opened, and an Al layer is deposited on the SiO ₂ film 20.
A film is deposited and patterned to form an Al wiring 22 connected to the n-type source region 18 through a contact hole 21, the drain region 15,
19 and the Al wiring 23 commonly connected through the contact holes 21, 21, and the p ⁺ type source region 14 connected through the contact hole.
CMOS is manufactured by forming Al interconnections 24 (as shown in g in the same figure).

According to the conventional method described above, the n-channel transistor has a low concentration n-type diffusion layer 13 ₁ located near the gate electrode 4 and a high concentration n ⁺ type diffusion layer 17 ₁ located away from the gate electrode 4. A source region 18 consisting of a low concentration n ^- type diffusion layer 13 ₂ located near the gate electrode 4 and a drain region 19 consisting of a high concentration n ⁺ type diffusion layer 17 ₂ located away from the gate electrode 4 are formed. Therefore, the so-called
It has an LDD structure and can suppress the generation of a high electric field between the source and drain regions described above.

[Problems with background technology]

However, the conventional method described above has various problems listed below.

(a) In the step of FIG. 2 d, CVD-SiO ₂
When the film 12 is etched to the same thickness using the RIE method to form the wall bodies 16 on the side surfaces of the gate electrodes 4 and 5, the field oxide film 3 is overetched and thinned. As a result, as shown in FIG. 3, the width of the field oxide film 3 separating the CMOS is reduced, and the ⁿ
−n ⁺ The distance between layers 25 is the length L before RIE method processing
The length Le decreases from 0 to 1, resulting in a decrease in pressure resistance.

(b) Since the wall 16 is formed by the RIE method,
At the time of formation, the surfaces of the silicon substrate 1 and the p-well 2 where the source and drain regions are formed are damaged by ions, significantly deteriorating the device characteristics.

(c) When forming the gate oxide films 6 and 7 by selectively etching the oxide films using the gate electrodes 4 and 5 as masks, undercuts occur in the gate oxide films, and the withstand voltage between the gate electrodes and the source and drain regions increases. decreases, causing problems in terms of reliability.

(d) In the above method, in order to avoid offset of the source and drain regions 14 and 15 of the p-channel transistor, the source and drain regions 14 and 15 of the p-channel transistor are
4 and 15 on the side surfaces of the gate electrodes 4 and 5.
is formed before it is formed. For this reason, p ⁺
Even after forming the type source and drain regions 14 and 15, the source and drain regions are re-diffused and the junction depth is reduced because they undergo high-temperature heat treatment to form the n ⁺ type diffusion layers 17 ₁ and 17 ₂ . becomes deeper, and the short channel effect of the p-channel transistor becomes significant, leading to fluctuations in threshold voltage and the like. Note that in order to prevent re-diffusion of the p ⁺ type source and drain regions 14 and 15,
After removing the wall 16 made of CVD- _SiO2 ,
A p + type source is created by ion-implanting p ^- type impurities,
A method of forming a drain region is also considered. However, in this method, when the CVD-SiO ₂ wall 16 is removed, the field oxide film 3 is etched and the film is thinned, causing the same problem as in (a) above.

[Purpose of the invention]

In the present invention, the n-channel transistor is an LDD.
In addition to eliminating the breakdown voltage drop between the n ⁺ -n ⁺ type high-concentration impurity layer, the breakdown voltage drop between the gate electrode and the source and drain regions, and the damage caused by ions on the semiconductor substrate surface, the threshold voltage of the p-channel transistor is improved. It is an object of the present invention to provide a method for manufacturing a high-performance, highly reliable complementary semiconductor device that prevents fluctuations or decreases in .

[Summary of the invention]

The present invention includes a step of selectively forming a semiconductor layer of a conductivity type opposite to that of the substrate on a semiconductor substrate of one conductivity type, a step of forming an element isolation region between the semiconductor substrate and the semiconductor layer, and a step of forming an element isolation region between the semiconductor substrate and the semiconductor layer. a step of forming an insulating film on the surfaces of the island-shaped element regions of the semiconductor substrate and the semiconductor layer separated by an isolation region; and a step of selectively forming gate electrodes on the insulating films on the surfaces of each of the element regions. a step of doping impurities of a first conductivity type into each of the device regions using each of the gate electrodes and the device isolation region as a mask; a step of sequentially depositing an oxidizable film and a coating on the entire surface; a step of selectively leaving an impurity of a first conductivity type on a side surface of each gate electrode; and a step of selectively doping an impurity of a first conductivity type into an element region of a conductivity type opposite to that of the impurity using the remaining film, the gate electrode, and the element isolation region as a mask. , a step of removing the remaining film, a step of converting the oxidizable film into an oxide film, and adding an impurity of a second conductivity type to an element region of an opposite conductivity type to that of the impurity using at least the gate electrode and the element isolation region as a mask. The present invention is characterized by comprising a step of selectively doping. According to the method of the present invention, as described above, the n-channel transistor has an LDD structure, and there is also a reduction in breakdown voltage between the n ⁺ −n ⁺ type high concentration impurity layer, a reduction in breakdown voltage between the gate electrode and the source and drain regions, and a reduction in the breakdown voltage between the gate electrode and the source and drain regions. It is possible to obtain a high-performance, highly reliable complementary semiconductor device that eliminates damage caused by ions on the substrate surface and also prevents fluctuations or decreases in the threshold voltage of the p-channel transistor.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described in detail with reference to Nos. 1a to 1h.

First, crystal orientation (100) non-n type silicon substrate 1
After a p-well 102 was selectively formed on the substrate 101 and the p-1 well 102 by thermal diffusion or the like, a field oxide film 103 as an element isolation region was formed on the substrate 101 and the p-1 well 102 by a selective oxidation method or the like. Subsequently, after forming an oxide film 104 on the island-shaped device region of the substrate 101 and the p-well 102 separated by the field oxide film 103, a phosphorus-doped polycrystalline silicon film 105, for example, is deposited on the entire surface (see FIG. a).

Next, after patterning the polycrystalline silicon film 105 to form gate electrodes 106 and 107 on the oxide film 104 in each element region, the oxide film 104 is selectively patterned using the gate electrodes 106 and 107 as a mask. Gate oxide films 108 and 109 were formed by etching and removing. Next, each gate electrode 106, 107 and the field oxide film 1
03 as a mask, an n-type impurity such as phosphorus is ion-implanted under conditions of an acceleration voltage of 20 keV and a dose of 1×10 ¹³ cm ^-2 to form a low-concentration phosphorus ion-implanted layer 110 ₁ ,
110 ₂ , 110 ₃ , 110 ₄ were formed (see figure b
(Illustrated). Subsequently, a polycrystalline silicon film 111 with a thickness of, for example, 300 Å is formed on the entire surface, and a polycrystalline silicon film 111 with a thickness of, eg, 4000 Å is formed on the entire surface.
After sequentially depositing CVD-SiO ₂ films 112, for example
Treat for 30 minutes in a nitrogen atmosphere at 900°C. As a result, the phosphorus ion implantation layers 110 ₁ to 110 ₄ were activated to form low concentration n ^- type diffusion layers 113 ₁ to 113 ₄ as shown in FIG. After that, the CVD-SiO ₂ film 112 is etched by a reactive ion etching method ( _RIE method).
Gate electrode 1 is removed by etching to a thickness of about 12.
06 and the side surfaces of the gate oxide film 108 and the side surfaces of the gate electrode 107 and the gate oxide film 109, respectively.
A wall 114 was formed by leaving the SiO ₂ film (as shown in d in the figure).

Next, after forming a resist pattern (not shown) covering the element region side of the substrate 101 by photolithography, the resist pattern covers the p-well 102.
Using the side gate electrode 106, wall 114 and field oxide film 103 as masks, an n-type impurity, for example arsenic, is applied at an acceleration voltage of 40 keV and a dose of 3×10 ¹⁵ cm ^-2
Ion implantation was performed under the following conditions. Thereafter, the resist pattern was removed, and heat treatment was performed in a nitrogen atmosphere at 900° C. to activate the arsenic ion implantation layer and form high concentration n ⁺ -type diffusion layers 115 ₁ and 115 ₂ . As a result, as shown in the figure e, the n ^- type diffusion layer 113 ₁
and a source region 11 consisting of an n ⁺ type diffusion layer 115 ₁
6 is formed, and the n ^- type diffusion layer 113 ₂
and a drain region 1 consisting of an n ⁺ type diffusion layer 115 ₂
17 were formed.

Next, as shown in FIG. 5F, after removing the wall 114, thermal oxidation treatment was performed to convert the polycrystalline silicon film 111 into an oxide film 118. Continuing,
After forming a resist pattern (not shown) covering the p-well 102 side by photolithography, the resist pattern, the gate electrode 107 and the field oxide film 103 are masked, and a p-type impurity, for example, boron, is applied at an accelerating voltage of 40 keV. The n ^- type diffused layers 113 ₃ , 11 of the substrate 101 at a dose of 1×10 ¹⁵ cm ⁻²
Ion implantation was performed on _3-4 . Thereafter, the resist pattern is removed, heat treatment is performed at, for example, 900° C. to activate the boron ion implantation layer, and the p ⁺ type source and drain regions 119 and 12 are formed in the element region of the substrate 101.
0 was formed (as shown in g in the same figure).

Next, a SiO ₂ film 121 is deposited on the entire surface, a contact hole 122 is opened, and the SiO ₂ film 121 is
An Al film is deposited on top and patterned to form the n-type source region 116 and contact hole 1.
Al wiring 123 connected through 22, the drain regions 117 and 120 and the contact hole 12
Al wiring 1 commonly connected through 2,122
24 and the Al wiring 12 connected to the p ⁺ type source region 119 through the contact hole 122
A CMOS is manufactured by forming 5, respectively (shown in h of the same figure).

Therefore, according to the present invention, the CVD-SiO ₂ film 11
2 by RIE method to form the gate electrode 10.
When forming the wall body 114 by leaving CVD-SiO ₂ on the side surfaces of 6 and 107, a polycrystalline silicon film 111 is formed under the CVD-SiO ₂ film 112. As a result, since the polycrystalline silicon film 111 acts as a stopper, it is possible to prevent the field oxide film 103 from thinning, and also to prevent the surfaces of the substrate 101 and p-well 102 from being damaged by ions in the RIE method, resulting in high reliability. You can get the same CMOS.

Furthermore, undercuts in the gate oxide films 108 and 109 that occur when etching the oxide film 104 using the gate electrodes 106 and 107 as masks are caused by the oxide film 118 converted by thermally oxidizing the polycrystalline silicon film 111. Buried. As a result, gate electrodes 106 and 107 and source and drain regions 1
16, 119, 117, and 120 can be prevented from decreasing.

Furthermore, as shown in FIGS. 1e and 1f, when the wall 114 is removed, the field oxide film 103 is covered with the polycrystalline silicon film 111, so that the field oxide film 103 can be prevented from being removed. As a result, as shown in FIG. 1g, after the wall 114 is removed, that is, after high-temperature heat treatment for forming the source and drain regions 116 and 117 of the n-channel transistor, the p ⁺ Type source and drain region 11
9,120 can be formed. Therefore, a p ⁺ type source,
Rediffusion of the drain regions 119 and 120 can be eliminated to prevent fluctuations in threshold voltage due to deepening of the junction depth, and a high-performance CMOS can be obtained.

In the above embodiment, a polycrystalline silicon film is used as the oxidizable film, but an amorphous silicon film or a metal silicon film may be used instead.

In the above embodiment, a CVD-SiO ₂ film was used as the coating, but a phosphosilicate glass film (PSG film) or a nitride film may be used instead.

In the above embodiments, the high concentration p-type diffusion layer was formed after converting the polycrystalline silicon film into an oxide film, but the high concentration p-type diffusion layer may be formed before converting the polycrystalline silicon film into an oxide film.

〔Effect of the invention〕

As described in detail above, according to the present invention, the n-channel transistor has an LDD structure, and the n ⁺ −
This eliminates the reduction in breakdown voltage between the n ⁺ type high concentration impurity layer, the reduction in breakdown voltage between the gate electrode and the source and drain regions, and the damage caused by ions on the semiconductor substrate surface.
It is possible to provide a method for manufacturing a high-performance, highly reliable complementary semiconductor device in which fluctuation or reduction in the threshold voltage of a channel transistor is prevented.

[Brief explanation of the drawing]

Figures 1a to 1h show examples of the present invention.
Cross-sectional diagram showing the manufacturing process of CMOS, Figure 2 a-g
3 is a cross-sectional view showing the conventional CMOS manufacturing process.
The figure is a cross-sectional view for explaining the problems of CMOS obtained by the conventional method. 101...n-type silicon substrate, 102...p-
Well, 103... Field oxide film (element isolation region), 106, 107... Gate electrode, 108,
109... Gate oxide film, 111... Polycrystalline silicon film (oxidizable film), 112... CVD-SiO ₂ film (film), 113 ₁ to 113 ₄ ... n ^- type diffusion layer, 11
4... Wall body, 115 ₁ , 115 ₂ ... n ⁺ type diffusion layer,
116... Source region, 117... Drain region, 118... Oxide film, 119... P ⁺ type source region, 120... P ⁺ type drain region, 121...
...SiO ₂ film, 123-125...Al wiring.

Claims (1)

[Claims] 1. A step of selectively forming a semiconductor layer of a conductivity type opposite to that of the substrate on a semiconductor substrate of one conductivity type, and a step of forming an element isolation region between the semiconductor substrate and the semiconductor layer. , forming an insulating film on the surfaces of the island-shaped element regions of the semiconductor substrate and the semiconductor layer separated by the element isolation region, and selectively forming a gate electrode on the insulating film on the surface of each element region. a step of doping impurities of a first conductivity type into each of the element regions using each of the gate electrodes and the element isolation region as a mask; a step of sequentially depositing an oxidizable film and a coating on the entire surface; A step of selectively leaving a film on the side surface of each of the gate electrodes, and selectively doping an impurity of a first conductivity type into a device region of a conductivity type opposite to that of the impurity using the remaining film, the gate electrode, and the device isolation region as a mask. a step of removing the remaining film; a step of converting the oxidizable film into an oxide film; and a step of adding an impurity of a second conductivity type to the impurity with a conductivity type opposite to that of the impurity using at least the gate electrode and the element isolation region as a mask. 1. A method for manufacturing a complementary semiconductor device, comprising the step of selectively doping an element region. 2. The method of manufacturing a complementary semiconductor device according to claim 1, wherein the oxidizable film is made of polycrystalline silicon. 3 The thickness of the oxidizable film is 1/ of the thickness of the insulating film.
Claim 1 characterized in that the thickness is greater than 2.
A method for manufacturing a complementary semiconductor device according to section 1. 4. The method of manufacturing a complementary semiconductor device according to claim 1, wherein the second conductivity type impurity is doped after the remaining film is removed.