JPH023242A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent deterioration of operation speed by element separation property between adjacent high concentration S/D areas, or increase of junction capacitance and oxide film capacity by keeping the shape of the end part and the thickness of a field SiO2 film as they are at the initial stage at the time of high concentration S/D area formation. CONSTITUTION:When forming a sidewall 29 by anisotropically etching the third SiO2 film 9, the field SiO2 film 2 is never etched by some overetching since the second polysilicon film 8 being the ground is protecting the field SiO2 film 2 from the overetching. Thereafter, with the field SiO2 film 2, the sidewall 29 and the polysilicon gate electrode as a mask, high concentration N type impurity is selectively introduced into a P type Si substrate through a second SiO2 film 5 and a second polysilicon film, and is annealed so as to form high concentration S/D areas 10 and 11. At this time, the end shape end the thickness of the field SiO2 film 2 are kept as they are at the initial stage.

Description

Detailed Description of the Invention (a) Industrial Application Field The present invention relates to a method for manufacturing a semiconductor device, and in particular to a semiconductor device having an LDD structure and a gate structure having sidewall spacers that can improve element isolation characteristics. The present invention relates to a method for manufacturing a device.

(b) Prior Art FIGS. 2(a), 2(b), and 2(c) are cross-sectional views of essential steps for explaining a conventional method for manufacturing a semiconductor device.

In the same figure (a), first, a P-type semiconductor substrate (for example, St
A field 5i0* film (102) is formed using a partial oxidation method or the like, except for a portion of the substrate (101) that will become an active region. Next, the entire surface is covered with a SiO2 film (about 200 people thick)
A polysilicon film (approximately 4000 mm thick) is deposited, and an N-type impurity such as phosphorus is introduced into the polysilicon film. After that, patterning is performed to place the gate S at an appropriate position in the active region.
iO2 film (123) and polysilicon gate electrode (124)
) to form. Furthermore, a thin (SiO2 film (105)) is formed on the entire surface, and the field SiO2 film (102) and polysilicon gate electrode (12) are connected via this SiO2 film (105).
4) as a mask, a low concentration of N-type impurity is applied to the P-type semiconductor substrate (101) by ion implantation (hereinafter referred to as I
selectively introduced using technology (abbreviated as I). Further annealing is performed to form a lightly doped source region (106) and a lightly doped drain region (107).

After that, install the side wall spacer (112) in the same figure (b).
) A SiO2 film (113) for formation is deposited on the entire surface of the P-type semiconductor substrate.

Next, in the same figure (b), the side wall spacer (1
In order to form 12), the SiO2 film (113) shown in FIG.
Although anisotropic etching is performed, the SiO2 film at end A of the field SiO2 film (102) is often overetched and the Si substrate in this area is exposed. Furthermore, the field SiO2 film (102) itself becomes less floating.

Next, in the same figure (c), the blocking SiO2 film (
114) (several hundred thick) on the Si substrate, sidewall spacer (112) and field)'Sin
Using the G film (102) and the polysilicon gate electrode (104) as masks, a high concentration of N-type impurity is introduced into the Si substrate.
High concentration S/D regions (110) (111) are formed.

(c) Problems to be Solved by the Invention However, according to the above-mentioned conventional method, over-etching occurs during anisotropic etching of the sidewall spacer (112), as shown in part A of FIG. SiO at the edge of the field SiO2 film (102).

The film is also removed and the high concentration S/D area (110) (111)
When a high concentration S/D region is formed, the width of the high concentration S/D region increases, and the distance between adjacent high concentration S/D regions becomes narrower, as shown in FIG. 3(c). Therefore, the junction capacitance formed between the P-type Si substrate (101) and the high-concentration S/D regions (110) (111) increases, which hinders high speed operation and is also undesirable for the isolation characteristics.

Also, the thickness of the field 5i0* film (102) itself becomes thinner because the Aj2 electrode etc. wired on the field SiO2 film (102) reduces the thickness of the field 5i0* film (102).
102) The P-type Si substrate immediately below is also easily affected, which is unfavorable in terms of separation characteristics.

Therefore, an object of the present invention is to solve the above problems and improve the performance of a semiconductor device.

(d) Means for solving the problem The above problem involves a step of partially forming a field SiO2 film at an appropriate position on a semiconductor substrate of one conductivity type, and a semiconductor of the one conductivity type on which the field SiO2 film is formed. A step of forming a first SiO2 film to become a gate 5iot film on the entire surface of the substrate, a step of forming a first SiO2 film on the first SiO film, and a step of forming the first polysilicon film with opposite conductivity. The step of introducing impurities in the form of SiO2
a step of patterning the first polysilicon film in an appropriate portion where no film is formed to form a polysilicon gate electrode and a gate SiO2 film;
A second Si layer is deposited on the entire surface of the semiconductor substrate of one conductivity type on which the film is placed.
n! a step of forming a film, and using the polysilicon gate electrode and the field SiO2 film as a mask, a low concentration impurity of an opposite conductivity type is selectively introduced into the semiconductor of the one conductivity type through the first and second SiO2 films. a step of forming a second polysilicon film on the entire surface of the semiconductor substrate of one conductivity type; and a step of forming a third silicon film on the second polysilicon film.
The step of forming an O2 film and the third Sin! forming a sidewall by anisotropic etching so that a film is left only around the polysilicon gate electrode, and etching the sidewall, the polysilicon electrode, and the field S.
selectively introducing high concentration impurities of opposite conductivity type into the semiconductor substrate of one conductivity type through the second polysilicon film and the first and second SiO films using the iO2 film as a mask; and a step of etching and removing the third SiO2 film and the second polysilicon film.

(*) In other words, in the present invention, when anisotropic etching is performed to form a sidewall using a SiO film as a mask for forming a high concentration S/D region, a polysilicon film is spread over the entire surface as a base layer to form a sidewall. This polysilicon film also acts as a buffer against over-etching during formation and prevents the field Sign film from being etched.

As a result, the interval between adjacent high concentration S/D regions does not become narrow, and the thickness of the field SiO2 film is maintained at its initial value, thereby preventing deterioration of the operating speed and element isolation characteristics of the semiconductor device.

(f) Example The present invention will now be described in detail with reference to an illustrated example.

FIGS. 1(a) to 1(f) are cross-sectional views of main steps for explaining the method for manufacturing a semiconductor device according to the present invention.

In the same figure (a), (1) is a P-type semiconductor substrate (for example, a Si substrate), and a field SiO2 film (2) for element isolation is selectively placed at an appropriate position except for the area where active elements are formed. A gate 510w film ((
b) Thickness as shown in Figure (23)) ~ 200 people 0 1st S
The iO2 film is formed into a polysilicon gate electrode (
(b) A first polysilicon film (4) having a thickness of about 4,000 layers as shown in FIG. 24 is formed by CVD. Thereafter, to make the first polysilicon film (4) N-type, an N-type impurity such as phosphorus is introduced by thermal diffusion or II.

Next, as shown in the same figure (b), the polysilicon gate electrode (24) and the gate SiO2 film (
23) is formed.

After that, as shown in the same figure (c), a second SiO2 film (5) for blocking of about 200 people is formed, and then a field SiO2 film (2) is formed through this SiO2 film.
and polysilicon gate electrode <24) as a mask,
A low concentration N-type impurity is selectively introduced into the P-type Si substrate using II, and annealing is performed to form a low concentration S/D region.

Next, as shown in FIG. 4(d), a second SiO2 film (8) (with a thickness of about 500 mm) and a third SiO2 film (9 )
(thickness approximately 2,000 mm) is deposited by the CVD method.

Next, in the same figure (e), the third SiOx film (9) is anisotropically etched to form a sidewall (29).

At this time, since the underlying second polysilicon film (8) protects the field SiO2 film (2) from over-etching, the field Si film will not be etched even if there is some over-etching.

After that, using the field Sign film (2), sidewall (29), and polysilicon gate electrode as a mask, high concentration N-type impurity is applied through the second 5xOt film (5) and the second polysilicon film. is selectively introduced into a P-type Si substrate and annealed to form high concentration S/D regions (10) and (11). At this time, as mentioned above, the end shape and thickness of the field SiO2 film (2) are maintained as they were at the initial stage, so the element isolation characteristics between adjacent high concentration S/D regions can be improved through the field SiO2 film. Deterioration in operating speed due to increase in capacitive junctions and oxide film can be prevented.

After the above steps, the sidewall (
10) and the second polysilicon film are removed by etching.

The semiconductor device is completed by following the usual steps, but the explanation will be omitted.

Although the above explanation was made for a P-type Si substrate, it goes without saying that it is also effective for a manufacturing method that uses impurities of the opposite type in an N-type Si substrate.

(G) Effects of the Invention As described above, according to the present invention, when forming a high concentration S/D region, the end shape and thickness of the field 5iot film are maintained as they were at the initial stage. This is effective in preventing deterioration in device isolation characteristics between adjacent high-concentration S/D regions, and in operating speed due to increases in junction capacitance and oxide film capacitance.

[Brief explanation of the drawing]

FIGS. 1(a) to (f) are cross-sectional views of main steps for explaining the method for manufacturing a semiconductor device according to the present invention, and FIGS. 2(a) to (c)
FIG. 2 is a cross-sectional view of main steps for explaining a conventional method for manufacturing a semiconductor device. In the figure, (1), <101)...P-type semiconductor substrate, (2), (102)...field SiO
2 film, (3)...first SiO film, (4)...
・First polysilicon film, (5)...second SiO2
Film, (6), (106)...Low concentration source region, (7), (107)...Low concentration drain region, (8)...Second polysilicon film, (9)...
・Third (7) SiO. Film, (10), (110)...high concentration source region, (11). (111)...high concentration drain region, (105)
, (113)...Si0g film, (23) ,
(123)...Gate Si film, (24). (124)...Polysilicon gate electrode, (29)...
・・Side wall, (12), (112)・・
・Side wall spacer is shown.

Claims (1)

[Claims] (1) LDD (Lightly Doped Drai)
n) In a semiconductor device having a structure and a gate structure having sidewall spacers, a step of partially forming a field SiO_2 film at an appropriate position on a semiconductor substrate of one conductivity type;
a step of forming a first SiO_2 film to become a gate SiO_2 film on the entire surface of the semiconductor substrate of one conductivity type on which an O_2 film is formed; a step of forming a first polysilicon film on the first SiO_2 film; , a step of introducing impurities of opposite conductivity type into the first polysilicon film, and patterning the first polysilicon film in an appropriate portion where the field SiO_2 film is not formed to form a polysilicon gate electrode and a gate. a step of forming a second SiO_2 film on the entire surface of the semiconductor substrate of one conductivity type on which the polysilicon gate electrode, the gate SiO_2 film and the field SiO_2 film are mounted; selectively introducing low concentration impurities of opposite conductivity type into the semiconductor substrate of the one conductivity type through the first and second SiO_2 films using the electrode and the field SiO_2 film as a mask; forming a second polysilicon film on the entire surface of the semiconductor substrate; forming a third SiO_2 film on the second polysilicon film; and depositing the third SiO_2 film on the polysilicon gate electrode. a step of forming a sidewall by anisotropic etching so as to leave it only on the periphery; and a step of etching the second polysilicon film and the first and second polysilicon films using the sidewall, the polysilicon electrode, and the field SiO_2 film as a mask. selectively introducing high concentration impurities of the opposite conductivity type into the semiconductor substrate of the one conductivity type through the second SiO_2 film; and etching and removing the third SiO_2 film and the second polysilicon film. A method for manufacturing a semiconductor device, comprising the steps of: