KR0146079B1 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- KR0146079B1 KR0146079B1 KR1019950021851A KR19950021851A KR0146079B1 KR 0146079 B1 KR0146079 B1 KR 0146079B1 KR 1019950021851 A KR1019950021851 A KR 1019950021851A KR 19950021851 A KR19950021851 A KR 19950021851A KR 0146079 B1 KR0146079 B1 KR 0146079B1
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- concentration impurity
- gate
- film
- region
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title abstract description 13
- 239000012535 impurity Substances 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 13
- 229920005591 polysilicon Polymers 0.000 claims abstract description 13
- 125000006850 spacer group Chemical group 0.000 claims abstract description 13
- 238000005468 ion implantation Methods 0.000 claims abstract description 11
- 230000001681 protective effect Effects 0.000 claims abstract description 9
- 238000009792 diffusion process Methods 0.000 claims abstract description 8
- 238000002955 isolation Methods 0.000 claims abstract description 8
- 238000010438 heat treatment Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 abstract description 33
- 238000000206 photolithography Methods 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 239000010408 film Substances 0.000 description 28
- 239000005360 phosphosilicate glass Substances 0.000 description 15
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
Abstract
본 발명은 반도체 소자 제조방법에 관한 것으로, 소자격리 영역과 액티브 영역이 정의된 반도체 기판 위에 절연막에 의해 기판과 분리되며, 진성 폴리 실리콘층과 PSG막이 적층된 형태의 게이트를 형성하는 공정과; 열처리 공정에 의해 PSG막 측벽 스페이서 및 보호막을 형성하는 공정과; 상기 PSG막 내의 불순물 확산 공정을 통해 게이트 내로 불순물을 도핑시킴과 동시에 저농도 불순물 영역을 형성하는 공정 및; 이온주입을 실시하여 고농도 불순물 영역을 형성하는 공정을 구비하여 소자제조를 완료하므로써, 별도의 게이트 형성 공정과 측벽 스페이서 형성 공정 및 저농도 불순물 영역 형성을 위한 사진식각공정이 필요하지 않아 공정단순화를 기할 수 있을 뿐 아니라 상기 보호막으로 인해 고농도 불순물 영역 형성을 위한 이온주입공정시 야기되던 기판 표면의 손상을 방지할 수 있게 된다.The present invention relates to a method for manufacturing a semiconductor device, the method comprising: forming a gate in which an insulated polysilicon layer and a PSG film are stacked on a semiconductor substrate on which a device isolation region and an active region are defined by an insulating film; Forming a PSG film sidewall spacer and a protective film by a heat treatment step; Forming a low concentration impurity region at the same time as doping impurities into the gate through an impurity diffusion process in the PSG film; By completing ion fabrication by performing ion implantation to form high-concentration impurity regions, a separate gate formation process, sidewall spacer formation process, and photolithography process for forming low-concentration impurity regions are not necessary, thereby simplifying the process. In addition, the protective film prevents damage to the substrate surface caused during the ion implantation process for forming a high concentration impurity region.
Description
제 1(a)도 내지 제 1(g)도는 종래 기술에 따른 반도체 소자 제조공정을 도시한 공정수순도,1 (a) to 1 (g) is a process flowchart showing a semiconductor device manufacturing process according to the prior art,
제 2(a)도 내지 제 2(d)도는 본 발명에 따른 반도체 소자 제조공정을 도시한 공정수순도.2 (a) to 2 (d) is a process flowchart showing a semiconductor device manufacturing process according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체 기판 2 : 게이트 절연막1 semiconductor substrate 2 gate insulating film
3 : 진성 폴리 실리콘 4 : 불순물이 도핑된 폴리 실리콘3: intrinsic polysilicon 4: impurity doped polysilicon
5 : CVD 산화막 6 : 격리막5: CVD oxide film 6: separator
7 : CVD 산화막 측벽 스페이서 8 : PSG막 측벽 스페이서7 CVD oxide film sidewall spacer 8 PSG film sidewall spacer
9 : 보호막 10 : 감광막 패턴9: protective film 10: photosensitive film pattern
11 : PSG막11: PSG film
본 발명은 반도체 소자 제조방법에 관한 것으로, 특히 고온에서 우수한 유량(flow) 특성 및 불순물 확산 특성을 갖는 PSG(phospho-silicate glass) 박막을 이용한 LDD(lightly doped drain) 모스 전계방출트랜지스터(이하, MOS FET한다) 구조의 반도체 소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, a lightly doped drain (LDD) MOS field emission transistor (PSS) using a phospho-silicate glass (PSG) thin film having excellent flow characteristics and impurity diffusion characteristics at a high temperature. FET) structure of the semiconductor device.
종래 일반적으로 사용되어 오던 반도체 소자는 제 1(a)도 내지 제 1(g)도에 도시된 공정수순도에서 알 수 있듯이 먼저, 제 1(a)도에 도시된 바와 같이 실리콘 기판(1) 상에 열산화 공정으로 격리막(6)을 형성하여 액티브 영역을 정의하고, 상기 액티브 영역에 게이트 절연막(2)을 형성한 후, 상기 게이트 절연막(2) 및 격리막(6) 상에 불순물이 도핑되지 않은 진성 폴리 실리콘층(3)을 증착하고, 상기 폴리 실리콘층 내로 이온을 주입하여 불순물이 도핑된 폴리 실리콘층(4)을 형성한다.The semiconductor device, which has been generally used in the prior art, can be seen from the process steps shown in FIGS. 1 (a) to 1 (g). First, as shown in FIG. 1 (a), the silicon substrate 1 After the isolation layer 6 is formed on the active region to define an active region, and the gate insulating layer 2 is formed in the active region, impurities are not doped on the gate insulating layer 2 and the isolation layer 6. An intrinsic polysilicon layer 3 is deposited and ions are implanted into the polysilicon layer to form a polysilicon layer 4 doped with impurities.
그 후, 사진식각 공정으로 상기 불순물이 도핑된 폴리 실리콘층을 식각하여 게이트 절연막(2)에 의해 기판과 절연되는 게이트를 형성한다.Thereafter, the polysilicon layer doped with the impurity is etched by a photolithography process to form a gate insulated from the substrate by the gate insulating layer 2.
그 다음, 제 1(c)도에 도시된 바와 같이 반도체 기판 전면에 상기 게이트(4)를 마스크로 한 이온주입 공정으로 기판 내에 저농도 불순물층을 형성하고, 제 2(d)도에 도시된 바와 같이 상기 패턴 전면에 CVD 산화막(6)을 증착한다.Next, as shown in FIG. 1 (c), a low concentration impurity layer is formed in the substrate by an ion implantation process using the gate 4 as a mask on the entire surface of the semiconductor substrate, and as shown in FIG. 2 (d). Likewise, a CVD oxide film 6 is deposited on the entire surface of the pattern.
이어서, 제 1(e)도에 도시된 바와 같이 상기 CVD 산화막(6)을 에치백하여 게이트 양 측벽에 측벽 스페이서(7)를 형성하고, 표면 보호용 산화막(9)을 형성한다.Subsequently, as shown in FIG. 1 (e), the CVD oxide film 6 is etched back to form sidewall spacers 7 on both sidewalls of the gate, and the oxide film 9 for surface protection is formed.
계속해서, 제 1(f)도에 도시된 바와 같이 상기 게이트 상에 마스크로 사용될 감광막 패턴(10)을 형성하고, 상기 감광막 패턴(10) 및 측벽 스페이서(7)를 마스크로 고농도 불순물 이온주입 공정을 실시하여 이미 형성시킨 저농도 불순물층과 구별되는 고농도 불순물층을 형성하므로써 LDD 영역을 정의한다.Subsequently, as shown in FIG. 1 (f), a photoresist pattern 10 to be used as a mask is formed on the gate, and a high concentration impurity ion implantation process is performed using the photoresist pattern 10 and the sidewall spacers 7 as a mask. The LDD region is defined by forming a high concentration impurity layer which is different from the low concentration impurity layer already formed by performing the following steps.
이후, 상기 게이트 상에 형성된 감광막 패턴(10)을 제거하여 소자 제조를 완료한다.Thereafter, the photoresist pattern 10 formed on the gate is removed to complete device fabrication.
그러나 상기 공정을 통해 소자를 제조할 경우에는 반도체 기판 상에 게이트를 형성하는 경우나, 고농도 불순물층을 형성하기 위한 이온주입 공정시 게이트에 과도한 불순물이 주입되는 것을 방지하기 위하여 마스크를 형성하는 경우에 있어서, 그 각각의 공정 진행시 사진식각 공정이 필요로 될 뿐 아니라, 저농도 불순물층의 형성과 고농도 불순물층의 형성을 위해서도 각각의 이온주입 공정이 필요로 되어 공정 진행이 복잡하다는 단점을 가지게 된다.However, when the device is manufactured through the above process, a gate is formed on a semiconductor substrate or a mask is formed to prevent excessive impurities from being injected into the gate during an ion implantation process for forming a high concentration impurity layer. Therefore, not only the photolithography process is required during each process, but also the ion implantation process is required for the formation of the low concentration impurity layer and the formation of the high concentration impurity layer.
이에 본 발명은 상기와 같은 단점을 해결하기 위하여 이루어진 것으로, 고온에서 우수한 유량 특성 및 불순물 확산 특성을 갖는 PSG 박막을 이용하여 소자 제조를 완료하므로써 공정 단순화를 기할 수 있도록 한 반도체 소자 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above disadvantages, to provide a semiconductor device manufacturing method that can simplify the process by completing the device manufacturing using a PSG thin film having excellent flow characteristics and impurity diffusion characteristics at high temperature The purpose is.
상기와 같은 목적을 달성하기 위한 본 발명의 바람직한 실시예에 따른 반도체 소자 제조방법은 소자격리 영역과 액티브 영역이 정의된 반도체 기판 위에 절연막에 의해 기판과 분리되며, 진성 폴리 실리콘층과 PSG막이 적층된 형태의 게이트를 형성하는 공정과; 열처리 공정에 의해 PSG막 측벽 스페이서 및 보호막을 형성하는 공정과; 상기 PSG막 내의 불순물 확산 공정을 통해 게이트 내로 불순물을 도핑시킴과 동시에 저농도 불순물 영역을 형성하는 공정 및; 이온주입을 실시하여 고농도 불순물 영역을 형성하는 공정으로 이루어진 것을 특징으로 한다.A semiconductor device manufacturing method according to a preferred embodiment of the present invention for achieving the above object is separated from the substrate by an insulating film on a semiconductor substrate in which the device isolation region and the active region are defined, the intrinsic polysilicon layer and the PSG film is laminated Forming a gate of a form; Forming a PSG film sidewall spacer and a protective film by a heat treatment step; Forming a low concentration impurity region at the same time as doping impurities into the gate through an impurity diffusion process in the PSG film; It is characterized by consisting of a step of forming a high concentration impurity region by performing ion implantation.
상기 공정 결과, 반도체 소자 제조공정을 단순화할 수 있게 된다.As a result, the semiconductor device manufacturing process can be simplified.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
제 2(a)도 내지 제 2(d)는 본 발명에 따른 반도체 소자 제조공정을 도시한 공정수순도를 나타낸 것으로, 이를 참조하여 그 구체적인 제조방법을 살펴보면 다음과 같다.2 (a) to 2 (d) show a process flow diagram showing a semiconductor device manufacturing process according to the present invention. Referring to this, the specific manufacturing method is as follows.
먼저, 제 2(a)도에 도시된 바와 같이 열산화 공정으로 반도체 기판(1) 상에 격리막(6)을 성장시켜 액티브 영역을 정의하고, 상기 액티브 영역에 게이트 절연막(2)을 형성한 후, 상기 게이트 절연막(2) 및 격리막(6) 상에 불순물이 도핑되지 않은 진성 폴리 실리콘층(3)을 저압 화학기상증착법으로 증착하고, 연이어 상기 진성 폴리 실리콘층(3) 상에 상압 화학기상증착법으로 PSG막(11)을 증착한다.First, as shown in FIG. 2 (a), the active layer is grown on the semiconductor substrate 1 by thermal oxidation to define an active region, and then a gate insulating layer 2 is formed in the active region. And depositing an intrinsic polysilicon layer 3 which is not doped with impurities on the gate insulating layer 2 and the isolation layer 6 by a low pressure chemical vapor deposition method, followed by an atmospheric pressure chemical vapor deposition method on the intrinsic polysilicon layer 3. The PSG film 11 is deposited.
그 다음, 제 2(b)도에 도시된 바와 같이 사진식각공정을 실시하여 게이트 절연막(2) 위에 기판과 절연되며, 상부에 PSG막(11)이 형성되어 있는 게이트를 형성한다.Then, as shown in FIG. 2 (b), a photolithography process is performed to form a gate insulated from the substrate on the gate insulating film 2 and the PSG film 11 formed thereon.
이어서, 제 2(c)도에 도시된 바와 같이 산화 분위기에서의 고온 열처리 공정을 통하여 게이트 상부의 PSG막(11)을 유동시켜 게이트 측면에 측벽 스페이서(8)를 형성함과 동시에 격리막(6)을 포함한 노출된 기판상에 보호막(9)을 형성하고, PSG막(11) 내의 불순물 확산 공정으로 게이트인 진성 폴리 실리콘(3) 내에 불순물을 도핑시켜 불순물이 도핑된 폴리 실리콘(4)을 형성한다. 이 때, 측벽 스페이서(8) 내의 불순물 확산 공정에 의해 그 하부의 반도체 기판(1)에 저농도 불순물층이 형성된다.Subsequently, as shown in FIG. 2 (c), the PSG film 11 on the gate flows through the high temperature heat treatment process in an oxidizing atmosphere to form the sidewall spacer 8 on the side of the gate, and at the same time, the isolation film 6 A protective film 9 is formed on the exposed substrate, and the dopant is doped in the intrinsic polysilicon 3 as a gate by an impurity diffusion process in the PSG film 11 to form the doped polysilicon 4. . At this time, a low concentration impurity layer is formed in the semiconductor substrate 1 under the impurity diffusion process in the sidewall spacer 8.
이후, 제 2(d)도에 도시된 바와 같이 게이트 상부의 PSG막과 측벽 스페이서(8)를 마스크로 고농도 불순물 이온주입공정을 실시하여 이미 형성된 저농도 불순물층과 구별되는 고농도 불순물층을 형성하므로써 본 공정을 완료한다.Subsequently, as shown in FIG. 2 (d), a high concentration impurity ion implantation process is performed using the PSG film and the sidewall spacer 8 on the gate as a mask to form a high concentration impurity layer which is distinguished from the low concentration impurity layer already formed. Complete the process.
이 때, 상기 보호막(9)은 고농도 불순물 영역 형성을 위한 이온주입공정 진행시 기판 표면이 손상되는 것을 방지해 주는 역할을 담당한다.At this time, the protective film 9 plays a role of preventing the surface of the substrate from being damaged during the ion implantation process for forming a high concentration impurity region.
상술한 바와 같이 본 발명에 의하면, 고온 산화 분위기에서의 열처리 공정을 통해 PSG막 측벽 스페이서를 형성함과 동시에 보호막을 형성하고, 상기 PSG막 내의 불순물 확산공정을 통해 게이트 내에 불순물을 도핑시킴과 동시에 저농도 불순물 영역을 형성할 수 있게 되어, 별도의 게이트 형성 공정과 측벽 스페이서 형성 공정 및 저농도 불순물 영역 형성을 위한 사진식각공정이 필요하지 않아 공정단순화를 기할 수 있을 뿐 아니라 상기 보호막으로 인해 고농도 불순물 영역 형성을 위한 이온주입공정시 야기되던 기판 표면의 손상을 방지할 수 있게 된다.As described above, according to the present invention, a PSG film sidewall spacer is formed through a heat treatment in a high temperature oxidizing atmosphere, a protective film is formed, and impurities are doped in the gate through a impurity diffusion process in the PSG film, and at the same time, a low concentration is achieved. Since the impurity region can be formed, a separate gate forming process, a sidewall spacer forming process, and a photolithography process for forming a low concentration impurity region are not necessary, thereby simplifying the process and forming a high concentration impurity region due to the protective film. It is possible to prevent damage to the surface of the substrate caused during the ion implantation process.
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