JPH0527995B2 - - Google Patents
Info
- Publication number
- JPH0527995B2 JPH0527995B2 JP59159658A JP15965884A JPH0527995B2 JP H0527995 B2 JPH0527995 B2 JP H0527995B2 JP 59159658 A JP59159658 A JP 59159658A JP 15965884 A JP15965884 A JP 15965884A JP H0527995 B2 JPH0527995 B2 JP H0527995B2
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- polycrystalline silicon
- impurity layer
- opposite conductivity
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000012535 impurity Substances 0.000 claims description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 239000002784 hot electron Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、MOS型半導体装置の製造方法の改
良に関する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an improvement in a method of manufacturing a MOS type semiconductor device.
従来例の構成とその問題点
従来、MOS型トランジスタの形成法としては、
第１図の断面図に示すｎチヤンネルトランジスタ
を例とすれば、Ｐ型半導体基板１の素子分離領域
（図示せず）にチヤンネルストツパーとしてホウ
素をイオン注入し、LOCOS法によりフイールド
酸化膜を形成する。その後、トランジスタ形成領
域にＰ型不純物をイオン注入し、しきい値制御を
行なう。そして、熱酸化処理を施して酸化膜３を
形成し、多結晶シリコン膜を堆積して、フオトエ
ツチング技術を用いてパターニングしてゲート電
極５とする。さらに、このゲート電極をマスクと
して、ゲート酸化膜３をパターニングし、ひきつ
づき、ゲート電極５をマスクとしてｎ型不純物を
イオン注入し、ソース・ドレイン部の拡散層２を
作り、熱処理を施して活性化させる。つづいて、
Ａ蒸着によつてソース・ドレインの電極６を形
成し、ｎチヤンネルMOSトランジスタを実現す
る。第１図中、４は層間絶縁膜用のシリコン酸化
膜である。Conventional structure and its problems Conventionally, the method for forming MOS transistors is as follows:
Taking the n-channel transistor shown in the cross-sectional view of FIG. 1 as an example, boron ions are implanted as a channel stopper into the element isolation region (not shown) of the P-type semiconductor substrate 1, and a field oxide film is formed by the LOCOS method. do. Thereafter, P-type impurity ions are implanted into the transistor formation region to control the threshold voltage. Then, a thermal oxidation process is performed to form an oxide film 3, a polycrystalline silicon film is deposited, and the gate electrode 5 is formed by patterning using a photo-etching technique. Furthermore, using this gate electrode as a mask, the gate oxide film 3 is patterned, and subsequently, using the gate electrode 5 as a mask, n-type impurity ions are implanted to form the diffusion layer 2 of the source/drain region, and heat treatment is performed to activate it. let Continuing,
Source and drain electrodes 6 are formed by A vapor deposition to realize an n-channel MOS transistor. In FIG. 1, 4 is a silicon oxide film for an interlayer insulating film.
しかしながら上記方法で形成したMOSトラン
ジスタのサイズは二次元水平方向のみで決定さ
れ、パターン形成技術の限界から、集積度の向上
に制限を与えている。また、第１図示の従来構造
では、集積度を向上させ、トランジスタのチヤン
ネル長1μｍ付近まで短くすると短チヤンネル効
果やホツトエレクトロンの酸化膜への注入現象に
よりデバイスの特性に悪影響を及ぼすといつた問
題点があつた。 However, the size of the MOS transistor formed by the above method is determined only in the two-dimensional horizontal direction, which limits the improvement of the degree of integration due to the limitations of pattern forming technology. In addition, in the conventional structure shown in Figure 1, when the degree of integration is improved and the channel length of the transistor is shortened to around 1 μm, there is a problem that the short channel effect and the injection phenomenon of hot electrons into the oxide film adversely affect the characteristics of the device. The dot was hot.
発明の目的
本発明は、上述のような従来例に見られた問題
点を解消した高集積度MOS型半導体装置を提供
するものである。OBJECTS OF THE INVENTION The present invention provides a highly integrated MOS type semiconductor device that solves the problems seen in the conventional example as described above.
発明の構成
本発明は、一導電型半導体基板の所定領域に反
対導電型の不純物を注入し、反対導電型不純物層
の深い部分と浅い部分とを選択的に形成する工程
と、前記深い反対導電型不純物層が形成された部
分に、異方性エツチングにより前記反対導電型不
純物層とを分離し凹部を形成する工程と、前記凹
部を有する基板表面に酸化膜を形成する工程と、
前記酸化膜のソース・ドレイン領域の電極開孔部
となる箇所をエツチングする工程と、前記凹部を
有する基板表面に多結晶シリコンを堆積する工程
と、前記ソース・ドレイン領域の電極開孔部にレ
ジストを残存させる工程と、異方性エツチングに
より前記凹部側面に多結晶シリコンを残置させゲ
ート電極を形成し、かつ、前記レジストで覆われ
ていない多結晶シリコンを除去し前記レジストで
覆われた多結晶シリコンをソース・ドレイン電極
とする工程と、を含み、前記ソース・ドレイン領
域の一方を前記凹部下の前記深い部分に形成し、
他方を前記浅い部分に形成したものであり、これ
により、短チヤンネル効果やホツトエレクトロン
による問題が除かれ、高集積化が達成される。Structure of the Invention The present invention comprises a step of implanting an impurity of an opposite conductivity type into a predetermined region of a semiconductor substrate of one conductivity type to selectively form a deep portion and a shallow portion of an impurity layer of an opposite conductivity type, and forming a recess in the portion where the type impurity layer is formed by separating it from the opposite conductivity type impurity layer by anisotropic etching; forming an oxide film on the surface of the substrate having the recess;
A step of etching the portions of the oxide film that will become the electrode openings in the source/drain regions, a step of depositing polycrystalline silicon on the surface of the substrate having the recesses, and a step of etching the electrode openings in the source/drain regions. A step of leaving polycrystalline silicon on the side surface of the recess by anisotropic etching to form a gate electrode, and removing the polycrystalline silicon not covered with the resist to remove the polycrystalline silicon covered with the resist. forming one of the source and drain regions in the deep part under the recess,
The other is formed in the shallow portion, thereby eliminating problems caused by short channel effects and hot electrons, and achieving high integration.
実施例の説明
以下にｐチヤンネルMOSトランジスタによる
インバータの製造に本発明を適用した例について
第２図ａからｅを用いて説明する。DESCRIPTION OF EMBODIMENTS An example in which the present invention is applied to the manufacture of an inverter using p-channel MOS transistors will be described below with reference to FIGS. 2a to 2e.
まず、ｎ型シリコン基板７の所定領域に、P+
型不純物層８の深い部分８ａと浅い部分８ｂとを
同時に形成するため、浅い部分８ｂとなるところ
には、注入時のマスクとなるべきレジスト９によ
つて、パターニングする。なお、レジストのかわ
りに酸化膜や窒化膜でも注入条件、膜厚を制御す
ることで代用できる。そして、ホウ素を全面注入
して第２図ａの構造を得る。その後、第２図ｂに
示すようにP+型不純物層８の深き部分８ａと浅
い部分８ｂとを分離し、かつ、深い部分のP+型
不純物層８ａの厚みt1が浅い部分８ｂの厚みt2と
ほぼ同じになるまで、異方性エツチングにより、
P+型不純物層８をエツチングしてシリコン基板
７中に凹部１６を形成する。なお、本実施例で
は、しきい値制御のためのチヤンネル領域への不
純物拡散は、あらかじめｎ型シリコン基板７の濃
度を適切に選んだため必要としなかつたが、必要
な場合は気相拡散にて行なつてもよい。 First, P +
In order to form the deep portion 8a and shallow portion 8b of the type impurity layer 8 at the same time, the portion that will become the shallow portion 8b is patterned using a resist 9, which serves as a mask during implantation. Note that an oxide film or a nitride film can be used instead of the resist by controlling the implantation conditions and film thickness. Then, boron is implanted over the entire surface to obtain the structure shown in FIG. 2a. Thereafter, as shown in FIG. 2b, the deep part 8a and shallow part 8b of the P + type impurity layer 8 are separated, and the thickness t 1 of the P + type impurity layer 8a in the deep part is equal to the thickness of the shallow part 8b. By anisotropic etching until approximately equal to t 2 ,
P + -type impurity layer 8 is etched to form a recess 16 in silicon substrate 7 . In this example, impurity diffusion into the channel region for controlling the threshold value was not necessary because the concentration of the n-type silicon substrate 7 was appropriately selected in advance, but if necessary, vapor phase diffusion could be performed. You may do so.
次に、第２図ｃに示したようにP+型不純物層
８とｎ型シリコン基板７との不純物濃度の違いに
よる酸化速度の差（拡散層上がｎ型シリコン基板
７上より速い）を利用して、熱酸化処理によつて
凹部１６の側壁にはゲート酸化膜３、P+型不純
物層の深い部分８ａと浅い部分８ｂには絶縁用酸
化膜４を同時に形成し、ひきつづきソース・ドレ
イン領域となるP+型不純物層８ａ，８ｂの一部
に電極開孔部１５を形成する。つづいて、多結晶
シリコン１０を堆積し、レジストパターン９を第
２図ｄに示したように、ソース・ドレイン領域と
なるP+型不純物層８の電極開孔部１５を覆つて
形成する。その後、異方性エツチングにより多結
晶シリコン１０をエツチングして、第２図ｅに示
したように凹部１６の側面に多結晶シリコンを残
置して第１ゲート電極１１、第２ゲート電極１２
を形成するとともに、凹部１６の下の深い部分８
ａ上に設けた電極開孔部１５上の多結晶シリコン
を残して、ソース・ドレイン多結晶シリコン電極
１３の一方を形成することで本願発明のMOSト
ランジスタが得られる。 Next, as shown in FIG. 2c, the difference in oxidation rate due to the difference in impurity concentration between the P + type impurity layer 8 and the n-type silicon substrate 7 (the rate on the diffusion layer is faster than on the n-type silicon substrate 7) is calculated. The gate oxide film 3 is simultaneously formed on the side wall of the recess 16, the insulating oxide film 4 is formed on the deep part 8a and the shallow part 8b of the P + type impurity layer by thermal oxidation treatment, and then the source/drain An electrode opening 15 is formed in a part of the P + type impurity layers 8a and 8b, which will be the regions. Subsequently, polycrystalline silicon 10 is deposited, and a resist pattern 9 is formed to cover the electrode opening 15 of the P + type impurity layer 8, which will become the source/drain region, as shown in FIG. 2d. Thereafter, the polycrystalline silicon 10 is etched by anisotropic etching, leaving the polycrystalline silicon on the side surfaces of the recess 16 as shown in FIG.
, and the deep part 8 below the recess 16
The MOS transistor of the present invention is obtained by forming one of the source/drain polycrystalline silicon electrodes 13, leaving the polycrystalline silicon on the electrode opening 15 provided on the electrode a.
発明の効果
本発明によれば、半導体基板に凹部を形成し、
その中にMOSトランジスタのソース・ドレイン
領域の一方およびゲート領域を形成したので、集
積度を向上させ、しかも、微細化に伴う短チヤン
ネル効果やホツトエレクトロンによる問題を発生
しないデバイスが達成できる。Effects of the Invention According to the present invention, a recess is formed in a semiconductor substrate,
Since one of the source/drain regions and the gate region of the MOS transistor are formed therein, it is possible to improve the degree of integration and achieve a device that does not suffer from short channel effects or hot electron problems associated with miniaturization.
第１図は、従来のｎチヤンネルMOSトランジ
スタの断面図、第２図ａ〜ｅは、本発明の用いた
ＰチヤンネルMOSトランジスタの製造工程を示
す断面図である。
１……Ｐ型シリコン基板、２……n+型不純物
層、３……ゲート酸化膜、４……層間絶縁用酸化
膜、５……多結晶シリコンゲート電極、６……ア
ルミニウムのソース・ドレイン電極、７……ｎ型
シリコン基板、８……P+型不純物層、８ａ……
深い部分、８ｂ……浅い部分、９……レジスト、
１０……多結晶シリコン、１１……第１多結晶シ
リコンゲート電極、１２……第２多結晶シリコン
ゲート電極、１３……ソース・ドレイン多結晶シ
リコン電極、１５……電極開孔部、１６……凹
部。
FIG. 1 is a sectional view of a conventional n-channel MOS transistor, and FIGS. 2 a to 2e are sectional views showing the manufacturing process of a p-channel MOS transistor used in the present invention. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... n + type impurity layer, 3... gate oxide film, 4... oxide film for interlayer insulation, 5... polycrystalline silicon gate electrode, 6... aluminum source/drain Electrode, 7... n-type silicon substrate, 8... P + type impurity layer, 8a...
deep part, 8b...shallow part, 9...resist,
DESCRIPTION OF SYMBOLS 10... Polycrystalline silicon, 11... First polycrystalline silicon gate electrode, 12... Second polycrystalline silicon gate electrode, 13... Source/drain polycrystalline silicon electrode, 15... Electrode opening, 16... ...concavity.
Claims (1)
の不純物を注入し、反対導電型不純物層の深い部
分と浅い部分とを選択的に形成する工程と、前記
深い反対導電型不純物層が形成された部分に、異
方性エツチングにより前記深い反対導電型不純物
層よりも浅く凹部を形成し、前記深い反対導電型
不純物層と前記浅い反対導電型不純物層とを分離
する工程と、前記凹部を有する基板表面に酸化膜
を形成する工程と、前記酸化膜のソース・ドレイ
ン領域の電極開孔部となる箇所をエツチングする
工程と、前記凹部を有する基板表面に多結晶シリ
コンを堆積する工程と、前記ソース・ドレイン領
域の電極開孔部にレジストを残存させる工程と、
異方性エツチングにより前記凹部側面に多結晶シ
リコンを残置させゲート電極を形成し、かつ、前
記レジストで覆われていない多結晶シリコンを除
去し前記レジストで覆われた多結晶シリコンをソ
ース・ドレイン電極とする工程と、を含み、前記
ソース・ドレイン領域の一方を前記凹部下の前記
深い部分に形成し、他方を前記浅い部分に形成し
たことを特徴とするMOS型半導体装置の製造方
法。1 A step of implanting an impurity of an opposite conductivity type into a predetermined region of a semiconductor substrate of one conductivity type to selectively form a deep portion and a shallow portion of the impurity layer of the opposite conductivity type, and forming the deep impurity layer of the opposite conductivity type. forming a recess shallower than the deep opposite conductivity type impurity layer in the etched portion by anisotropic etching to separate the deep opposite conductivity type impurity layer from the shallow opposite conductivity type impurity layer; a step of forming an oxide film on the surface of the substrate; a step of etching portions of the oxide film that will become electrode openings in the source/drain regions; a step of depositing polycrystalline silicon on the surface of the substrate having the recessed portions; a step of leaving resist in the electrode openings in the source/drain regions;
Polycrystalline silicon is left on the side surfaces of the recess by anisotropic etching to form a gate electrode, and the polycrystalline silicon not covered with the resist is removed and the polycrystalline silicon covered with the resist is used as source/drain electrodes. A method of manufacturing a MOS type semiconductor device, comprising the steps of: forming one of the source/drain regions in the deep part under the recess, and forming the other in the shallow part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15965884A JPS6136974A (en) | 1984-07-30 | 1984-07-30 | Manufacture of mos semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15965884A JPS6136974A (en) | 1984-07-30 | 1984-07-30 | Manufacture of mos semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6136974A JPS6136974A (en) | 1986-02-21 |
| JPH0527995B2 true JPH0527995B2 (en) | 1993-04-22 |
Family
ID=15698512
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15965884A Granted JPS6136974A (en) | 1984-07-30 | 1984-07-30 | Manufacture of mos semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6136974A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63292677A (en) * | 1987-05-25 | 1988-11-29 | Nec Corp | Semiconductor integrated circuit device |
| KR100701701B1 (en) | 2005-08-30 | 2007-03-29 | 주식회사 하이닉스반도체 | Semiconductor device and method of manufacturing the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS566448A (en) * | 1979-06-28 | 1981-01-23 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Mos type integrated circuit device |
-
1984
- 1984-07-30 JP JP15965884A patent/JPS6136974A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS566448A (en) * | 1979-06-28 | 1981-01-23 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Mos type integrated circuit device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6136974A (en) | 1986-02-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH1126597A (en) | Fabrication of semiconductor device | |
| JPH0355984B2 (en) | ||
| JPH058587B2 (en) | ||
| JPS59220971A (en) | Manufacture of semiconductor device | |
| JPH07153952A (en) | Semiconductor device and manufacture thereof | |
| JP2730535B2 (en) | Method for manufacturing semiconductor device | |
| JPH098135A (en) | Manufacture of semiconductor device | |
| JPH0527995B2 (en) | ||
| JPS6025028B2 (en) | Manufacturing method of semiconductor device | |
| JPH0637106A (en) | Manufacture of semiconductor device | |
| JPS6237543B2 (en) | ||
| JPH07273183A (en) | Semiconductor device and its fabrication | |
| JPH0491481A (en) | Mis field effect transistor | |
| JPH04196341A (en) | Manufacture of semiconductor device | |
| JPS6156448A (en) | Manufacture of complementary semiconductor device | |
| JP2705583B2 (en) | Method for manufacturing semiconductor device | |
| JPH0481339B2 (en) | ||
| JP2001257346A (en) | Semiconductor integrated circuit device | |
| JPH0431193B2 (en) | ||
| JP2001217236A (en) | Method for manufacturing semiconductor | |
| JPH0766400A (en) | Semiconductor and its manufacture | |
| JPS626664B2 (en) | ||
| JPH07122741A (en) | Manufacture of semiconductor device | |
| JPH11289082A (en) | Semiconductor device and its manufacture | |
| JPH1126756A (en) | Manufacture of semiconductor device |