JP2001217236A - Method for manufacturing semiconductor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device for subdividing an element and at the same time improving an element isolation breakdown voltage. SOLUTION: The manufacturing method of a semiconductor device is provided with a process for forming an LOCOS oxide film 4 on the surface of a P well 1 of a silicon substrate, a process for forming a resist pattern 5 on the LOCOS oxide film 4, and a process for forming a channel stopper 7 on the P well 1 by implanting an impurity ion 6 with the resist pattern 5 as a mask. Length L between the outer periphery of the resist pattern 5 and the end part of the LOCOS oxide film 4 is equal to or more than 0.2 μm and is equal to or less than 0.5 μm.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device in which a channel stopper layer is formed by ion implantation after forming a LOCOS oxide film. In particular, the present invention relates to a method for manufacturing a semiconductor device capable of achieving both miniaturization of an element and improvement of an element withstand voltage.

[0002]

2. Description of the Related Art FIG. 3 is a cross-sectional view for explaining a conventional method for manufacturing a semiconductor device. The method of manufacturing this semiconductor device is described in FITL (Field Channel-Stopperion-Implantat).
This is a method of forming an element isolation region called ion through LOCOS. FITL is a method of forming a channel stopper layer by ion implantation after forming a LOCOS oxide film.

As shown in FIG. 3, first, a P-well 31 is formed in a silicon substrate (not shown) by introducing P-type impurity ions into the silicon substrate. Next, a LOCOS oxide film 34 is formed on the surface of the P well 1. Thereafter, a gate oxide film 32 is formed on a region of the silicon substrate where an element is to be formed by a thermal oxidation method. Next, a channel stopper 37 is formed in the P well 31 by implanting the impurity ions 6 through the LOCOS oxide film 34.

Thereafter, a polysilicon film (not shown) is deposited on the entire surface including the gate oxide film 32 by the CVD method.
By patterning the polysilicon film, a gate electrode (not shown) is formed on gate oxide film 32. Next, impurity ions are introduced into the source / drain regions 38 and 39 of the MOS transistor by performing ion implantation using the gate electrode as a mask. Thus, the structure of the element isolation portion is completed.

[0005]

In the above-described conventional method for manufacturing a semiconductor device, after the LOCOS oxide film 34 is formed, ion implantation is performed on the entire element isolation region or the entire surface including the region where the element is formed. 37 are formed. Therefore, the channel stopper 37 is formed shallow at the end of the LOCOS oxide film 34. When the concentration of the channel stopper 37 is increased in order to improve the inversion withstand voltage of the parasitic MOS transistor, the element isolation withstand voltage of the semiconductor device becomes higher than that of the channel stopper 3.
7 is determined by the breakdown voltage of the junction between the shallow end of the LOCOS oxide film 34 and the source / drain regions 38 and 39 of the transistor. For this reason, it is difficult to achieve both the inversion withstand voltage and the withstand voltage of this portion, and the element isolation withstand voltage of the semiconductor device becomes low. In the above-described manufacturing method, a fine element separation of about 0.7 μm
It was difficult to obtain an element isolation withstand voltage of 16 V or more.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a method of manufacturing a semiconductor device capable of achieving both miniaturization of an element and improvement in withstand voltage for element isolation. It is in.

[0007]

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a LOCOS oxide film on a surface of a semiconductor substrate, a step of forming a resist pattern on the LOCOS oxide film, and a step of forming a resist pattern on the LOCOS oxide film. Forming a channel stopper on the semiconductor substrate by implanting impurity ions using the pattern as a mask, wherein the length between the outer periphery of the resist pattern and the end of the LOCOS oxide film is 0.2 μm or more. .5 μm or less.

According to the method of manufacturing a semiconductor device, the LO
A resist pattern is formed on the COS oxide film, and impurity ions are implanted using the resist pattern as a mask. For this reason, the LOCOS oxide film becomes thinner.
The channel stopper located below the peripheral portion of the S oxide film can be formed lower than the conventional channel stopper. As a result, even if the thickness of the LOCOS oxide film becomes relatively thin due to the miniaturization of the element, the element isolation withstand voltage can be improved. Therefore, it is possible to achieve both miniaturization of the element and improvement of the element isolation withstand voltage.

In the method of manufacturing a semiconductor device according to the present invention, a first conductive type well and a second conductive type well adjacent to each other are formed on a semiconductor substrate.
Forming a conductive type well, and forming a LO on the surface of the semiconductor substrate on an adjacent portion between the first conductive type well and the second conductive type well;
A step of forming a COS oxide film, a step of forming a first resist pattern on the LOCOS oxide film above the second conductivity type well and a step of forming a first resist pattern on the second conductivity type well, and a step of LOCOS oxidation above the first conductivity type well Forming a second resist pattern on the film and on the first resist pattern; and implanting impurity ions using the first and second resist patterns as a mask to form a channel stopper in the first conductivity type well. And wherein the length between the outer periphery of the second resist pattern and the end of the LOCOS oxide film is 0.2 μm or more and 0.5 μm or less. Preferably, the first conductivity type well is a P well and the second conductivity type well is an N well.

According to the method of manufacturing a semiconductor device, the LO
The channel stopper located in the first conductivity type well below the peripheral portion of the LOCOS oxide film where the COS oxide film becomes thinner can be formed lower than the conventional channel stopper. As a result, even if the thickness of the LOCOS oxide film becomes relatively thin due to the miniaturization of the element, the element isolation withstand voltage can be improved.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention. FIG. 1 shows only a portion where an element isolation region is formed.

First, as shown in FIG. 1A, a P well 1 is formed on a silicon substrate (not shown) by introducing P-type impurity ions into the silicon substrate. Next, a silicon oxide film 2 having a thickness of about 13 nm is formed on the silicon substrate by a thermal oxidation method. This silicon oxide film 2
Is for relaxing the stress generated during LOCOS oxidation.

Thereafter, low pressure CVD is performed on the silicon oxide film 2.
160n thick by (Chemical Vapor Deposition) method
An about m silicon nitride film is formed. Next, a resist film is applied on the silicon nitride film, and the resist film is exposed and developed to form a resist pattern on the silicon nitride film. Thereafter, the silicon nitride film is etched using the resist pattern as a mask to form a mask film 3 made of a silicon nitride film on silicon oxide film 2. This mask film 3 is
An opening 3a is formed in a region where an OS oxide film is formed, and functions as an oxidation mask at the time of LOCOS oxidation.

Next, 1050 is performed using the mask film 3 as a mask.
By performing wet oxidation at 95 ° C. and 95%, FIG.
As shown in (b), the surface of the P well 1 has a thickness of 350 mm.
LOCOS oxide film 4 of about 0 to 5000 Å is formed. Thereafter, the mask film 3 is removed, and a gate oxide film 2a is formed by thermal oxidation on a region of the silicon substrate where an element is to be formed.

Thereafter, a resist film is applied on the entire surface including the LOCOS oxide film 4, and the resist film is exposed and developed, so that a thickness of 0.7 to
A resist pattern 5 of 1.1 μm (preferably 0.9 μm) is formed. The outer periphery of this resist pattern 5 and L
The length L between the end of the OCOS oxide film 4 and the end thereof is 0.2 to 0.2.
It is 0.5 μm. Since the end of the LOCOS oxide film 4 is a portion of about 0.1 μm inward from the outer end of the mask film 3a, when the length L is 0.2 μm, the end of the LOCOS oxide film 4 starts from the outer end of the mask film 3a. This means a range of 0.1 μm inward and 0.1 μm from the outer end of the mask film 3a toward the center of the LOCOS oxide film.

Next, using the resist pattern 5 as a mask
By implanting impurity ions 6 with high energy,
A channel stopper 7 is formed in the P well 1.
Here, the acceleration energy is about 250 to 350 KeV.
(Preferably 300 KeV) and a dose of 2 × 10¹²~
1 × 10¹³/ Cm^TwoDegree (preferably 4 × 10¹²/ C
m ^TwoB) (boron) is ion-implanted. this
The channel stopper 7 is located below the resist pattern 5.
Is formed at a shallow position in the P-well 1 of FIG.
Then, it is formed at a deeper position. In addition, this ion
At the time of implantation, control the threshold value of the MOS transistor
Is preferably performed continuously.
Thereby, the process can be simplified.

Thereafter, the resist pattern 5 is peeled off.
Next, a polysilicon film (not shown) is deposited on the entire surface including the gate oxide film 2a by the CVD method, and the polysilicon film is patterned to form the gate oxide film 2a.
A gate electrode (not shown) is formed thereon. Thereafter, ion implantation is performed using the gate electrode as a mask, thereby introducing impurity ions into the source / drain regions 8 and 9 of the MOS transistor as shown in FIG. Thus, the structure of the element isolation portion is completed.

According to the first embodiment, the LOCO
The channel stopper 7 located below the peripheral portion of the LOCOS oxide film 4 where the S oxide film 4 becomes thinner can be formed lower than the conventional channel stopper.
Therefore, the distance between the diffusion layers 8 and 9 of the source / drain regions and the channel stopper 7 under the peripheral portion of the LOCOS oxide film 4 can be made wider than that in the conventional case. Thereby, the concentration of the channel stopper 7 can be increased. As a result, even if the thickness of the LOCOS oxide film becomes relatively thin due to the miniaturization of the element,
Since the reverse breakdown voltage of the parasitic MOS transistor can be secured,
The element isolation withstand voltage can be improved. By using the above-described method, it is possible to secure a breakdown voltage of 15 to 16 V or more with a fine element isolation of about 0.7 μm. Therefore, it is possible to achieve both miniaturization of the element and improvement of the element isolation withstand voltage.

FIGS. 2A and 2B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

First, as shown in FIG. 2A, a P well 11 and an N well 12 are formed on a silicon substrate (not shown). Next, a LOCOS oxide film 15 having a thickness of about 450 nm is formed on and adjacent to the P well 11 and the N well 12. A well is formed by a self-aligned twin well method, and a gentle step is formed between the P well 11 and the N well 12. After this,
A gate oxide film 13 is formed on a region of the silicon substrate where an element is to be formed by a thermal oxidation method.

Next, a thick resist film is applied on the entire surface including the LOCOS oxide film 15, and the resist film is exposed and developed, so that the LOCOS oxide film 15 above the N well 12 and the gate oxide film are exposed. First on the membrane 13
Is formed. The thickness of the first resist pattern 16 is so large that no channel stopper is formed in the N well 12 when ion implantation for forming a channel stopper 21 described later is performed. Is 1.5 μm
More preferably, it is 1.8 μm or more.

Thereafter, a resist film is applied on the entire surface including the LOCOS oxide film 15 and the first resist pattern 16, and the resist film is exposed and developed, thereby
A second resist pattern 17 is formed on COS oxide film 15 and first resist pattern 16. This second
The thickness of the resist pattern 17 is smaller than that of the first resist pattern 16. The length L between the outer periphery of the second resist pattern 17 on the LOCOS oxide film 15 and the end of the LOCOS oxide film 15 is 0.
It is 2 to 0.5 μm.

Next, the first and second resist patterns 1
Impurity ions (for example, B) 19 using 6, 17 as a mask
Is implanted at a high energy to form a channel stopper 21 in the P well 11. The channel stopper 21 is formed at a shallow position in the P well 11 below the second resist pattern 17, and is formed at a deeper position in other regions. It is preferable that the ion implantation for controlling the threshold value of the MOS transistor be performed continuously during the ion implantation. Thereby, the process can be simplified.

Thereafter, the first and second resist patterns 1
6 and 17 are peeled off. Next, a gate electrode (not shown) is formed on the gate oxide film 13 and ion implantation is performed using the gate electrode as a mask, thereby forming the source / drain regions of the MOS transistor as shown in FIG. Impurity ions are introduced into 23 and 24. Thus, the structure of the element isolation portion is completed.

The same effects as those of the first embodiment can be obtained in the second embodiment. That is,
LOCOS oxide film 15 in which LOCOS oxide film 15 becomes thinner
The channel stopper 21 located in the P well 11 below the peripheral portion of the channel stopper can be formed lower than the conventional channel stopper. For this reason, the distance between the diffusion layer 23 in the source / drain region and the channel stopper 21 in the P well 11 below the peripheral portion of the LOCOS oxide film 15 can be made wider than that in the conventional case. As a result, even if the thickness of the LOCOS oxide film becomes relatively thin due to the miniaturization of the element, the element isolation withstand voltage can be improved. By using the method described above, 0.7
With a fine element isolation of about μm, it is possible to secure a breakdown voltage of 15 to 16 V or more. Therefore, it is possible to achieve both miniaturization of the element and improvement of the element isolation withstand voltage. In particular, it is suitable for miniaturization of a product having a high-speed logic section and a medium / high voltage circuit, for example, an EPLD (Electronic Programmable Logic Device).

The present invention is not limited to the above embodiment, but can be implemented with various modifications.

[0028]

As described above, according to the present invention, L
A resist pattern is formed on the OCOS oxide film, and impurity ions are implanted using the resist pattern as a mask. Therefore, it is possible to provide a method of manufacturing a semiconductor device capable of achieving both miniaturization of an element and improvement of an element isolation withstand voltage.

[Brief description of the drawings]

FIGS. 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIGS. 2A and 2B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view for explaining a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 P well 2 Silicon oxide film 2a Gate oxide film 3 Mask film 3a Opening 4 LOCOS oxide film 5 Resist pattern 6 Impurity ion 7 Channel stopper 8,9 Source / drain region 11 P well 12 N well 13 Gate oxide film 15 LOCOS oxidation Film 16 First resist pattern 17 Second resist pattern 19 Impurity ion 21 Channel stopper 23, 24 Source / drain region 31 P well 32 Gate oxide film 34 LOCOS oxide film 37 Channel stopper 38, 39 Source / drain region

Claims (3)

[Claims] A step of forming a LOCOS oxide film on a surface of the semiconductor substrate; a step of forming a resist pattern on the LOCOS oxide film; and implanting impurity ions using the resist pattern as a mask to form a channel in the semiconductor substrate. Forming a stopper, wherein the length between the outer periphery of the resist pattern and the end of the LOCOS oxide film is not less than 0.2 μm and not more than 0.5 μm. . 2. A step of forming a first conductivity type well and a second conductivity type well adjacent to each other on a semiconductor substrate, and forming a first conductivity type well and a second conductivity type well adjacent to each other on a surface of the semiconductor substrate on an adjacent portion between the first conductivity type well and the second conductivity type well. Forming a first resist pattern on the LOCOS oxide film above the second conductivity type well and on the second conductivity type well, and forming a LOCOS oxide film above the first conductivity type well. Forming a second resist pattern on the oxide film and the first resist pattern; and forming a channel stopper in the first conductivity type well by implanting impurity ions using the first and second resist patterns as a mask. Wherein the length between the outer periphery of the second resist pattern and the end of the LOCOS oxide film is 0.2 μm or more and 0.5 μm or less. The method of manufacturing a semiconductor device which is a bottom. 3. The method according to claim 2, wherein the first conductivity type well is a P well and the second conductivity type well is an N well.