JP2001291786A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of easily realizing a high speed operation without shortening the channel length of a transistor, and a method for manufacturing this semiconductor device. SOLUTION: In this method for manufacturing a semiconductor device having a bi-polar transistor and an MOS transistor, an N well 9 is formed in a silicon substrate 1, and a triple well 17 is formed in an N well 9, a gate oxide film 31 is formed on the surface of the N well 9, and a gate electrode 33 is formed on the gate oxide film 31, and an N+ diffusion layer 35 is formed in the N well 9, and an N+ diffusion layer 34 is formed in the triple well 17, and a P+ type diffusion layer (source diffusion layer) 36 is formed in the N well 9. In this case, the by-polar transistor is constituted of the N+ diffusion layers 34 and 35, the triple well 17, and the N well 9, and the MOS transistor is constituted of the gate electrode 33, the triple well 17, and the P+ type diffusion layer 36.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a bipolar transistor and a MOS transistor and a method of manufacturing the same. In particular, the present invention relates to a semiconductor device capable of easily performing high-speed operation without shortening a channel length of a transistor, and a method for manufacturing the same.

[0002]

2. Description of the Related Art In a conventional method of manufacturing a semiconductor device, a triple well is formed on a silicon substrate, and a CMOS is formed using the triple well. Hereinafter, a specific description will be given. 6A to 6C are cross-sectional views illustrating a method for forming a triple well.

First, as shown in FIG. 6A, a silicon oxide film 103 is formed on the surface of a P-type silicon substrate 101 by a thermal oxidation method, and the silicon oxide film 103 is located on a P-well formation region on the silicon oxide film 103. A nitride film pattern 105 is formed. Thereafter, an N-well 109 is formed in the P-type silicon substrate 101 by ion-implanting an N-type impurity 107 into the P-type silicon substrate 101 using the nitride film pattern 105 as a mask.

Next, the P-type silicon substrate 101 is thermally oxidized by using the nitride film pattern 105 as a mask.
As shown in FIG. 6B, the N-type
A thick oxide film 103a is formed on well 109. Thereafter, the nitride film pattern 105 is peeled off, and the P-type silicon substrate 10 is removed using the thick oxide film 103a as a mask.
By ion-implanting a P-type impurity 111 into
Type silicon substrate 101 has a P
A well 113 is formed.

Next, as shown in FIG. 6C, after the thick oxide film 103a and the silicon oxide film 103 are peeled off, the silicon oxide film 1 is formed on the entire surface of the P-type silicon substrate 101.
15 is formed by a thermal oxidation method. Thereafter, a resist film (not shown) is formed on the silicon oxide film 115, and a P-type impurity is ion-implanted into the N-well 109 of the P-type silicon substrate 101 using the resist film as a mask, thereby forming the N-well 109. Inside, a triple well 117 is formed.

Next, after removing the resist film, the silicon oxide film 115 is removed by etching. Thereafter, a gate oxide film is formed on the surface of the silicon substrate 101 by a thermal oxidation method. Next, a polycrystalline silicon film is deposited on the gate oxide film by a CVD method, and the polycrystalline silicon film is patterned, so that the first and second gates made of the polycrystalline silicon film are formed on the gate oxide film. An electrode is formed. The first gate electrode becomes a gate electrode of a P-channel MOS transistor, and the second gate electrode becomes a gate electrode of an N-channel MOS transistor.

Next, a P-type impurity is ion-implanted into the silicon substrate 101 so that the first well is formed in the N well 109.
And a second P-type diffusion layer. First and second P
The type diffusion layer becomes a source diffusion layer and a drain diffusion layer of a P-channel MOS transistor described later. Thereafter, an N-type impurity is ion-implanted into the silicon substrate 101,
First and second N-type diffusion layers are formed in the triple well 17. The first and second N-type diffusion layers serve as a source diffusion layer and a drain diffusion layer of an N-channel MOS transistor described later. In this manner, a CMOS including the P-channel MOS transistor formed in the N well 109 and the N channel MOS transistor formed in the triple well 117 is manufactured.

[0008]

By the way, a CMOS which is a conventional semiconductor device manufactured by the above-mentioned manufacturing method.
Because the DC current flowing between the power terminals is very small,
It is excellent in that it consumes very little current and has low power consumption, but its operating speed with respect to load capacity is limited. For this reason, a semiconductor device capable of high-speed operation is demanded. On the other hand, in order to increase the operation speed in CMOS, the channel length of the transistor must be shortened.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor device capable of easily operating at high speed without reducing the channel length of a transistor, and a method of manufacturing the same. Is to do.

[0010]

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a bipolar transistor and a MOS transistor, comprising the steps of forming a first conductivity type well on a semiconductor substrate. Forming a second conductivity type well in the first conductivity type well;
Forming a gate insulating film on the surface of the conductive well;
Forming a gate electrode on the gate insulating film; forming a first conductivity type first diffusion layer in the first conductivity type well; and forming a first conductivity type second diffusion layer in the second conductivity type well. Forming, and forming a second conductivity type diffusion layer in the first conductivity type well, wherein the bipolar transistor has a first conductivity type well, a second conductivity type well, and a first conductivity type first well. The MOS transistor includes a diffusion layer and a first conductivity type second diffusion layer, and the MOS transistor includes a gate electrode, a second conductivity type well, and a second conductivity type diffusion layer.

According to the method of manufacturing a semiconductor device, the MO
The drain diffusion layer of the S transistor can be formed by the second conductivity type well, and the bipolar transistor can be formed by using the second conductivity type well. Therefore, a semiconductor device capable of high-speed operation without shortening the channel length can be manufactured.

A semiconductor device according to the present invention includes a first conductivity type well formed on a semiconductor substrate and a second conductivity type well formed in the first conductivity type well and formed below one side surface of a gate electrode described below. A bipolar transistor comprising: a first conductivity type first diffusion layer formed in the first conductivity type well; and a first conductivity type second diffusion layer formed in the second conductivity type well. A gate electrode formed on the surface of the one-conductivity-type well via a gate insulating film; a second-conductivity-type diffusion layer formed in the first-conductivity-type well and formed under the other side surface of the gate electrode; MOS having two conductivity type wells
And a transistor.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1 to 4 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

First, as shown in FIG. 1, a silicon oxide film (not shown) is formed on the surface of a P-type silicon substrate 1 by a thermal oxidation method, and a P-well formation region (not shown) is formed on the silicon oxide film. 3) A nitride film (not shown) located on the upper surface is formed. Thereafter, an N well 9 is formed in the P-type silicon substrate 1 by ion-implanting an N-type impurity into the P-type silicon substrate 1 using the nitride film as a mask. Next, a thick oxide film (not shown) is formed on the N well 9 of the P-type silicon substrate 1 by performing thermal oxidation on the P-type silicon substrate 1 using the nitride film as a mask. After this,
The nitride film is removed, and a P-type impurity is ion-implanted into the P-type silicon substrate 1 using the thick oxide film as a mask, so that a P-well (not shown) adjacent to the N-well 9 is formed in the P-type silicon substrate 1. It is formed.

Next, after removing the thick oxide film and the silicon oxide film, a silicon oxide film 15 is formed on the entire surface of the P-type silicon substrate 1 by a thermal oxidation method. Thereafter, a resist film is formed on the silicon oxide film 15, and a P-type impurity is ion-implanted into the N-well 9 of the P-type silicon substrate 1 using the resist film as a mask. 17 are formed.

Thereafter, CVD is performed on the silicon oxide film 15.
A silicon nitride film is deposited by a (Chemical Vapor Deposition) method. Next, a resist film (not shown) is formed on the silicon nitride film, and etching is performed using the resist film as a mask, whereby a nitride film pattern 27 is formed on the silicon oxide film 15.

Next, after the resist film is peeled off, a resist film is applied on the silicon oxide film 15 and the nitride film pattern 27, and the resist film is exposed and developed, so that a One resist pattern 3 is formed. Thereafter, the first resist pattern 3 and the nitride film pattern 27 are used as a mask to ion-implant a P-type impurity 5 into the silicon substrate 1, as shown in FIG. P-type diffusion layer 1
1 and 12 are formed, and third and fourth P-type diffusion layers 13 and 14 are formed in the triple well 17. The conditions for the above ion implantation are, for example, using B as the P-type impurity 5,
The acceleration energy is 35 KeV and the dose is 9.00 × 1
It is set to 0 ¹³ cm ^-2 .

Next, as shown in FIG. 2, the first resist pattern 3 is peeled off, a resist film is applied on the silicon oxide film 15 and the nitride film pattern 27, and the resist film is exposed and developed. As a result, the second resist pattern 4 is formed on the silicon oxide film 15 and the nitride film pattern 27.
Is formed. Thereafter, the second resist pattern 4
And silicon substrate 1 using nitride film pattern 27 as a mask
The first to third N-type diffusion layers 18 to 20 are formed in the N-well 9 by ion-implanting the N-type impurity 6 into the N well 9. The ion implantation conditions at this time include, for example, N-type impurity 6.
Is used, the acceleration energy is 80 KeV, and the dose is 8.00 × 10 ¹² cm ⁻² .

Thereafter, after the second resist pattern 4 is peeled off, the silicon oxide film 1 is thermally oxidized using the nitride film pattern 27 as a mask as shown in FIG. The first to fifth LO
COS oxide films 21 to 25 are formed. The first LOCO
Under the S oxide film 21, a first P-type diffusion layer 11 and a first N-type diffusion layer 18 are formed, and the second LOCOS oxide film 2 is formed.
2, a second P-type diffusion layer 12 is formed, and a third L-type diffusion layer 12 is formed.
A third P-type diffusion layer 13 is formed below the OCOS oxide film 23, and a fourth P-type diffusion layer 13 is formed below the fourth LOCOS oxide film 24.
A third diffusion layer 14 and a second N-type diffusion layer 19 are formed, and a third N-type diffusion layer 2 is formed under the fifth LOCOS oxide film 25.
0 is formed.

Next, as shown in FIG. 4, the nitride film pattern 27 is peeled off, and the silicon oxide film 15 is removed by etching. Thereafter, a gate oxide film 31 is formed on the surface of the silicon substrate 1 by a thermal oxidation method. Next, C is formed on the gate oxide film 31 and the first to fifth LOCOS oxide films 21 to 25.
By depositing a polycrystalline silicon film by the VD method and patterning the polycrystalline silicon film, a gate electrode 33 made of the polycrystalline silicon film is formed on the gate oxide film 31.

Thereafter, a resist film is formed on the gate electrode 33 and the silicon substrate 1, and N-type impurities are ion-implanted using the resist film as a mask. Thus, an N ⁺ diffusion layer 34 is formed between the third and fourth LOCOS oxide films 23 and 24 in the triple well 17, and the fourth and fifth LOCOS oxide films 24 and 24 in the N well 9 are formed. An N ⁺ diffusion layer 35 is formed between the layers 25.

Next, after removing the resist film, N ⁺
A resist film is formed on the diffusion layers 34 and 35, and P-type impurities are ion-implanted using the resist film as a mask. Thus, the first and second LOCs in the N well 9
A P ⁺ type diffusion layer 36 is formed between the OS oxide films 21 and 22. Thus, a bipolar transistor having the emitter 34 and the collectors 9 and 35 and a MOS transistor having the gate electrode 33, the source diffusion layer 36 and the drain diffusion layer 17 are manufactured.

FIG. 5 is a circuit diagram of the semiconductor device shown in FIG. This semiconductor device includes an NPN bipolar transistor 41 and a P-channel MOS transistor 42. The emitter E of the bipolar transistor 41 is connected to one electrode of a capacitor, and the other electrode of the capacitor is connected to the ground potential. Bipolar transistor 4
1 is connected to the source S of the MOS transistor 42, and the base B of the bipolar transistor 41 is connected to M
It is connected to the drain D of the OS transistor 42.

According to the above-described embodiment, a drain diffusion layer of a P-channel MOS transistor is formed using a triple well by a process similar to the conventional method of manufacturing a semiconductor device using a triple well to form a CMOS. , An NPN bipolar transistor can be formed using a triple well. Therefore, a semiconductor device capable of high-speed operation without shortening the channel length can be manufactured. Further, the number of steps is equal to the triple well process.

The present invention is not limited to the above embodiment, but can be implemented with various modifications. For example,
In the semiconductor device according to the above-described embodiment, it is possible to use a semiconductor device having a conductivity type opposite to each conductivity type.

[0026]

As described above, according to the present invention, M
The drain diffusion layer of the OS transistor is formed of a second conductivity type well, and a bipolar transistor is formed using the second conductivity type well. Therefore, it is possible to provide a semiconductor device capable of easily performing high-speed operation without reducing the channel length of a transistor, and a method for manufacturing the semiconductor device.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the present invention, showing a step subsequent to FIG. 1;

FIG. 3 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the present invention, showing a step subsequent to FIG. 2;

FIG. 4 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the present invention, which shows the step subsequent to FIG. 3;

FIG. 5 is a circuit diagram of the semiconductor device shown in FIG. 4;

FIGS. 6A to 6C are cross-sectional views illustrating a method for forming a triple well.

[Explanation of symbols]

Reference Signs List 1 P-type silicon substrate 3 First resist pattern 4 Second resist pattern 5 P-type impurity 6 N-type impurity 9 N-well 11 to 14 First to fourth P-type diffusion layer 15 Silicon oxide film 17 Triple well (drain) Diffusion layer) 18 to 20 First to third N-type diffusion layers 21 to 25 First to fifth LOCOS oxide films 27 Nitride film patterns 31 Gate oxide films 33 Gate electrodes 34 N ⁺ Diffusion layers (emitters) 35 N ⁺ Diffusion layer (collector) 36 P ⁺ type diffusion layer (source diffusion layer) 41 NPN bipolar transistor 42 P channel MOS transistor 101 P type silicon substrate 103 silicon oxide film 103 a thick oxide film 105 nitride film pattern 107 N type impurity 109 N well 111 P-type impurity 113 P well 115 Silicon oxide film 117 Triple well Le

Continued on the front page F term (reference) 5F003 BB01 BB02 BC01 BC02 BG03 BJ15 BM01 5F048 AA05 AB05 AB07 AC07 BA01 BB05 BC03 BE02 BE03 BG12 BH07 CA01 5F082 AA06 BA04 BA27 BA38 BA47 BC01 BC09 EA10 GA04

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor device having a bipolar transistor and a MOS transistor, comprising: forming a first conductivity type well in a semiconductor substrate; and forming a second conductivity type well in the first conductivity type well. Forming a gate insulating film on the surface of the first conductivity type well; forming a gate electrode on the gate insulating film; and forming a first diffusion layer in the first conductivity type well. Forming a first conductivity type second diffusion layer in the second conductivity type well, and forming a second conductivity type diffusion layer in the first conductivity type well. The bipolar transistor is a well of the first conductivity type,
The MOS transistor includes a conductive type well, a first conductive type first diffusion layer, and a first conductive type second diffusion layer, and the MOS transistor includes a gate electrode, a second conductive type well, and a second conductive type diffusion layer. A method for manufacturing a semiconductor device. A first conductivity type well formed on the semiconductor substrate; a second conductivity type well formed in the first conductivity type well and formed below one side surface of a gate electrode described below; A bipolar transistor comprising: a first conductivity type first diffusion layer formed in a well; a first conductivity type second diffusion layer formed in a second conductivity type well; and a surface of the first conductivity type well. A gate electrode formed via a gate insulating film, a second conductivity type diffusion layer formed in the first conductivity type well and formed under the other side surface of the gate electrode, and the second conductivity type well. A semiconductor device comprising: a MOS transistor having the following.