JPH06132541A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a semiconductor device and a manufacture of the device, in which the number of processes can be decreased so that it is possible to reduce a manufacturing cost to obtain a low-cost semiconductor device. CONSTITUTION:A second semiconductor region 2 of second conductive type is formed in a first semiconductor region 1 of undoped or first conductive type, and a first diffused source layer 9 of second conductive type and a first diffused drain layer 10 of DSA structure for forming a transistor are formed in the first semiconductor region 1. Further, a second diffused source layer 11 of a first conductive type and a second diffused drain layer 12 of DSA structure for constituting the transistor are formed in the second semiconductor region 2, and a bipolar transistor is formed from the second semiconductor region 2 and the second diffused drain layer 12 of DSA structure.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, it can be applied to a bipolar transistor in a CMOS type nonvolatile semiconductor memory device such as an EPROM or a flash memory. The present invention relates to a semiconductor device capable of reducing the manufacturing cost by reducing the number of steps and a manufacturing method thereof.

In recent years, B has the advantages of both low power consumption of CMOS devices and load driving capability of bipolar devices.
The development of i-CMOS technology has begun and is beginning to draw attention.

[0003]

2. Description of the Related Art FIGS. 6 and 7 are views for explaining a conventional method of manufacturing a semiconductor device. The illustrated example is applied to a method for manufacturing a Bi-CMOS integrated circuit. 6 and 7,
Reference numeral 31 is, for example, a p ⁻ type substrate such as Si, 32 is a silicon oxide film such as SiO ₂ formed by thermally oxidizing the substrate 31, and 33 is an opening formed by etching the silicon oxide film 32. Numeral 34 is, for example, an n ⁺ type buried region formed in the substrate 31 through the opening 33. Next, 35 is an epitaxial layer formed on the buried region 34,
36 and 37 are n wells and p wells formed in the epitaxial layer 35, 38 is a field oxide film such as SiO ₂ formed by selective oxidation of the epitaxial layer 35, and 39 is in the n well 36. Formed n ⁺ type buried region
It is an n ⁺ -type region that serves as an extraction electrode of 34. Then 40
Is a gate oxide film such as SiO ₂ formed by oxidizing the epitaxial layer 35 between the field oxide films 38, 41 is a gate electrode such as poly Si formed in a predetermined region on the gate oxide film 40, 42 Is a p ⁺ type source / drain diffusion layer formed in the n well 36 in the PMOS region, and 43 is N
An external base diffusion layer formed in the n well 36 in the PN bipolar region, and 44 an n ⁺ type source / drain diffusion layer formed in the p well 37 in the NMOS region. 45 and 46 are n ⁺ type emitter diffusion layers and active base diffusion layers respectively formed in the n well 36 of the NPN bipolar region, 47 is an interlayer insulating film such as PSG, and 48 is an interlayer insulating film. 47 is a contact hole formed by etching, and 49 is an n ⁺ type region through this contact hole 48.
39, an emitter diffusion layer 45, an external base diffusion layer 43, source / drain diffusion layers 42, 44, and the like, which are wiring layers made of Al or the like.

Next, a method of manufacturing the semiconductor device will be described. Here, of the manufacturing process of the Bi-CMOS integrated circuit, the bipolar process will be focused and described. First,
As shown in FIGS. 6A and 6B, the p-type Si substrate 31 is thermally oxidized to deposit a silicon oxide film 32 having a thickness of about 1 μm, and only the portion where the n ⁺ -type buried region is formed is selectively oxidized with silicon. The film 32 is removed to form an opening 33, and Sb is doped into the substrate 31 through the opening 33 by thermal diffusion to form an n ⁺ -type buried region 34 in the substrate 31. Next, FIG. 6 (c)
, The silicon oxide film 32 is removed, and
Epitaxial growth is performed to form an epitaxial layer 35. At this time, if the epitaxial layer 35 is n-type doped, it can be used as a collector, and if it is p-type doped, the following n-well can be used as a collector. Then, in the epitaxial layer 35, an n well 36 and ap well 37 are formed.
Formation.

Next, as shown in FIG. 7 (d), the epitaxial layer 35 is selectively oxidized to form a field oxide film 38, and n ⁺ which becomes an extraction electrode of the n ⁺ type buried region 34 in the n well 36 is formed. After forming the mold region 39, the field oxide 38
The epitaxial layer 35 in between is oxidized to form a gate oxide film 40. Then, as shown in FIG. 7E, channel ion implantation for adjusting the threshold of the MOS transistor is performed to form a gate electrode 41 in a predetermined region on the gate oxide film 40, and then p ^{+ + is performed} by ion implantation or the like. Forming the p ⁺ -type external base diffusion layer 43 at the same time as forming the n-type source / drain diffusion layer 42 and forming the n ⁺ -type source / drain diffusion layer 44 by ion implantation or the like, and simultaneously forming the n ⁺ -type emitter diffusion layer 45. , A p-type active base diffusion layer 46 is separately formed in the n-well 36 in the NPN bipolar transistor region by ion implantation or the like.
To form.

Then, an interlayer insulating film 47 such as PSG is formed on the entire surface, the interlayer insulating film 47 is etched to form a contact hole 48, and an n ⁺ type region 39 and an emitter diffusion layer 45 are formed through the contact hole 48. By forming the wiring layer 49 of Al or the like so as to contact the external base diffusion layer 43 and the source / drain diffusion layers 42, 44, etc., a semiconductor device as shown in FIG. 7F can be obtained.

[0007]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the method of manufacturing the device, the NPN bipolar transistor region is used.
External base diffusion layer 43 and emitter diffusion in n-well 36 in the region
In addition to forming the layer 45 and the active base diffusion layer 46, n⁺Mold area
39 must be formed, and the p ⁺Type
Source / drain diffusion layer 42 and NMOS n⁺Type sauce / do
The rain diffusion layer 44 and the rain diffusion layer 44 must be formed in separate steps.
The number of processes is very large, leaving a problem in terms of manufacturing cost.
Was there.

When performing high speed writing in a flash memory, a method is known in which the drain portion of the memory cell transistor has a DSA structure.
In the case of such a structure, an impurity of different conductivity type must be ion-implanted into the drain portion twice. In such a case, the number of steps is further increased, so that the above-mentioned problem becomes remarkable. Therefore, it is an object of the present invention to provide a semiconductor device and a manufacturing method thereof, which can reduce the manufacturing cost by reducing the number of steps and can obtain an inexpensive semiconductor element.

[0009]

In order to achieve the above object, a semiconductor device according to the present invention has a second semiconductor region of a second conductivity type formed in a first semiconductor region of an undoped or first conductivity type. A first source diffusion layer of a second conductivity type forming a transistor and a first drain diffusion layer of a DSA structure are formed in the first semiconductor region, and a first transistor forming a transistor is formed in the second semiconductor region. A conductive type second source diffusion layer and a DSA structure second drain diffusion layer are formed,
A bipolar transistor is formed from the second semiconductor region and the second drain diffusion layer having the DSA structure.

The method of manufacturing a semiconductor device according to the present invention is the same as the step of forming a second semiconductor region of a second conductivity type in a first semiconductor region of an undoped or first conductivity type in order to achieve the above object. Using the mask pattern of
A step of forming a first diffusion layer of a first conductivity type forming a DSA structure in the second semiconductor region, and then using the same mask pattern, a second diffusion layer of the second conductivity type in the first semiconductor region. Forming a source diffusion layer, forming a second diffusion layer of the second conductivity type in the first diffusion layer of the first semiconductor region to form a first drain diffusion layer of a DSA structure, And a step of forming a second diffusion layer of the second conductivity type in the first diffusion layer of the second semiconductor region to form a second drain diffusion layer having a DSA structure.

In the present invention, the first conductivity type source diffusion layer of the second semiconductor region is the first conductivity type first diffusion layer.
The diffusion layer may be formed before the formation of the diffusion layer, simultaneously with the formation of the diffusion layer, or after the formation of the DSA structure. In order to achieve the above object, a semiconductor device according to the present invention has a first conductivity type first diffusion layer serving as a base formed in a second conductivity type semiconductor region serving as an emitter or a collector. A second diffusion layer of a second conductivity type serving as a collector or an emitter is formed therein, and a third diffusion layer of a first conductivity type serving as a base is formed so as to be adjacent to the first diffusion layer. It is a thing.

[0012]

In the present invention, as shown in FIGS. 1 and 2 of the embodiment described later, the drain diffusion layer 10 of the DSA structure of the n-channel memory cell transistor and the drain diffusion layer 12 of the DSA structure of the p-channel MOS transistor are formed by the same resist. Patterns 21 and 22 are used to form simultaneously. Moreover, NPN
N-type bipolar transistor also serves as the drain diffusion layer 12 of the DSA structure of the p-channel MOS transistor.
^The p-type MO layer is composed of a ⁺ type diffusion layer 12b and ap ⁺ type diffusion layer 12a, an n well 2 and an n ⁺ type diffusion layer 13.
When forming the S transistor, an NPN bipolar transistor is also formed at the same time. Therefore, the number of steps can be extremely reduced as compared with the case where the source / drain of the conventional p-channel transistor and the n-channel transistor are separately formed, and the case where the bipolar transistor has a complicated structure, and the manufacturing cost can be reduced. It can be significantly reduced.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing the structure of a semiconductor device according to the first embodiment of the present invention, which is applied to a Bi-CMOS flash memory having a DSA structure. In FIG.
Reference numeral 1 denotes, for example, a p ⁻ -type substrate such as Si, 2 denotes, for example, an n ⁻ -type n well formed in the p ⁻ -type substrate 1, and 3
Is a field oxide film such as SiO ₂ which becomes an element isolation region, and 4 is a gate oxide film such as SiO ₂ . Then
Reference numerals 5 to 7 are a gate electrode made of poly-Si or the like, a floating gate made of poly-Si or the like, a control gate made of poly-Si or the like, and 8 is an interlayer film such as SiO ₂ . Then, 9 p ^- is a source diffusion layer of the n ⁺ -type formed on the mold substrate 1, 10 p ^- a drain diffusion layer of the formed on the mold substrate 1 DSA structure, the drain of the DSA structure Diffusion layer 10
Consists the n ⁺ -type diffusion layer 10b formed on the p ⁺ -type diffusion layer 10a Toko of p ⁺ -type diffusion layer 10a.

[0014] Then, 11 the n ^- is a source diffusion layer of the p ⁺ -type formed in the mold n-well 2, 12 the n ^- a drain diffusion layer of the formed in the mold n-well 2 DSA structure,
The drain diffusion layer 12 of this DSA structure is ap ⁺ type diffusion layer 12a.
And the n ⁺ type diffusion layer 12 formed in the p ⁺ type diffusion layer 12a
It consists of b and. Next, 13 is an n ^- type n well 2
An n ⁺ -type diffusion layer formed inside the n ⁺ -type diffusion layer
13 and the n ⁻ type n well 2 also serve as a collector diffusion layer,
The p ⁺ type diffusion layer 12a also serves as a base diffusion layer, and the n ⁺ type diffusion layer 12b also serves as an emitter diffusion layer, which form an NPN bipolar transistor. Further, 14 is an interlayer insulating film such as PSG, 15 is a contact hole in which each of the diffusion layers 9 to 13 is exposed, and 16 is in contact with each of the diffusion layers 9 to 13 through the contact hole 15. It is a wiring layer formed of Al or the like. In addition,
A indicates an n-channel memory cell transistor region, and 13 indicates a p-channel MOS transistor and NPN bipolar transistor region.

Next, FIG. 2 is a diagram for explaining a method of manufacturing a semiconductor device according to the first embodiment of the present invention. 2, the same reference numerals as those in FIG. 1 indicate the same or corresponding portions, and 21 is p.
^The resist pattern 22 has an opening 21a for forming the ⁺ type diffusion layer 10a and the p ⁺ type diffusion layer 12a, and 22 is n ^+.
The resist pattern has an opening 22a for forming the type diffusion layer 10b, the source diffusion layer 9, the n ⁺ type diffusion layer 12b, and the n ⁺ type diffusion layer 13, and 23 forms the p ⁺ type source diffusion layer 11. This is a resist pattern having an opening 23a for the purpose.

Next, the method of manufacturing the semiconductor device
explain. Here, each of the diffusion layers 9 to 9 which is a feature of the present invention
A method of forming 13 will be specifically described. First, FIG.
As shown in (a), p^-Type Si group
N in board 1 ^-Type n-well 2 is formed, LOCOS method, etc.
Selectively oxidizes the Si substrate 1 to form an element isolation region.
After forming the field oxide film 3, the Si substrate 1 is thermally oxidized.
Then, the gate oxide film 4 is formed. Then, the CVD method
A gate made of poly-Si is formed on the gate oxide film 4 by RIE or the like.
The gate electrode 5 and the floating gate 6 are formed and
Poly-Si control gate 7 on the gate 6
And SiO₂The interlayer film 8 is formed.

Next, as shown in FIG. 2B, a resist is applied on the entire surface, and the resist is patterned by exposure and development so that the drain portions of the memory cell transistor portion and the p-channel MOS transistor portion are opened. Opening 21
After the resist pattern 21 having a is formed, the resist pattern 21 is used to introduce impurities into the substrate 1 in the opening 21a by ion implantation with impurities such as boron (B) to form the p ⁺ -type diffusion layer 10a. Simultaneously with the formation of p., The p ⁺ type diffusion layer 12a is formed.

Next, as shown in FIG. 2C, the resist
After removing the pattern 21, apply resist again on the entire surface
The source of the memory cell transistor is exposed and developed.
/ Drain section and p-channel MOS transistor section drain
Pattern the resist so that the in and collector parts are open.
To form a resist pattern 22 having an opening 22a.
After forming the resist pattern 22, arsenic (A
In the opening 22a by ion implantation with impurities such as
By introducing impurities into the substrate 1 of⁺Type source diffusion layer
At the same time that 9 is formed, p⁺N in the mold diffusion layer 10a⁺Mold expansion
Form the diffusion layer 10b to form the drain diffusion layer 10 of the DSA structure.
And at the same time p⁺N in the mold diffusion layer 12a ⁺Type diffusion layer
12b is formed to form a drain diffusion layer 12 having a DSA structure
At the same time, the collector is pulled out into the n-well 2.
Service n⁺The mold diffusion layer 13 is formed.

Next, as shown in FIG. 2D, after removing the resist pattern 22, the resist is applied again on the entire surface, and the resist is exposed and developed so that the source portion of the p-channel transistor portion is opened. After patterning to form the resist pattern 23 having the opening 23a, the resist pattern 23 is used to introduce impurities into the substrate 1 in the opening 23a by ion implantation with impurities such as boron (B), A p ⁺ type source diffusion layer 11 is formed.

Then, the resist pattern 23 is removed to form a PSG interlayer insulating film 14 having a contact hole 15 exposing the diffusion layers 9 to 13, and then the diffusion layers 9 to 13 are formed through the contact hole 15. A to contact
By forming the 1 wiring layer 16, a semiconductor device as shown in FIG. 1 can be obtained. Needless to say, the heat treatment step after ion implantation for forming the diffusion layers 9 to 13 may be appropriately performed in the next step.

As described above, in this embodiment, the drain diffusion layer 10 of the DSA structure of the n-channel memory cell transistor is used.
And the drain diffusion layer 12 of the DSA structure of the p-channel MOS transistor are simultaneously formed by using the same resist patterns 21 and 22. Moreover, the NPN type bipolar transistor is composed of the n ⁺ type diffusion layer 12b and the p ⁺ type diffusion layer 12a which also serve as the drain diffusion layer 12 of the DSA structure of the p channel MOS transistor, and the n well 2 and the n ⁺ type diffusion layer 13. Therefore, when forming a p-channel MOS transistor, an NPN bipolar transistor is also formed at the same time. Therefore, the number of steps can be extremely reduced as compared with the case where the source / drain of the conventional p-channel transistor and the n-channel transistor are formed separately, and the case of the bipolar transistor having a complicated structure. Therefore, the manufacturing cost can be significantly reduced, and an inexpensive semiconductor element can be obtained.

By the way, when the flash memory is used in a decoder, the flash memory requires a high voltage and a pressure adjustment when writing. At this time, when a high voltage is applied from the power source, in the conventional CMOS, the source / drain diffusion layer is biased in the forward direction between the substrate and the operation becomes unstable. Therefore, in the conventional case, as shown in FIG. As shown in the section M, a backflow preventing transistor was required. On the other hand, in the present invention, as can be seen from FIGS. 3B and 3C, the output has a capacitance and the bipolar transistor is
When it is N, it is charged, and it has a high current drive capability and can be charged rapidly. When the potential at the other end of the capacitor is raised in this state, the output also rises accordingly. At this time, the bipolar transistor is reverse-biased between the emitter and base, and it is possible to prevent current from flowing. It is possible to omit the transistor. Therefore, the booster circuit can be easily formed.

In the first embodiment, as shown in FIG. 4, the NPN bipolar transistor is the n ⁺ type diffusion layer 12b and the p ⁺ type diffusion layer 12a which also serve as the drain diffusion layer 12 of the DSA structure of the P channel MOS transistor. And an n well 2 and an n ⁺ type diffusion layer 13, and a P channel MO
Although the case where the S transistor is formed at the same time as the formation of the S transistor has been described, in the present invention, as shown in the second embodiment of FIG. 5, an NPN bipolar transistor is formed in the n well 2 serving as the collector and the p ⁺ type serving as the base is formed. the diffusion layer 12b is formed, the p ⁺ -type diffusion layer 12b emitter electrode lead-out n ⁺ -type diffusion layer 12b serving as the emitter in the form, the base electrode lead for p-type so as to be adjacent to the p ⁺ -type diffusion layer 12b The diffusion layer 25 may be formed, and then the n ⁺ -type diffusion layer 13 for drawing out the collector electrode may be formed in the n well 2. This forming method is the same as that of the first embodiment if the p-type diffusion layer 25 is made to correspond to the source diffusion layer 11 of the first embodiment without providing the gate electrode 5 in the first embodiment.

In the above embodiment, the source diffusion layer 11 is formed after the DSA structure is formed. However, the present invention is not limited to this, and the p ⁺ type diffusion layer 10 is not limited to this.
a and 12a may be formed at the same time when they are formed, or p ⁺
It may be formed before forming the mold diffusion layers 10a and 12a.

[0025]

According to the present invention, the number of steps can be reduced, the manufacturing cost can be reduced, and an inexpensive semiconductor element can be obtained.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a method of manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating an effect when the semiconductor device of the present invention is used in a decoder of a flash memory.

FIG. 4 is a cross-sectional view showing a structure of a p-channel transistor portion and an NPN bipolar transistor portion according to the first embodiment of the present invention and an equivalent circuit diagram thereof.

FIG. 5 is a cross-sectional view showing a structure of a bipolar transistor according to a second embodiment of the present invention and its equivalent circuit diagram.

FIG. 6 is a diagram illustrating a method of manufacturing a conventional semiconductor device.

FIG. 7 is a diagram illustrating a method for manufacturing a conventional semiconductor device.

[Explanation of symbols]

1 substrate 2 n-well 3 field oxide film 4 gate oxide film 5 gate electrode 6 floating gate 7 control gate 8 interlayer film 9 source diffusion layer 10 drain diffusion layer 10a p ⁺ type diffusion layer 10b n ⁺ type diffusion layer 11 source diffusion layer 12 Drain diffusion layer 12a p ⁺ type diffusion layer 12b n ⁺ type diffusion layer 13 n ⁺ type diffusion layer 14 Interlayer diffusion layer 15 Contact hole 16 Wiring layer 21 Resist pattern 21a Opening 22 Resist pattern 22a Opening 23 Resist pattern 23a Opening 25 p-type diffusion layer

Claims (4)

[Claims] 1. A second semiconductor region (2) of second conductivity type in a first semiconductor region (1) of undoped or first conductivity type.
And a first source diffusion layer (9) of a second conductivity type and a first drain diffusion layer (10) of a DSA structure which form a transistor are formed in the first semiconductor region (1),
A second source diffusion layer (11) of the first conductivity type and a second drain diffusion layer (12) of the DSA structure that form a transistor are formed in the second semiconductor region (2), and the second drain diffusion layer (12) of the DSA structure is formed. A semiconductor device comprising a bipolar transistor formed from a semiconductor region (2) and a second drain diffusion layer (12) having the DSA structure. 2. A second semiconductor region (2) of the second conductivity type in a first semiconductor region (1) of the undoped or first conductivity type.
And the step of forming the first and second masks using the same mask pattern (21).
A step of forming a first diffusion layer (10a, 12a) of the first conductivity type forming a DSA structure in the second semiconductor region (1, 2), and then using the same mask pattern (22) A second conductivity type source diffusion layer (9) in the first semiconductor region (1).
And forming a second diffusion layer (10) of the second conductivity type in the first diffusion layer (10a) of the first semiconductor region (1).
b) to form a first drain diffusion layer (1
0) is formed, and further the first semiconductor region of the second semiconductor region (2) is formed.
Of the second conductivity type second diffusion layer (12a)
b) to form a second drain diffusion layer (1
And a step of forming 2). 3. The first conductivity type source diffusion layer (11) of the second semiconductor region (2) is formed before the formation of the first conductivity type first diffusion layer (10a, 12a). 3. The method for manufacturing a semiconductor device according to claim 2, wherein the semiconductor device is formed at the same time, or is formed after the DSA structure is formed. 4. A first conductive type semiconductor region (2) serving as an emitter or collector and a second conductive type first region serving as a base.
Diffusion layer (12a) is formed, and the first diffusion layer (12a) is formed.
A second diffusion layer (12b) of the first conductivity type serving as a collector or an emitter is formed in the third diffusion layer of the second conductivity type serving as a base so as to be adjacent to the first diffusion layer (12a). A semiconductor device comprising a layer (25) formed.