JPS60128656A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60128656A JPS60128656A JP58236162A JP23616283A JPS60128656A JP S60128656 A JPS60128656 A JP S60128656A JP 58236162 A JP58236162 A JP 58236162A JP 23616283 A JP23616283 A JP 23616283A JP S60128656 A JPS60128656 A JP S60128656A
- Authority
- JP
- Japan
- Prior art keywords
- drain
- source
- polycrystalline
- metal
- silicide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims 5
- 229910052751 metal Inorganic materials 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 19
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 19
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 19
- 239000012535 impurity Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 230000005669 field effect Effects 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 18
- 238000000034 method Methods 0.000 abstract description 9
- 230000010354 integration Effects 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 229910052785 arsenic Inorganic materials 0.000 abstract description 2
- 238000005530 etching Methods 0.000 abstract description 2
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 2
- 230000004913 activation Effects 0.000 abstract 2
- 150000002500 ions Chemical class 0.000 abstract 2
- 230000000717 retained effect Effects 0.000 abstract 1
- 238000006243 chemical reaction Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 239000012808 vapor phase Substances 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 235000006732 Torreya nucifera Nutrition 0.000 description 1
- 244000111306 Torreya nucifera Species 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
- H01L29/41783—Raised source or drain electrodes self aligned with the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の利用分野〕
本発明は高速化、高集積化が可能な絶縁ゲ−１・電界効
果トランジスタ（以下ＭＯ８＋・ランジスタと略記する
）に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an insulated gate field effect transistor (hereinafter abbreviated as MO8+ transistor) which can be operated at high speed and highly integrated.
Ｍｏ８）−ランジスタの性能改善のためにはチャネル長
を短くするとともに、ソース、ドレイン及びゲート電極
の寄生抵抗を減らすことが重要である。このため、第１
図に示されているように、ソース、ドレイン拡散層４の
上に選択的にタングステン等の金属やシリサイド６を形
成することが試みられている（例えば特願昭５８−５５
０７５号に報告されている）。しかし、この方法では金
属又はシリサイド層６が選択的にソース、ドレイン上に
形成された時、金属又はシリサイド層が横方向にも化学
反応で入り込み、ソース、トレイン間が短絡し、Ｃしま
うという問題点が生じる。さらに、金属又はシリサイド
層６とソース、トレイン層４との接触抵抗を低減するた
めには、ソース、ドレイン層４の不純物濃度は高くなけ
ればならず、このため、ソース、ドレイン拡散層の不純
物濃度を制御してＭｏ８＋−ランジスタのトレイン耐圧
を向上させるということが難しくなる。従って、第１図
に示すような従来構造でＭｏ８＋−ランジスタを高速化
、高集積化するには限界があった。In order to improve the performance of Mo8)-transistors, it is important to shorten the channel length and reduce the parasitic resistance of the source, drain, and gate electrodes. For this reason, the first
As shown in the figure, attempts have been made to selectively form metal such as tungsten or silicide 6 on the source and drain diffusion layers 4 (for example, Japanese Patent Application No. 58-55
075). However, this method has the problem that when the metal or silicide layer 6 is selectively formed on the source and drain, the metal or silicide layer also penetrates in the lateral direction due to chemical reaction, causing a short circuit between the source and the train, resulting in C. A point occurs. Furthermore, in order to reduce the contact resistance between the metal or silicide layer 6 and the source/train layer 4, the impurity concentration of the source/drain layer 4 must be high. It becomes difficult to improve the train withstand voltage of the Mo8+- transistor by controlling it. Therefore, there is a limit to increasing the speed and integration of the Mo8+- transistor with the conventional structure shown in FIG.
本発明は上記従来技術の問題点を改善し、高速で高集積
化が可能なＭｏＳトランジスタ構造を提供するにある。The present invention aims to improve the problems of the prior art described above and to provide a MoS transistor structure that is capable of high speed and high integration.
本発明では上記目的を達成するために、ＭＯＳトランジ
スタの低濃度ソース、ドレイン上に多結晶シリコンを自
己整合的に形成し、さらに上記多結晶シリコン上に自己
整合的に低抵抗金属又はシリサイド層を形成することを
特徴としている。In order to achieve the above object, the present invention forms polycrystalline silicon in a self-aligned manner on the low concentration source and drain of a MOS transistor, and further forms a low resistance metal or silicide layer on the polycrystalline silicon in a self-aligned manner. It is characterized by the formation of
以下、本発明の詳細な説明を実施例を用いて行なう。 Hereinafter, the present invention will be explained in detail using examples.
第２図は高速で高集積化が可能な本発明によるＭＯＳト
ランジスタの断面構造図である。同図に合深さが１０〜
ｓｏｏｎｍのｎ形ソース、ドレイン層１１があり、さら
にシリコン基板表面上には５〜５０ｎｍの薄いゲート絶
縁膜１４と多結晶シリコンや金属或いはシリサイドによ
るグー１〜？！！極８が存在する。また、低濃度ソース
、ドレイン１１上には高濃度のｎ形多結晶シリコン１２
があり、さらにこの多結晶シリコン１２上には低抵抗の
タングステン等の金属或いはシリサイド１′３が形成さ
れている５本構造を有するＭＯ８Ｉ〜ランジスタの特徴
は以下の通りである。FIG. 2 is a cross-sectional structural diagram of a MOS transistor according to the present invention, which allows high speed and high integration. In the same figure, the depth of fit is 10~
There is an n-type source/drain layer 11 of soon-to-nm type, and furthermore, on the surface of the silicon substrate, there is a thin gate insulating film 14 of 5 to 50 nm and a layer 1-?of polycrystalline silicon, metal, or silicide. ! ! There are 8 poles. Further, on the low concentration source and drain 11, a high concentration n-type polycrystalline silicon 12 is provided.
Further, on the polycrystalline silicon 12, a low resistance metal such as tungsten or silicide 1'3 is formed.The characteristics of the MO8I transistor having a five-layer structure are as follows.
１）ソース、ドレイン領域１１は不純物濃度が低いため
、ドレイン領域にも空乏層が延びてきて、ゲート絶縁膜
下に形成されるチャネル領域の電界が緩和されてソース
、ドレイン間耐圧が向上する。このため、短チャネルＭ
Ｏ８）−ランジスタで問題となるホットキャリア・（高
エネルギーを有する電子又は正孔）がゲート絶縁膜に注
入されることがなく、Ｍ９Ｓｌ−ランジスタ動作上の信
頼度が大幅に向上する。1) Since the impurity concentration in the source and drain regions 11 is low, a depletion layer extends to the drain region as well, and the electric field in the channel region formed under the gate insulating film is relaxed, improving the breakdown voltage between the source and drain. Therefore, the short channel M
Hot carriers (electrons or holes with high energy), which are a problem in O8) transistors, are not injected into the gate insulating film, and the operational reliability of the M9Sl transistor is greatly improved.
２）ソース、ドレイン１１の上には低抵抗の金属やシリ
サイド層１３が形成されているため、ソース、ドレイン
抵抗が小さくなり、ＭＯＳトランジスタの相互コンダク
タンスの劣化がなく、高速化が可能となる。2) Since a low-resistance metal or silicide layer 13 is formed on the source and drain 11, the source and drain resistances are reduced, the mutual conductance of the MOS transistor does not deteriorate, and high speed operation is possible.
３）低抵抗金属或いはシリサイド層１３は低濃度ソース
、ドレイン領域１１には直接接することなく、高濃度多
結晶シリコン１２を介して接している。従って、金属或
いはシリサイド層１３と高濃度多結晶シリコンとの間の
接触抵抗は小さく、ｌ）で述べた高耐圧構造とこの低抵
抗構造が整合よく形成される。3) The low-resistance metal or silicide layer 13 does not directly contact the low-concentration source and drain regions 11 but through the high-concentration polycrystalline silicon 12 . Therefore, the contact resistance between the metal or silicide layer 13 and the highly doped polycrystalline silicon is small, and the high breakdown voltage structure described in 1) and this low resistance structure are formed with good matching.
４）低抵抗金属或いはシリサイド層１３が多結晶シリコ
ン１２上に形成されているため、第１図に示した従来構
造のところで述べたように金属或いはシリサイド層のゲ
ート絶縁膜下での横方向の侵入はない。従って、本構造
によりＭＯＳトランジスタの短チヤネル化とソース、ド
レインの低抵抗化が同時に実現される。4) Since the low resistance metal or silicide layer 13 is formed on the polycrystalline silicon 12, as described in the conventional structure shown in FIG. There is no intrusion. Therefore, with this structure, it is possible to simultaneously shorten the channel of the MOS transistor and lower the resistance of the source and drain.
５）ソース、ドレイン１１上の多結晶シリコン１２がゲ
ート電極８とほぼ同じ高さに形成されているため、ＭＯ
Ｓトランジスタの表面が平坦化され、ＭＯＳトランジス
タの製造プロセス上好ましい。5) Since the polycrystalline silicon 12 on the source and drain 11 is formed at almost the same height as the gate electrode 8, the MO
The surface of the S transistor is flattened, which is preferable for the manufacturing process of a MOS transistor.
６）ソース、ドレイン上には低抵抗金属やシリサイド１
３が形成されているため、ソース、ドレイン上にアルミ
ニウム等による電極を形成した場合、アルミニウムとシ
リコン基板との合金反応を防ぐことができ、さらにアル
ミニム等による電極とソース、ドレインとの電極孔接触
抵抗も低減される。6) Low resistance metal or silicide 1 on the source and drain
3 is formed, when an electrode made of aluminum or the like is formed on the source or drain, an alloy reaction between the aluminum and the silicon substrate can be prevented, and furthermore, electrode hole contact between the electrode made of aluminum or the like and the source or drain can be prevented. Resistance is also reduced.
以下に本発明によるＭＯＳ ｌ−ランジスタの製造方法
を第３図を用いて説明する。まず、Ｐ形シリコン甚板’
７−にに厚さ０．１〜１．０μｍの厚い酸化膜を形成し
た後、能動領域となるところの上記酸化膜を削除し、フ
ィールド酸化膜１０を形成する。その後５３〜’５０ｎ
ｍの薄いゲート絶縁膜１５を能動領域に形成する（第３
図Ａ）。その後、２００ ＫｅＶ以上の高エネルギーで
ボロン等のＰ形不純物を１０ ”□Ｏｃ’ｒＸフィール
ド酸化膜１０及びゲート絶Ｂ１Ｍ１５を通してイオン打
ち込みし、シリコン基板表面にｐ影領域１６を形成する
（第３図Ｂ）にのｐ影領域１６はフィールド酸化膜ｌｏ
下では寄生Ｍ ０ Ｓ トランジスタの発生を防ぐチャ
ポルストッパ−として働き、ゲーＩ−４！８１ｆｔ（膜
１５下ではＭＯ３Ｉ−ランジスタのしきい値電圧制御と
パンチスルーストッパとして働く。次に、タングステン
等の金属やシリサイド或いは多結晶シリコンによるゲー
ト電極１７を絶縁膜１８をマスクとして加工形成する。A method of manufacturing a MOS l-transistor according to the present invention will be explained below with reference to FIG. First, P-type silicone board'
After forming a thick oxide film with a thickness of 0.1 to 1.0 μm on 7-, the oxide film that will become the active region is removed, and a field oxide film 10 is formed. After that 53~'50n
m thin gate insulating film 15 is formed in the active region (third
Figure A). Thereafter, P-type impurities such as boron are ion-implanted with high energy of 200 KeV or more through the 10"□Oc'r The p shadow region 16 in B) is the field oxide film lo
Below, it acts as a chapol stopper to prevent the generation of parasitic M0S transistors, and below the gate film 15, it acts as a threshold voltage control and punch-through stopper for MO3I transistors.Next, tungsten, etc. A gate electrode 17 made of metal, silicide, or polycrystalline silicon is formed using the insulating film 18 as a mask.
その後、りんやひ素等の■！形不純物を１０〜１０ｃＭ
イオン打ち込みし、低濃度ソース、トレイン領域１９を
形成する（第３図Ｃ）。After that, phosphorus, arsenic, etc.■! 10-10cM of form impurities
Ion implantation is performed to form low concentration source and train regions 19 (FIG. 3C).
次に厚さ０．１〜０．５μｍの絶縁膜２０を化学気相反
応等により形成しく第３図Ｄ）、その後、異方性エツチ
ングにより上記絶縁膜２０をエツチングして段差部にの
みスペース２１として残す。次に。Next, an insulating film 20 with a thickness of 0.1 to 0.5 μm is formed by a chemical vapor phase reaction or the like (FIG. 3D), and then the insulating film 20 is etched by anisotropic etching to form a space only in the step portion. Leave it as 21. next.
高濃度のｎ形多結晶シリコン２２を０．１〜１．０μｍ
の厚さでソース、ドレイン領域１９上に形成する。Highly concentrated n-type polycrystalline silicon 22 with a thickness of 0.1 to 1.0 μm
is formed on the source and drain regions 19 to a thickness of .
この多結晶シリコン２２をソース、ドレイン１９上にの
み形成する方法としては、選択的化学気相反応法や、通
常の化学気相反応法による膜堆積後のドライエツチング
による自己整合形の埋め込み法がある。次に、多結晶シ
リコン層２２上に選択的にタングステン等の金属やシリ
サイド層２３を形成する（第３図Ｅ）。最後に、ＰＳＧ
や窒化膜等による保護膜２４を形成し、電極孔と電極２
５を形成する（第３図Ｆ）。Methods for forming this polycrystalline silicon 22 only on the source and drain 19 include a selective chemical vapor phase reaction method and a self-aligned embedding method using dry etching after film deposition using a normal chemical vapor phase reaction method. be. Next, a metal such as tungsten or a silicide layer 23 is selectively formed on the polycrystalline silicon layer 22 (FIG. 3E). Finally, P.S.G.
A protective film 24 made of a nitride film or the like is formed to protect the electrode hole and the electrode 2.
5 (Figure 3F).
なお、本発明の特徴を有する他の構造としては、第４図
に示すように、フィールド酸化膜の代りにグー１−電極
と同じ構造２４を形成し、これを接地電位として用いる
ことも可能である。As another structure having the characteristics of the present invention, as shown in FIG. 4, it is also possible to form the same structure 24 as the Goo 1 electrode instead of the field oxide film and use this as the ground potential. be.
本発明によれば、ＭＯＳ）−ランジスタの高耐圧化、短
チヤネル化による高速化高集デ化ソース、ドレイン抵抗
低減による高集積化が可能であり、その製造プロセスも
自己整合法を有効に用いることにより簡略化でき、製造
コストの低減化が可能である。従って、本発明により１
．０〜０．１μｍの寸法を有する微細ＭＯＳトランジス
タ及びそれを用いた大規模集積回路が実現できる。According to the present invention, it is possible to increase the breakdown voltage of a MOS transistor, shorten the channel to achieve high speed, and reduce the source and drain resistance to achieve high integration.The manufacturing process also effectively uses the self-alignment method. This makes it possible to simplify the process and reduce manufacturing costs. Therefore, according to the present invention, 1
．． Fine MOS transistors having dimensions of 0 to 0.1 μm and large-scale integrated circuits using the same can be realized.
なお、本発明は実施例に限定されることなく、本発明の
思想を逸脱しない範囲で種々変更が可能である。例えば
、本発明によるＭＯ８＋−ランジスタはＣＭＯ８栂造の
ウェルの中に形成されてもよく、又ＰチャネルＭｏｓ＋
−ランジスタであってもよい。Note that the present invention is not limited to the embodiments, and various changes can be made without departing from the spirit of the present invention. For example, a MO8+- transistor according to the present invention may be formed in a CMO8 well, or a P-channel Mos+
- It may be a transistor.
第１図は従来構造の断面図、第２図は本発明における実
施例の断面図、第３図は本発明による実施例の製造工程
を工程順に示す断面図、第４図は本発明による他の実施
例を示す断面図である。
１−２７・・・シリコン基板、２，８．１７・・・ゲー
ト電極、５，１４．１５・・・ゲート絶縁膜、４，１１
゜１９・・・ソース・ドレイン領域、６，１３．２３・
・・低抵抗金属又はシリサイド、３，９，１８，２０゜
２１．２４・・・絶縁膜、１２．２２・・・多結晶シリ
コ瑳１の
２
茅 ２ 図
第３０
第１頁の続き
■発明者 和１）恭雄 国イ
央（
＠発明者 水量 喜夫 国づ
央（
す寺市東恋ケ窪１丁目２８幡地 株式会社日立製作所中
汗究所内
す寺市東恋ケ窪１丁目２８幡地 株式会社日立製作所中
斤究所内FIG. 1 is a sectional view of a conventional structure, FIG. 2 is a sectional view of an embodiment according to the present invention, FIG. 3 is a sectional view showing the manufacturing process of an embodiment according to the present invention in order of process, and FIG. 4 is a sectional view of another embodiment according to the present invention. FIG. 1-27...Silicon substrate, 2,8.17...Gate electrode, 5,14.15...Gate insulating film, 4,11
゜19...source/drain region, 6,13.23.
...Low-resistance metal or silicide, 3,9,18,20°21.24...Insulating film, 12.22...Polycrystalline silicon paste 1-2 Kaya 2 Figure 30 Continued from page 1 ■Invention Person Kazu1) Kunizuo Kunizuo (@Inventor Yoshio Mizuno) (1-28 Hata, Higashi-Koigakubo, Tera-shi Hitachi, Ltd. Nakakankyujo 1-28 Hata, Higashi-Koigakubo, Tera-shi Hitachi, Ltd. Inside the laboratory
Claims (1)
て設けられたゲート電極を有する絶縁ゲート電界効果ト
ランジスタにおいて、上記半導体基板表面に第２導電形
の低不純物濃度ソース、ドレインが設けられる、さらに
上記ソース、ドレイン上に第２導電形の高不純物濃度多
結晶半導体と低抵抗の金属或いはシリサイドが形成され
たことを特徴とする半導体装置。In an insulated gate field effect transistor having a semiconductor substrate of a first conductivity type and a gate electrode provided through a thin G-1 to insulating film, a low impurity concentration source and a drain of a second conductivity type are provided on the surface of the semiconductor substrate. A semiconductor device further comprising a second conductivity type high impurity concentration polycrystalline semiconductor and a low resistance metal or silicide formed on the source and drain.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58236162A JPS60128656A (en) | 1983-12-16 | 1983-12-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58236162A JPS60128656A (en) | 1983-12-16 | 1983-12-16 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60128656A true JPS60128656A (en) | 1985-07-09 |
Family
ID=16996684
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58236162A Pending JPS60128656A (en) | 1983-12-16 | 1983-12-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60128656A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02164059A (en) * | 1988-10-24 | 1990-06-25 | Internatl Business Mach Corp <Ibm> | Manufacture of |
| US5571735A (en) * | 1994-06-21 | 1996-11-05 | Nec Corporation | Method of manufacturing a semiconducter device capable of easily forming metal silicide films on source and drain regions |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5286086A (en) * | 1976-01-12 | 1977-07-16 | Hitachi Ltd | Field effect transistor |
| JPS57196573A (en) * | 1981-05-27 | 1982-12-02 | Toshiba Corp | Manufacture of mos type semiconductor device |
-
1983
- 1983-12-16 JP JP58236162A patent/JPS60128656A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5286086A (en) * | 1976-01-12 | 1977-07-16 | Hitachi Ltd | Field effect transistor |
| JPS57196573A (en) * | 1981-05-27 | 1982-12-02 | Toshiba Corp | Manufacture of mos type semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02164059A (en) * | 1988-10-24 | 1990-06-25 | Internatl Business Mach Corp <Ibm> | Manufacture of |
| US5571735A (en) * | 1994-06-21 | 1996-11-05 | Nec Corporation | Method of manufacturing a semiconducter device capable of easily forming metal silicide films on source and drain regions |
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