JPS5975653A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the degree of integration of the device using a CMOS element by boring a contact opening, introducing boron to the whole surface of a polycrystalline silicon film formed to the whole surface of a main surface, selectively removing a silicon oxide film formed to the whole surface and introducing phosphorus only to the contact opening section of an n type diffusion layer section while using the oxide film as a mask. CONSTITUTION:The contact openings are formed protruded from the edges of impurity diffusion layers 106, 107. The polycrystalline silicon film 110 in 1,000Angstrom is grown on the whole surface of the main surface, and boron is introduced to the whole surface. Boron is introduced to both contact opening sections of the p and n type impurity diffusion layers through the polycrystalline silicon film 110. The non-doped silicon oxide film 113 is grown on the whole surface of the main surface, the silicon oxide film 113 is removed selectively by using a photoetching method, the polycrystalline silicon film 110 of the n type diffusion layer section is exposed, and phosphorus is introduced to the whole surface through a thermal diffusion method at 900 deg.C. The silicon oxide film 113 functions as a mask on the diffusion of phosphorus to prevent the introduction of phosphorus in the opening section to the p type diffusion layer, and a novel p type diffusion layer 112 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor integrated circuit device using an insulated gate field effect (MOS) type device, particularly a complementary insulated gate field effect (MOS) type device.

In recent years, so-called CMO8 integrated circuit devices using both p- and n-channel MOS transistors have attracted attention from the standpoint of low power consumption and high-speed operation. However, in terms of the degree of integration, devices using 0MO8 devices have the disadvantage of being significantly inferior to devices using only n-channel MO8 devices (or only p-channel MOB devices). In particular, for contact openings used to connect metal wiring and diffusion layers, even if the edges of the opening and the diffusion layer are close to each other, impurities are introduced through the opening to prevent destruction of the p-n junction. Contact method”
It is possible to use only n-gyannel MO8 elements (or p
However, in a device using 0 MO8 elements, the diffusion layer is p-type and n-type 2f! It is difficult to apply the "external punching contact method" because there are similar types, and it is necessary to have a large margin for alignment between one contact hole and the diffusion layer, which has the disadvantage of causing a decrease in the degree of integration.

The purpose of this invention is to develop a semiconductor assembly using CMO8 elements.
It is an object of the present invention to provide a manufacturing method that realizes an improvement in the degree of integration and reliability of an f-circuit device, as well as an improvement in operating speed.

The method for manufacturing a C0M5 integrated circuit device according to the present invention is to grow a polycrystalline silicon film over the entire main surface after opening a contact for connecting a metal wiring and an impurity diffusion layer, and then implant boron over the entire surface by ion implantation. (1) selectively removing the silicon oxide film in the n-type impurity diffusion layer portion using the silicon oxide film as a mask; and n-type diffusion using the silicon oxide film as a mask. The method is characterized in that it includes a step of introducing phosphorus (P) only into the contact opening portion of the layer portion by thermal diffusion or ion implantation.

In this invention, boron is introduced into the opening of the p-type diffusion layer, and the concentration of boron and phosphorus is appropriately selected into the opening of the n-type diffusion layer. By using the method, contact openings to the HP type and 11 type diffusion layers can be newly opened to add p type and n type diffusion layers, respectively. Therefore, even in integrated circuits using CMO8 elements, the [external contact method] is possible, and the margin for alignment between the opening and the diffusion layer can be virtually eliminated.
It is possible to realize higher integration, higher reliability, and even higher operating speed.

Next, an embodiment of the present invention will be described with reference to all the drawings. FIG. 1 shows the metal layout #j! using a normal CMOS process. FIG. 3 is a cross-sectional view of the device after contact opening for performing the process. In the figure, 101 is an n-type silicon substrate, 10
2 is a p-well, 103 is a field oxide film, 104 is a gate oxide film, 105 is a polycrystalline silicon gate electrode doped with l-type impurities, 106 is an n-type impurity diffusion layer, 10
7 is a p-type impurity diffusion layer, 108 is an interlayer insulating film, and 109 is a contact opening. In this embodiment, the contact openings are formed to protrude from the edges of the impurity diffusion layers 106 and 107. When metal wiring is formed in this state, the p-well 102 and the n-type impurity diffusion layers 106 and n
The p-n junction formed between the p-type silicon substrate 101 and the p-type impurity diffusion layer 1070 is destroyed, and the operation of the device is prevented. The present invention is intended to provide a manufacturing method that operates with reliability even when a contact is opened as shown in FIG. 1, and specific examples thereof are shown in FIGS. 2 and subsequent figures. Figure 2 shows a polycrystalline silicon film 1 of 100 OX on the entire main surface.
After growing 10, boron (B) is ion-implanted onto the entire surface #) lXl0 /crI? □This is a cross-sectional view when introducing boron (B) into the contact openings of both the p- and n-type impurity diffusion layers through the polycrystalline silicon film 110.
) has been introduced. Subsequently, a dinon-doped silicon oxide film 113 (c-0,5
After the silicon oxide film 113 is selectively removed using photolithography to expose the polycrystalline silicon film 110 in the n-type diffusion layer, thermal diffusion is performed at 900°C over the entire surface. Figure 3 shows the introduction of Sirin (P) by the method. In this case, during phosphorus diffusion, the silicon oxide film 113 acts as a mask to prevent the introduction of phosphorus into the opening to the p-type diffusion layer, so only boron flows through the opening into the new p-type diffusion layer 1.
form 12. Boron and phosphorus are still introduced continuously into the opening to the n-type diffusion layer through the polycrystalline silicon 110, but as in the case shown in this example, the concentration of the introduced phosphorus is lower than that of boron. If it is two or more orders of magnitude higher than , the effect of the introduced boron is almost canceled out by the phosphorus, and only a new n-type diffusion layer 111 is formed.

After that, the silicon oxide film 113 left in the hydrofluoric acid solution
is removed to expose a polycrystalline silicon film 110 over the entire track, and an aluminum layer %l# 114 is deposited to a thickness of 1.0 μm. Using photolithography again, the aluminum wiring 114 and polycrystalline silicon film 110 are removed into a desired wiring shape, and the device is completed as shown in FIG.

According to this embodiment, by using only one photolithographic process, the opening of the p-type diffusion layer 1if1 is exposed to the sludge through the opening.
A type diffusion layer 112 can be added, and a new LCN type diffusion layer 111 can be added to the n type diffusion layer opening through the opening. Therefore, the "outside contact method" that virtually eliminates the alignment margin between the opening and the diffusion layer can be applied to the 0MO8 element, which significantly improves the degree of integration, reliability, and operation of devices using the 0MO8 element. It is possible to improve speed.

[Brief explanation of the drawing]

FIGS. 1 to 4 are sectional views showing each manufacturing process of an apparatus showing an embodiment of the present invention. In the figure, 101... n-type silicon substrate, 102...
P well, 103...Field oxide film, 104
...Gate oxide film, 105 - Polycrystalline silicon gate electrode, 106 - N-type impurity diffusion layer, 107...
... n-type impurity diffusion layer, 108 ... interlayer insulating film, 109 ... contact opening, 110 ...
・Polycrystalline silicon film, 111 Added n-type impurity diffusion layer, 112... Added n-type impurity diffusion layer, 113... Silicon oxide film, 114... Aluminum wiring. be.

Claims (1)

[Claims] In the manufacturing process of a semiconductor integrated circuit device using a complementary insulated gate field effect element, a contact opening for connecting a metal wiring and an impurity diffusion layer, a process of growing a polycrystalline silicon film over the entire main surface, and a subsequent process. All over? '! A process of introducing phosphorus (3) by ion implantation, followed by growing a silicon oxide film on the entire surface by vapor phase growth, and forming a pn type impurity diffusion layer part L: silicon oxide film by photolithography. and a step of selectively removing phosphorus (P) using the silicon oxide film as a mask and introducing phosphorus (P) only into the opening of the n-type diffusion region by thermal diffusion or ion implantation. A method for manufacturing a semiconductor integrated circuit device.