JPS63128661A - Manufacture of cmos semiconductor device - Google Patents

Abstract

PURPOSE:To decrease the number of photo resist processes for masking both MOS transistors one time and to obtain good contact resistance in a fine contact area by a method wherein the whole surface of a substrate is coated with a barrier layer after contact holes are formed, an impurity is ion-implanted in the whole surface and moreover, an impurity is ion-implanted masking the MOS transistor on one side. CONSTITUTION:P<+> source and drain regions 5 and 6 and N<+> source and drain regions 7 and 8 are respectively formed in a substrate 1 and a well region 2. Contact holes 12 are formed in an insulating film 13 on the source and drain regions 5-8 of both MOS transistors 9 and 10. Then, a thin barrier layer 20 is adhered on the whole surface of the insulating film 13. An impurity to give one conductivity type or an inverse conductivity type to the surfaces of the source and drain regions 5-8 of both MOS transistors 9 and 10 is ion-implanted in the whole surface of the substrate without using a mask layer from over the barrier layer 20 through the contact holes 12 and contact regions 14 and 15 are formed. Then, the upper part of the MOS transistor 9 of a P channel is covered with a mask layer and an ion-implantation of arsenic As<+> is performed in the source and drain regions 7 and 8 of the MOS transistor 10 of an N channel.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a method of manufacturing a CMO5 semiconductor device, and more particularly to a method of manufacturing a CMO3 semiconductor device that allows finer contacts to be obtained.

(B) Prior Art Since a conventional CMOS semiconductor device is formed with a large source/drain region, there is a margin for misalignment when forming a contact hole to the source/drain region.

However, in order to achieve higher integration of CMOS semiconductor devices, MOS transistors have been miniaturized, and as a result, source and drain regions of MOS transistors have also been formed more easily. For this reason, the margin for misalignment of the contact hole is greatly reduced, and the contact hole may be formed protruding from the source/drain region. In this case, leakage current is generated from the source/drain electrode to the substrate or P-well region. I will do it.

As methods for preventing this, there are a method of forming a contact hole using self-alignment as shown in Japanese Unexamined Patent Publication No. 52-60571, and a method of implanting impurity ions into the contact hole.

The latter method described above is detailed in FIGS. 2A to 2E.

First, as shown in FIG. 2A, a P channel MOS transistor (27) and an Nf channel MO3 transistor (30) are formed in a semiconductor substrate (21) by a well-known method. (21) is an N-type silicon semiconductor substrate, (22) is a P-type well region formed by ion implantation, (23) is a field oxide film formed by selective oxidation, (24) is a gate electrode made of polysilicon, (25) (26) are P" type source drain regions of P channel MO3I-transistor (27), (28) and (29) are N channel MOS
This is the N+ type source/drain region of the transistor (30).

Next, as shown in FIG. 2B, a P-channel MOS transistor (27) and an N-channel MO8 transistor (
30) each source drain region (25) (26) (28
) (29) Contact hole (32) in oxide film (31) on top
...(32) is formed. In this step, the contact holes (32), . . . (32) are simultaneously formed using well-known photoetching. In this process, each contact hole (32)
...(32) represents each source/drain region (25) (26)
)(28) May protrude from (29).

Next, as shown in FIG. 2C, boron ions are implanted onto the P-channel MOS transistor (27) while masking the N-channel MOS transistor (30) with a photoresist J1 (33). In this process, the contact hole (32)
(32) to its opening via a P-type contact region (
34) (35) are formed.

Next, as shown in the second diagram, arsenic ions are implanted onto the N-channel MOS transistor (30) while masking the P-channel MOS transistor (27) with a photoresist layer (36). In this process, the contact hole (32) (3
2) into the opening through the N-type contact region (37
)(38) is formed.

Furthermore, as shown in FIG. 2E, aluminum Jl (39), which is a metal electrode material, is sputtered over the entire surface of the semiconductor substrate (21). The aluminum layer (39) is sputtered and then photo-etched to form the desired source/drain electrodes.

According to the method described above, there is always a P-type or N-type contact region (34) (35) (37>
(38), and the source and drain electrodes are connected to contact holes (
32) It is possible to prevent contact with the substrate (21) or the well region (22) due to positional deviation of (32).

(c) Problems to be Solved by the Invention However, according to the above-mentioned conventional method for manufacturing a CMOS semiconductor device, contact regions (34), (35), and
) When performing ion implantation to form (38), there was a problem in that two photoresist steps were required to be used as a mask.

Means for solving the problems The present invention has been made in view of the above problems, and is based on one MOS
The present invention provides a method for manufacturing a CMO3 semiconductor device in which the number of photoresist steps is reduced by one compared to the conventional method by forming a contact region of a transistor by ion implantation without using a mask layer.

Furthermore, the present invention provides a method for manufacturing a CMO5 semiconductor device in which good contact resistance can be obtained even with a small contact area by performing ion implantation through a barrier layer.

(E) Function According to the present invention, after forming the contact hole, the entire surface of the substrate is covered with a barrier layer, impurity ions are implanted over the entire surface, and one of the MOS transistors is further masked and impurity ions are implanted, so that both MO8) Since the contact area is formed under the contact hole of the transistor, the photoresist process for the mask can be reduced to one time.Also, since the barrier layer eliminates direct contact between the metal electrode layer and the contact area, the contact area can be Prevents silicon precipitation.

(F) Embodiment An embodiment of the present invention will be described in detail with reference to FIGS. 1A to 1E.

As shown in FIG. 1A, the first step of the present invention is to form a reverse conductivity type source/drain region (5) on a semiconductor substrate (1) of one conductivity type to form a reverse conductivity channel MOS transistor (9). 6) and a conductive channel MO in the well region (2) of the opposite conductivity type provided on the surface of the semiconductor substrate (1).
The purpose is to form source and drain regions (7) and (8) of one conductivity type forming a 3I-transistor (10).

This step is manufactured using a conventionally well-known CMOS process. A P-type well region (2) is formed on an N-type silicon semiconductor substrate (1) by ion implantation, and a thick buried field is formed on the field region on the surface of the substrate (1) and the well region (2) by selective oxidation. An oxide film (3) is formed. A gate electrode (4) made of phosphorus-doped polysilicon is formed on the substrate (1) and the well region (2) via a gate oxide film (11).
4) as a mask and use Selfa Line to attach the substrate (1).
) P1 type source/drain regions (5) (6), and N4 type source/drain regions (7) (8) in the well region (2).
can be formed.

The second step of the present invention, as shown in FIG. 1B, is the source/drain regions (5) (
6) Contact hole (12)...(1) on (7) (8)
2).

This process is performed using conventionally well-known photoetching, and both M
Contact holes (12) (12) are formed in the insulating film (13) on the source/drain regions (5) (6) (7) (8) of the O3I transistors (9) (10). At this time, the contact holes (12)...(12) are minute, with a diameter of 1 to 2 μm, and the contact holes (12)...(12) are the sources of both MOS transistors (9) and (10) due to mask misalignment. The drain region (5) (6) <7) (8) may be formed offset from the drain region (5) (6) <7) (8).

The third step of the present invention is to form an insulating film (
13) depositing a barrier layer (20) on top.

This step is a characteristic step of the present invention, and is an insulating film (13
) A thin barrier Jl (20) is attached to the entire upper surface. The barrier layer (20) is made of polysilicon or TiSi.

Silicide such as T-kei is used. In this step, a non-doped polysilicon layer was deposited to a thickness of 1000 Å or less by low pressure CVD. This polysilicon layer has the function of preventing direct contact between the metal electrode layer and the substrate, and the function of protecting the substrate surface during ion implantation in a subsequent process.

Similarly, in the fourth step of the present invention, as shown in FIG. 1C, the contact holes (12)...(1
2), an impurity giving one conductivity type or an opposite conductivity type is ion-implanted into the surfaces of the source and drain regions (5) (6) (7) (8) of both MO8) transistors (9) (10), and the contact regions ( 14>(15).

This step is a characteristic step of the present invention, in which ions are implanted into the substrate (1) to form the contact regions (14) and (15).
The purpose is to perform the process without a mask layer on the entire surface. That is, with the contact holes (12)...(12) formed, boron (
B+) ion implantation is performed. This ion implantation was performed at an acceleration voltage of 40 KeV and a dose of I
) P1 type contact regions (14) and (15) are formed through the contact regions (14) and (15). At this time, boron is also implanted into the source and drain regions (7) and (8) of the N-channel MO3I-transistor (10) through the contact holes (12) and (12). Since the concentration of is high, there is no risk of the surface becoming P-type.

Note that in this step, boron ions are also implanted into the barrier layer (20), so the entire polysilicon is doped with boron. Also, due to the presence of the barrier layer (20), the peak of the impurity concentration during ion implantation is reduced to the contact regions (14) and (15).
It can be placed on the surface, reducing contact resistance.

As shown in the first diagram, the fifth step of the present invention is to cover the contact hole (12>(12)) on the source/drain region of the MOS transistor -b with a mask layer (16), and The purpose is to form contact regions by ion-implanting impurities imparting opposite conductivity type or one conductivity type from above the barrier layer (20) through contact holes (12) (12) on the source and drain regions of the barrier layer (20).

In this step, the Pf channel MOS transistor (9) is covered with a mask layer (16) made of photoresist, and the contact holes (12) (12 ) ion implantation of arsenic (As”) is carried out using an accelerating voltage of 80 KeV and a dose of 1×1018σ.
-2, N-channel MO9 transistor off 10)
N+ type contact regions (1) are also formed on the source and drain regions (7) and (8) of the
7) (18) is formed. Nfw tunnel MO in the previous process
Contact hole (12) (12) of S transistor tank 10)
), but boron ion implantation can be compensated for by sufficiently implanting arsenic ions in this step.

Also, in this process, the barrier J! on the N-channel MOS transistor (10) which is completely exposed! ? The (20) polysilicon is doped with arsenic to cancel out the boron implanted in the previous step and to be N-type doped. Further, due to the presence of the barrier layer (20), the impurity concentration peak of ion implantation is located on the surfaces of the contact regions (17) and (18), thereby reducing contact resistance.

In the sixth step of the present invention, as shown in FIG.
) on the barrier layer (20) on the insulating film (13).

This step utilizes a well-known electrode formation method and is performed on the substrate (1) (
7) Barrier layer (20) Aluminum all over! (19) is attached by sputtering. Therefore the aluminum layer (19)
are the contact holes (12) with the barrier layer (20) in between.
...(12) to each MO8) transistor (9) (1
It makes ohmic contact with the source/drain regions (5), (6), (7), and (8) of 0). Especially the contact hole (12)...
(12) due to mask shift, each MO3) transistor (9)
)Do) source drain region (5>(6>(7)(8
) even if it is formed protruding from the contact hole (12).
...(12) Since the contact regions (14), (15), (17), and (18) are always formed under the self-alignment lines, the aluminum layer (19) is always connected to each MOS transistor (9), (10). source drain region (5)
(6) (7) (8) are connected.

Also, in this process, aluminum containing 1% by weight of silicon is normally used as the metal electrode layer (19), so if it is directly deposited on the contact area (14) < 15) (17) (18), the silicon in the aluminum will spread to the contact area. (14) (15) (17) (18) There was a tendency for contact resistance to increase due to precipitation on the surface. However, in this example, the barrier W (20) prevents direct contact between the aluminum layer (19) and the contact regions (14), (15), (17), and (18).
9) There is no risk that the silicon inside will precipitate and increase the contact resistance. Therefore, the contact hole (12)...(
Even if the diameter of 12) is about 1.2 μm, a good contact can be formed.

Another embodiment of the present invention will be described. The fourth step mentioned above (
In Fig. 1 C), arsenic (As”) is ion-implanted over the entire surface, and N
Contact regions (17) (18) are formed on the source/drain regions (7) (8) of the channel MOS transistor (10).
) to form. After that, the fifth step mentioned above (Fig. 1D)
Then, the N-channel MOS transistor (10) is covered with a mask layer (16) to form a P-channel MOS transistor (
Contact regions (14) and (15) are formed by implanting boron (B+) ions onto the source and drain regions (5) and (6) of 9) through the contact holes (12) and (12).

The remaining steps are the same as described above.

(G) Effects of the Invention According to the present invention, firstly, each MOS transistor (9) (
Contact areas (14) (15) (1
7) When forming (18), by performing ion implantation over the entire surface, the mask layer (16) for ion implantation can be realized in one photoresist process, making CMOS simpler than conventional CMOS.
It has the advantage of being able to implement a method for manufacturing semiconductor devices.

Second, since contact regions (14), (15), (17), and (18) are formed by self-alignment lines under the contact holes (12), ... (12) of each MOS transistor (9), (1o), There is no short circuit between the metal electrode layer (19) and the substrate (1) or the well region (2), and the diameter of the contact holes (12) can be reduced to less than )(7)(8)
This has the advantage that the size of the CMOS semiconductor device can be reduced, and a method for manufacturing a CMOS semiconductor device that can be extremely miniaturized can be realized.

Thirdly, by interposing the barrier layer (20), the metal electrode layer (19) and the contact regions (14), (15), and (17)
) (18) can be eliminated, silicon precipitation from the metal electrode layer (19) can be suppressed, and a miniaturized contact with low contact resistance can be realized.

[Brief explanation of the drawing]

1A to 1E are cross-sectional views illustrating a method for manufacturing a CMOS semiconductor device according to the present invention, and FIGS. 2A to 2E
1 is a cross-sectional view illustrating a conventional method of manufacturing a CMO5 semiconductor device. (1) is a semiconductor substrate, (2) is a well region, (5)
(6)<7) (8) is the source/drain region, (9)
is a Pf cancel MOS transistor, (10) is an N-channel MOS transistor, (12)...(12) is a contact hole, (14) (Is) (17) (18)
is the contact region, (19) is the metal electrode layer, (20)
is a barrier layer. Applicant Sanyo Electric Co., Ltd. and one other agent Patent attorney Takuji Nishino and one other person Fig. 1 A Fig. 1 B 14 So] Co First drawing Fig. 1 E Fig. 2 A Fig. 2 B lt 30 Fig. 2 Diagram 2 E

Claims (1)

[Claims] (1) MO of opposite conductivity channel on semiconductor substrate of one conductivity type
A step of forming a source drain region of opposite conductivity type to form an S transistor, and forming a source drain region of one conductivity type to form a MOS transistor of one conductivity channel in a well region of opposite conductivity type provided on the surface of the semiconductor substrate. forming contact holes on the source and drain regions of both the MOS transistors in an insulating film covering the surface of the semiconductor substrate; depositing a barrier layer on the insulating film; forming a contact region by ion-implanting an impurity giving one conductivity type or an opposite conductivity type into the surface of the source and drain regions of both MOS transistors from above the barrier layer; and forming the contact hole on the source and drain region of one of the MOS transistors. is coated with a mask layer, and the other M
forming a contact region by ion-implanting an impurity imparting opposite conductivity type or one conductivity type from above the barrier layer through the contact hole on the source/drain region of the OS transistor; and the barrier layer on the semiconductor substrate. A method for manufacturing a CMOS semiconductor device, comprising the step of sputtering a conductive metal thereon.