JP2760493B2 - Method for manufacturing CMOS semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a CMOS semiconductor device, and more particularly to a method for manufacturing a CMOS semiconductor device capable of obtaining a miniaturized contact. (B) Conventional technology In a conventional CMOS semiconductor device, a large source / drain region is used, and therefore, there is a margin for displacement when a contact hole to the source / drain region is formed. However, MOS transistors have been miniaturized in order to achieve higher integration of CMOS semiconductor devices.
Source / drain regions of transistors have also been made smaller. As a result, the margin for positional displacement of the contact hole is greatly reduced, and the contact hole may be formed to protrude from the source / drain region. In this case, a leak current is generated from the source / drain electrode to the substrate or the P-well region. Will do. As methods for preventing this, there are a method of forming a contact hole by self-alignment as disclosed in Japanese Patent Application Laid-Open No. 52-60571 and a method of ion-implanting impurities into the contact hole. The latter method described above with reference to FIGS. 2A to 2E will be described in detail. First, as shown in FIG. 2A, a P-channel MOS transistor (27) and an N-channel MOS transistor (27) are formed in a semiconductor substrate (21) by a known method.
A channel MOS transistor (30) is formed. (twenty one)
Is an N-type silicon semiconductor substrate, (22) is a P-type well region formed by ion implantation, (23) is a field oxide film formed by selective oxidation, (24) is a gate electrode made of polysilicon, (25) (26) is a P ⁺ type source / drain region of a P-channel MOS transistor (27), (28) (29)
Is an N ⁺ type source / drain region of the N channel MOS transistor (30). Next, as shown in FIG. 2B, a P-channel MOS transistor (27) and an N-channel MOS transistor (30)
Contact holes (32)... (32) are formed in the oxide film (31) on each of the source / drain regions (25) (26)) (28) (29). In this step, the respective contact holes (32)... (32) are simultaneously formed by using known photoetching. In this step, the contact holes (32)... (32) may protrude from the source / drain regions (25) (26) (28) (29). Next, as shown in FIG. 2C, boron is ion-implanted on the P-channel MOS transistor (27) by masking the N-channel MOS transistor (30) with a photoresist layer (33). In this step, P-type contact regions (34) (35) are formed in the openings through the contact holes (32) (32). Next, as shown in FIG. 2D, arsenic is ion-implanted on the N-channel MOS transistor (30) while masking the P-channel MOS transistor (27) with a photoresist layer (36). Also in this step, N-type contact regions (37) and (38) are formed in the openings through the contact holes (32) and (32). Further, as shown in FIG. 2E, an aluminum layer (39) as a metal electrode material is sputtered on the entire surface of the semiconductor substrate (21). The aluminum layer (39) forms desired source / drain electrodes by photoetching after sputtering. According to the above-described method, P-type or N-type contact regions (34) (35) (37) (38) are always provided below the contact holes (32). , The source and drain electrodes are contact holes (32)… (32)
Substrate (21) or well area (22) due to misalignment
Contact can be prevented. (C) Problems to be Solved by the Invention However, according to the above-described conventional method for manufacturing a CMOS semiconductor device, the contact regions (34) (35) (37) (38)
When performing the ion implantation for forming the mask, there is a problem that two photoresist steps used as a mask are required. (D) Means for Solving the Problems The present invention has been made in view of the above problems, and one of the MOS
It is an object of the present invention to provide a method of manufacturing a CMOS semiconductor device in which a photoresist step is reduced by one time by ion-implanting a transistor contact region without using a mask layer. Further, the present invention provides a method for manufacturing a CMOS semiconductor device in which good contact resistance can be obtained even with a small contact area by performing ion implantation through a barrier layer. (E) Function According to the present invention, after the contact holes are formed, the entire surface of the substrate is covered with a barrier layer, impurities are ion-implanted over the entire surface, and the impurity is ion-implanted by masking one MOS transistor. Since the contact region is formed below the contact hole, the number of photoresist steps for the mask can be reduced to one, and direct contact between the metal electrode layer and the contact region is eliminated by the barrier layer.
Precipitation of silicon in the contact region can be prevented. (F) Embodiment One embodiment of the present invention will be described in detail with reference to FIGS. 1A to 1E. In the first step of the present invention, as shown in FIG. 1A, a reverse conductivity type source / drain region (5) (FIG. 1) for forming a MOS channel (9) of a reverse conductivity channel on a semiconductor substrate (1) of one conductivity type. 6) is formed, and a MOS channel of one conductive channel is formed in the well region (2) of the opposite conductivity type provided on the surface of the semiconductor substrate (1).
One object is to form source / drain regions (7) and (8) of one conductivity type for forming the transistor (10). This process is manufactured using a conventionally known CMOS process. A P-type well region (2) is formed in an N-type silicon semiconductor substrate (1) by ion implantation, and a thick buried-type field is formed by selective oxidation on the substrate (1) and the field region on the well region (2). An oxide film (3) is formed. A gate electrode (4) made of phosphorus-doped polysilicon is formed on the substrate (1) and the well region (2) via a gate oxide film (11). Self-alignment is performed using the gate electrode (4) as a mask. Utilizing a substrate (1), P ⁺ -type source / drain regions (5) and (6) are used in the substrate (1), and an N ⁺ -type source / drain region (7) is used in the well region (2)
(8) is formed. In the second step of the present invention, as shown in FIG. 1B, the source / drain regions (5) (6) of the MOS transistors (9) and (10) of the insulating film (13) covering the surface of the semiconductor substrate (1) )
(7) To form contact holes (12)... (12) on (8). This step is performed using a conventionally well-known photo-etching,
Contact holes (12)... (12) are formed in the insulating film (13) on the source / drain regions (5), (6), (7) and (8) of the MOS transistors (9) and (10). At this time, the contact holes (12)... (12) are as fine as 1 to 2 μm in diameter, and the contact holes (12). ) (6)
(7) In some cases, it is formed out of alignment with (8). The third step of the present invention is to deposit a barrier layer (20) on the insulating film (31) as shown in FIG. 1C. This step is a characteristic step of the present invention, and the insulating film (1
3) A thin barrier layer (20) is deposited on the entire upper surface. As the barrier layer (20), silicide such as polysilicon, TiSi, or TiW is used. In this step, a non-doped polysilicon layer was deposited to a thickness of 1000 mm or less by a low pressure CVD method. The polysilicon layer has a function of preventing direct contact between the metal electrode layer and the substrate, and a function of protecting the surface of the substrate during ion implantation in a later step. In the fourth step of the present invention, similarly, as shown in FIG. 1C,
The source / drain regions (5), (6), (7) and (8) of the MOS transistors (9) and (10) are formed on the surface of the barrier layer (20) through the contact holes (12). An object of the present invention is to form contact regions (14) and (15) by ion-implanting an impurity imparting a reverse conductivity type. This step is a characteristic step of the present invention, in which ion implantation for forming the contact regions (14) and (15) is performed over the entire surface of the substrate (1) without a mask layer. That is, ion implantation of boron (B ⁺ ) is performed with the contact holes (12)... (12) formed. This ion implantation is performed at an acceleration voltage of 40 KeV and a dose of 1 × 10 ¹⁵ cm ⁻² , and is formed on the source / drain regions (5) and (6) of the P-channel MOS transistor (9) through the contact holes (12) and (12). P ⁺ -type contact regions (14) and (15) are formed. At this time, N channel MOS
Source / drain regions of transistor (10) (7) (8)
Although boron is also implanted through the contact holes (12) and (12), the surface is not likely to become P-type because the source / drain regions (7) and (8) have a high concentration. In this step, since boron is also ion-implanted into the barrier layer (20), the polysilicon is entirely boron-doped. Further, the presence of the barrier layer (20) allows the peak of the impurity concentration of the ion implantation to be located on the surface of the contact regions (14) and (15), thereby reducing the contact resistance. In the fifth step of the present invention, as shown in FIG.
The contact holes (12) (12) on the source / drain regions of the MOS transistor are covered with a mask layer (16), and the other MOS
It is to form a contact region by ion-implanting an impurity imparting the opposite conductivity type or one conductivity type from above the barrier layer (20) through the contact holes (12) (12) on the source / drain regions of the transistor. In this step, the P-channel MOS transistor (9) is covered with a mask layer (16) made of photoresist, and contact holes (12) (12) are formed in the source / drain regions (7) (8) of the N-channel MOS transistor (10). Arsenic (As ⁺ ) is ion-implanted. This ion implantation is performed at an acceleration voltage of 80 KeV and a dose of 1 × 10 ¹⁶ cm ⁻² , and an N-channel M
OS transistor (10) source / drain region (7)
N ⁺ -type contact regions (17) and (18) are also formed on (8) via the contact holes (12) and (12). In the previous step, the contact hole (1
2) Boron is ion-implanted under (12). Boron ion implantation can be compensated by sufficiently ion-implanting arsenic in this step. Also, in this step, the polysilicon which is the barrier layer (20) on the exposed N-channel MOS transistor (10) is doped with arsenic to cancel the boron implanted in the previous step and dope it with N-type. In addition, due to the presence of the barrier layer (20), the peak of the impurity concentration of the ion
7) (18) Position on the surface to reduce contact resistance. In the sixth step of the present invention, as shown in FIG. 1E, the conductive metal layer (19) is sputtered on the barrier layer (20) on the insulating film (13) on the substrate (1). In this step, an aluminum layer (19) is sputtered onto the entire surface of the barrier layer (20) on the substrate (1) by utilizing a well-known electrode forming method. Therefore, the aluminum layer (19) sandwiches the barrier layer (20) and the source / drain regions (5) (6) (7) of each MOS transistor (9) (10) through the contact holes (12). Ohmic contact with (8). In particular, contact holes (12) ...
Even if they are formed so as to protrude from the source / drain regions (5) (6) (7) (8) of the S transistors (9) (10), the contact regions (12)... Since 14), (15), (17), and (18) are formed, the aluminum layer (19) must be
Source and drain regions of transistors (9) and (10) (5)
(6) Connected to (7) and (8). In this step, aluminum containing 1% by weight of silicon is usually used as the metal electrode layer (19), so that if it is directly attached to the contact regions (14), (15), (17) and (18), silicon in the aluminum will be (14) (1
5) There was a tendency that contact resistance increased due to precipitation on the (17) and (18) surfaces. However, in this embodiment, the barrier layer (20)
With aluminum layer (19) and contact area (4) (15)
(17) Since direct contact with (18) is prevented, there is no danger that silicon in the aluminum layer (19) will precipitate and increase the contact resistance. Therefore, a good contact can be formed even when the diameter of the contact holes (12)... (12) is about 1.2 μm. Another embodiment of the present invention will be described. Arsenic (As ⁺ ) is ion-implanted over the entire surface in the above-described fourth step (FIG. 1C).
Contact regions (17) and (18) are formed on the source / drain regions (7) and (8) of the channel MOS transistor (10). Thereafter, in the above-described fifth step (FIG. 1D), the N-channel MOS transistor (10) is covered with a mask layer (16) to cover the source / drain regions (5) and (6) of the P-channel MOS transistor (9). Boron (B ⁺ ) ions are implanted through the contact holes (12) (12) to form contact regions (14) (15). The remaining steps are the same as described above. (G) Effects of the Invention According to the present invention, first, each MOS transistor (9) (1)
In forming the contact regions (14) (15) (17) (18) by self-alignment under the contact holes (12) of (0) ... (12), ion implantation is carried out over the entire surface to form a mask layer for ion implantation. (16) can be realized in a single photoresist process, which has the advantage that a simpler method of manufacturing a CMOS semiconductor device than in the past can be realized. Second, since the contact regions (14) (15) (17) (18) are formed below the contact holes (12)... (12) of the MOS transistors (9) (10) by self-alignment, the metal electrodes are formed. Layer (19) and substrate (1) or well region (2)
There is no short circuit with the contact hole (12)… (12)
Of the source and drain regions (5)
(6) There is an advantage that the size of (7) and (8) can be reduced, and a method of manufacturing a CMOS semiconductor device which can be extremely miniaturized can be realized. Third, the metal electrode layer (19) and the contact regions (14) (15) (17) (18) by interposing the barrier layer (20)
This has the advantage that direct contact with the metal electrode can be eliminated, silicon deposition from the metal electrode layer (19) can be suppressed, and a miniaturized contact with low contact resistance can be realized.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1E are cross-sectional views for explaining a method for manufacturing a CMOS semiconductor device according to the present invention, and FIGS. 2A to 2E are views for manufacturing a conventional CMOS semiconductor device. It is sectional drawing explaining a method. (1) is a semiconductor substrate, (2) is a well region, (5)
(6), (7) and (8) are source / drain regions, and (9) is P
Channel MOS transistor, (10) N-channel MOS
Transistor, (12) ... (12) is contact hole, (14)
(15), (17) and (18) are contact regions, (19) is a metal electrode layer, and (20) is a barrier layer.

   ────────────────────────────────────────────────── ─── Continuation of front page    (56) References JP-A-59-75653 (JP, A)                 JP-A-60-182157 (JP, A)                 JP-A-53-86583 (JP, A)                 JP-A-59-201444 (JP, A)                 JP-A-56-133477 (JP, A)

Claims (1)

(57) [Claims] A reverse conductivity type source / drain region for forming a reverse conductivity type MOS transistor is formed in a semiconductor substrate of one conductivity type, and a MOS transistor of one conductivity type is formed in a reverse conductivity type well region provided on the surface of the semiconductor substrate. Forming a source / drain region of one conductivity type; forming contact holes on the source / drain regions of the two MOS transistors in an insulating film covering the surface of the semiconductor substrate; and a barrier made of silicide on the insulating film. Attaching a layer, and the two MOs from above the barrier layer through the contact hole.
By implanting boron or arsenic that gives one conductivity type or the opposite conductivity type to the source / drain region surface of the S transistor, a contact region where the impurity concentration peak of the ion implantation is shallower than the source / drain region located on the surface is formed. Covering the contact hole on the source / drain region of the one MOS transistor with a mask layer;
By implanting arsenic or boron giving the opposite conductivity type or one conductivity type from above the barrier layer through the above contact hole on the source / drain region of the transistor, the peak of the impurity concentration of the ion implantation is located on the surface. A method for manufacturing a CMOS semiconductor device, comprising: a step of forming a contact region shallower than a source / drain region; and a step of sputtering a metal electrode layer made of an aluminum layer on the barrier layer on the semiconductor substrate.