JP3161527B2 - Semiconductor device including diode structure and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a Zener diode used for a semiconductor integrated circuit and a method for manufacturing the same.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, a Zener diode is used to fix (clamp) a voltage difference at a specific location. 11 to 14 show examples of a conventional diode.

First, in the example of FIG. 11, a pn junction is formed by providing ap ⁺ diffusion layer 102 in an n well 101 formed by ion implantation into a silicon substrate, and ap ⁺ diffusion layer 1 is formed.
02 is connected to the anode electrode 104 and the n-well 101 is connected to the cathode electrode 105 to establish connection with the outside. The insulation is performed by the oxide film 103. The breakdown voltage is determined by the concentration of the diffusion layer at the pn junction. That is, a desired breakdown voltage can be obtained by changing the impurity concentration of the n-well or the p ⁺ diffusion layer. However, the diode is usually formed as one component in the semiconductor integrated circuit, and the n-well is formed simultaneously with the n-well in the pMOS formation region and the p ⁺ diffusion layer is formed simultaneously with the impurity implantation in the source / drain regions. There was a problem that the voltage of the above could not be obtained. To get the desired voltage,
Although it is possible to implant impurities separately from the MOS, there is a problem that the number of steps increases and the cost increases.

On the other hand, in the example of FIG. 12, an n-diffusion layer 106 and a p-diffusion layer 107 are formed side by side on the surface of a silicon substrate 108 as shown in FIG. In recent miniaturized MOSFETs, the surface of the impurity diffusion layer is silicided to reduce the resistance. However, in such a diode that forms a pn junction in the lateral direction, FIG. As shown in (b), when the surfaces of the adjacent p-diffusion layer 106 and n-diffusion layer 107 are silicided, the silicide layers 110 formed on the respective layers come into contact with each other and short-circuit, and do not function as a diode. There's a problem.

Japanese Patent Laid-Open No. 7-326774 discloses a diode structure shown in FIG. First
Field oxide film 214 of conductive type semiconductor substrate 211
Medium-concentration impurity layer 20 of the first conductivity type in a region defined by
1. An impurity layer 221 of the first conductivity type is provided thereon, and an impurity layer 222 of the second conductivity type is provided at a position away from the impurity layer. Further, a gate electrode 204 of a MOS element is provided on the substrate between the first conductivity type impurity layer 221 and the second conductivity type impurity layer 222, and the first conductivity type impurity layer 221 and the second conductivity type impurity layer 221 are provided. In the impurity layer 222, the wiring metal 2
25 is connected through a contact 224 provided on the insulating film 223 for multilayer wiring. According to the description of this publication, the breakdown is caused by the high-concentration impurity layer 2 of the second conductivity type.
22 and the first conductive type medium-concentration impurity layer 201, and its breakdown voltage can be adjusted by the voltage applied to the gate electrode 204.

However, in this method, in order to obtain a desired breakdown voltage, a constant voltage must always be applied to the gate electrode, and wires and contacts for applying a voltage to the gate electrode are required. Become. In addition, in order to form the medium-concentration impurity layer 201, it is necessary to add a step of forming a mask pattern and a step of implanting ions under conditions different from those of the drain diffusion layer and the well. further,
Although the breakdown voltage can be adjusted by the gate voltage, it is necessary to control the concentration to a desired value as in the example of FIG. 11 in order to make the voltage adjustable.

Japanese Patent Application Laid-Open No. 9-148591 discloses a diode structure shown in FIG. 14 (corresponding to FIG. 1 in the publication). Only the diode structure D2 related to the present invention will be described. D2 is the p anode region 3
09b is formed in the surface layer of the n ⁺ wall region 306 formed by diffusing impurities from the diffusion window 313.
According to this description, the surface concentration of the n ⁺ wall region is about 7
At 10 ¹⁸ cm ^-3 , the diffusion depth is about 11 μm. As shown in this figure, if the p anode region 309b is formed in a region about 3 μm (W) away from the diffusion window 313 formed in the field oxide film 311, the surface concentration becomes about 1 × 10 ¹⁸
cm ⁻³ , and the reverse blocking voltage of the diode is about 7.5 V. The breakdown voltage is determined by the thick line portion of the p anode region 309b in FIG. Drain contact region 308b
However, it also serves as the cathode of the diode.

That is, in this structure, the n ⁺ wall region 306 is a region which is heavily doped with impurities, is doped with impurities from the diffusion window 313, and has a concentration distribution in the surface also in the lateral direction from the diffusion window 313. . Therefore, utilizing the fact that the breakdown voltage depends on the impurity concentration, the voltage of the diode is determined by forming the p anode region 309b at a position where the concentration of the n-type impurity has decreased to an appropriate value.

However, forming the n ⁺ wall region 306 having such a high impurity concentration and a predetermined concentration distribution in the lateral direction in a normal CMOS process involves a problem that the number of steps increases. In addition, it is difficult to reduce the manufacturing variation of the concentration gradient in the lateral direction, and the breakdown is apt to vary. Further, it is not clear how and what is formed by the reference numeral 320 corresponding to the spacer, and there is no description of the formation in a normal CMOS process. In addition, since the surface is not silicided, there is a problem that the resistance is increased and a current-voltage characteristic of a steep breakdown cannot be obtained.

[0010]

SUMMARY OF THE INVENTION The present invention has been made in view of such a problem, and it is possible to obtain an arbitrary desired breakdown voltage by the same process as the CMOS formation. An object of the present invention is to provide a semiconductor device having a diode having excellent characteristics and a method for manufacturing the same.

[0011]

SUMMARY OF THE INVENTION The present invention relates to a semiconductor device including a pn junction diode structure provided on a silicon substrate, wherein an n diffusion layer, a p diffusion layer and a p diffusion layer are formed on a silicon substrate on which a CMOS is formed. A semiconductor device including a diode structure provided on the surface of the substrate between the n-type diffusion layer and the p-type diffusion layer and having the same structure as the gate electrode of the MOSFET and having a predetermined length corresponding to the breakdown voltage. .

Further, according to the present invention, in a semiconductor device including a pn junction diode structure provided on a silicon substrate, an n diffusion layer, a p diffusion layer, and an n diffusion layer are formed on a silicon substrate on which a CMOS is formed. A plurality of diode structures are formed on the substrate surface between the layer and the p-diffusion layer and have the same structure as the gate electrode of the MOSFET and a spacer having a predetermined length corresponding to the breakdown voltage. The present invention relates to a semiconductor device including a diode structure, wherein breakdown voltages are set independently of each other.

In this case, at least a part of the plurality of diode structures is made back-to-b by making the n diffusion layer and the p diffusion layer common between adjacent diode structures.
Ack and head-to-head can be arranged in series.

In the present invention, it is further preferable that a silicide layer is formed on the surfaces of the n-type diffusion layer and the p-type diffusion layer.

In the present invention, the n-diffusion layer has an nMO
It is preferable that the p-type diffusion layer is formed simultaneously with the impurity diffusion layer of pMOS, and the p-type diffusion layer is formed simultaneously with the impurity diffusion layer of pMOS.

Further, according to the present invention, in a method of manufacturing a semiconductor device including a diode structure with a pn junction on a silicon substrate, the gate electrode of the CMOSFET is formed on the silicon substrate at the same time as the breakdown voltage of the same structure as the gate electrode of the MOSFET. Forming a spacer of a predetermined length corresponding to the above, and using the spacer as a mask, alternately covering the silicon substrate surfaces on both sides sandwiching the spacer with a resist, and ion-implanting on each side to obtain a diode structure. And a step of forming a p-type diffusion layer.

At this time, in the step of forming the n-type diffusion layer and the p-type diffusion layer having the diode structure, the formation of the n-type diffusion layer is performed simultaneously with the formation of the impurity diffusion layer of the nMOS.
It is preferable to form the diffusion layer simultaneously with the formation of the pMOS impurity diffusion layer.

Further, it is preferable to form a silicide layer on the surface of the n-diffusion layer and the p-diffusion layer of the diode structure.

In the present application, the n-diffusion layer and the p-diffusion layer indicate a cathode-side n-type impurity diffusion layer and an anode-side p-type impurity diffusion layer of a diode structure, respectively, unless otherwise specified.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 ((a) sectional view, (b) plan view) shows an example of a semiconductor device of the present invention. The semiconductor device of the present invention includes a CMOS structure and a diode structure on the same substrate. In the diode structure, an n diffusion layer 6 and a p diffusion layer 7 are provided on the surface of the silicon substrate 1 as shown in FIG. The spacer 2 is provided on the substrate surface between them. This spacer is a CMOSFET
It is made in the same shape as the electrode structure. However, MOS
Unlike an FET, this spacer is not used as an electrode, and no voltage is applied to the spacer.

When the normal formation method is used, the impurity is diffused and spreads to a part of the lower part of the spacer end in the n-type diffusion layer and the p-type diffusion layer as shown in FIG. If the subsequent annealing conditions are substantially the same, the distance between the n diffusion layer and the p diffusion layer is a length obtained by subtracting a constant lateral diffusion length from the spacer length L. Also, n
The surfaces of the diffusion layer and the p diffusion layer are silicided to form a silicide layer 3. In the example of this figure, an interlayer insulating film 4 is formed on the surface, and a contact 8 reaching the silicide layer 3 on the surface of the n-diffusion layer and the p-diffusion layer in the interlayer insulating film 4 and a wiring 9 connected to this contact are formed. Is provided. Further, the diode structure in this figure is separated by the LOCOS oxide film 5 so that only one is independent.

The breakdown voltage of the diode structure is
Although it can be adjusted by changing the impurity concentration, in the present invention, by changing the length L of the spacer, that is, n
It can be adjusted by changing the distance between the diffusion layer and the p diffusion layer.

In the present invention, the diode structure is preferably formed in a region of the silicon substrate which has not been subjected to ion implantation or the like. Although the diode structure may be formed in a well region formed in the silicon substrate, it is preferable that the impurity concentration is low enough that the breakdown voltage can be controlled by the distance between the n diffusion layer and the p diffusion layer. The concentration may be the same as that of a well in a region where a normal FET is formed, or may be formed in the same step as a normal well forming step. Also, there is no need for a lateral change in concentration on the surface in the well.

In forming such a semiconductor device of the present invention, a diode structure can be formed simultaneously when forming a CMOSFET formed on the same substrate. First, the spacer is formed exactly the same as the gate structure when forming the gate electrode of the CMOSFET. However, the opening of the resist is adjusted so that a desired voltage is obtained for the spacer length.

The n-diffusion layer and the p-diffusion layer are CMOSF
It is formed simultaneously when forming the source / drain regions of the ET. At this time, the breakdown voltage can be adjusted by separately ion-implanting impurities so as to have a concentration different from the impurity concentration of the source / drain regions.
Normally, it is preferable to form the source / drain regions of the CMOSFET at the same time as the source / drain regions and to adjust the breakdown voltage by the spacer length because the diode structure can be formed only by the CMOS process, so that the process is simplified.

The CMOSFET is an LDD (lig)
In the case of adopting an htly doped drain structure, ions are implanted into a shallow region and a deep region twice before and after forming a sidewall insulating film on a gate. In this case, an n diffusion layer having a diode structure is used. The p-type diffusion layer and the p-type diffusion layer may be formed by performing ion implantation simultaneously with ion implantation into a deep region.

Even in the case of such an LDD structure,
Since it is only necessary to change the area covered with the resist, the number of resist steps does not increase.

Further, the step of forming a silicide layer also includes
This can be performed simultaneously with silicidation of the surface of the source / drain region of the MOSFET.

Although only one diode structure is shown in FIG. 1, a large number of diode structures may exist on the silicon substrate. In this case, the spacer length must be set independently for each diode structure. Thereby, the required breakdown voltage can be obtained for each. If necessary, either the same voltage or a different voltage may be used.

As shown in FIG. 2 (plan view), an n diffusion layer (6-1 to 6-3) and a p diffusion layer (7-1 to 7-3)
Are alternately connected in series, the n-diffusion layer and the p-diffusion layer are made common to each other between adjacent diode structures, and the back-to-ba
ck and head-to-head. At this time, the length of the spacers (2-1 to 2-5) is
By changing L1 <L2 <L3 <L4 <L5, the breakdown voltages can be set independently of each other.

At this time, the breakdown voltages of the respective diode structures are formed so as to be different from each other. Further, as shown in FIG. 3, wirings 9 are provided in common to the n-diffusion layer and the p-diffusion layer, respectively. In order to obtain such a structure, a predetermined position of the wiring 9 made of, for example, Al may be blown by using, for example, a laser to leave a necessary diode structure.

[0032]

Next, the present invention will be described more specifically with reference to examples.

Embodiment 1 Referring to FIGS. 4 to 8,
The steps of this embodiment will be described. First, as shown in FIG. 4A, a LOCOS oxide film 5 is formed on the surface of a p-type silicon substrate 1 having an impurity concentration of about 1 × 10 ¹⁵ cm ⁻³ , and a plurality of active regions are separately formed. After a sacrificial oxide film is formed on the surface, ions are implanted into an nMOSFET formation region and a pMOSFET formation region to form a p-well 10 and an n-well (not shown), respectively. The well impurity concentration is 1 ×
It was set to 10 ^{17 to} 5 × 10 ¹⁷ cm ⁻³ . In this figure and the following figures, only the nMOSFET formation region 41 and the diode formation region 42 are shown, and the illustration of the pMOSFET formation region is omitted.

Thereafter, as shown in FIG. 4B, a gate oxide film 12 is formed on the surface of the substrate to a thickness of, for example, 4.0 nm, and a gate polysilicon 13 is formed on the gate oxide film 13 for a thickness of, for example, 200 nm.
Then, the gate polysilicon film 13 and the gate oxide film 12 are patterned to a predetermined length. Further, after a silicon oxide film is formed on the entire surface by CVD, the side wall oxide film 14 is formed by etching back, and the gate electrode 1 is formed.
5 is formed.

At this time, the diode forming region 42 also has
When patterning the gate polysilicon and the gate oxide film, by forming a resist mask so as to obtain a predetermined spacer length, the nMOSFET formation region 41 is formed.
Simultaneously with the formation of the gate electrode 15, the spacer 2 having the same structure (other than the gate length) is formed. Spacer L in this case
Is the length including the sidewall thickness of the sidewall oxide film, that is, the length serving as a mask at the time of the following ion implantation.

Next, as shown in FIG.
A photoresist 16 having an opening in the FET formation region 41 and an n-diffusion layer formation portion of the diode formation region 42 is formed on the substrate surface.
The source / drain region 18 of the nMOSFET is ion-implanted under the conditions of keV and a dose of 2 to 5 × 10 ¹⁵ cm ^−2.
And an impurity concentration of 1 × 10 ¹⁹ to 1 × 10
An n diffusion layer 6 of ²⁰ cm ^-3 is formed.

Next, as shown in FIG.
FET formation region (not shown) and diode formation region 4
Photoresist 1 having an opening in the portion where p diffusion layer 2 is formed
9 is formed on the substrate surface, for example, boron is ion-implanted under the conditions of an acceleration energy of 50 to 70 keV and a dose of 2 to 5 × 10 ¹⁵ cm ⁻² to form a source / drain region (not shown) of the pMOSFET. , Impurity concentration is 1
A p-diffusion layer 7 of × 10 ¹⁹ to 1 × 10 ²⁰ cm ⁻³ is formed (FIG. 5B). Thereafter, the photoresist is removed, and 8
A heat treatment is performed at 00 to 900 ° C. for several tens of minutes to activate the implanted impurities. With this, the basic structure of the diode is completed.

In the next step, as shown in FIG.
After the sacrificial oxide film 21 is formed on the surface, the surface of the diffusion layer is made amorphous to improve the reactivity with titanium described later. For example, arsenic is accelerated at an energy of 30 keV and a dose of 3 × 10 ¹⁴ cm ⁻² . Ion implantation under conditions, then
As shown in FIG. 6B, the sacrificial oxide film 21 is removed.

Next, as shown in FIG. 7A, a titanium film 22 is formed on the surface by sputtering. In addition to titanium, metals generally used for silicidation, such as cobalt, can be used. 70 by lamp annealing
Heat treatment is performed at 0 ° C. for several tens of seconds to perform silicidation. Then, when the unreacted titanium is removed by etching, FIG.
As shown in (b), a titanium silicide layer 23 is formed on the impurity diffusion layers (the n-type diffusion layer and the p-type diffusion layer of the diode structure, the source / drain regions of the MOSFET, and the gate polysilicon part of the gate electrode).

Next, as shown in FIG. 8, after depositing a silicon oxide film 24 as an interlayer insulating film to a thickness of about 1000 nm by the CVD method, the n-diffusion layer 6, p
After providing a diffusion layer 7 and a contact hole reaching the source / drain region of the MOSFET and embedding a metal, an Al wiring 25 is formed on the surface to form a semiconductor device of the present invention.

In the semiconductor device thus formed, when the spacer length of the diode structure is changed,
FIG. 9 shows the breakdown voltage. From this figure, it is understood that the breakdown voltage can be changed from about 5 V to about 30 V by changing the spacer length from 0.2 to 1 μm.

FIG. 10 shows the result of simulating the breakdown characteristics at the one-step plane shown in FIG. 1A, with and without silicidation of the surfaces of the n-type and p-type diffusion layers of the diode structure. FIG. 6 is a comparison of breakdown characteristics (current-voltage characteristics) at the time of the above. L was set to 0.3 μm. From this figure, even if the diodes show the same breakdown voltage, the silicified one can pass a large current,
It can be seen that the contact resistance can be reduced. This figure is 2
Since it is a result of dimensional simulation, the difference between silicidation and non-silicidation cannot be said to be extremely large. However, in a three-dimensional structure as an actual structure, the difference between the two is extremely large. It is easy to understand.

As described above, since the surface of the diffusion layer is silicided, the contact resistance can be reduced, so that the number of contacts can be reduced and the chip area can be reduced. Furthermore, there is no restriction on the contact position, and the degree of freedom in layout is improved. The characteristics of the diode structure of the present invention are such that the rise after breakdown is steep and the high-speed response is excellent.

[0044]

According to the present invention, it is possible to obtain a desired breakdown voltage by the same process as the CMOS formation, and to provide a semiconductor device having a diode with excellent characteristics and a method of manufacturing the same. be able to.

[Brief description of the drawings]

FIG. 1 is a diagram showing one example of a diode structure of a semiconductor device of the present invention. (A) sectional view (AA 'section in (b)), (b) plan view

FIG. 2 is a diagram showing one example of a diode structure of the semiconductor device of the present invention.

FIG. 3 is a diagram showing one example of a diode structure of the semiconductor device of the present invention.

FIG. 4 is a process sectional view illustrating the manufacturing method in the first embodiment.

FIG. 5 is a process sectional view illustrating the manufacturing method of the first embodiment, following FIG. 4;

FIG. 6 is a process sectional view illustrating the manufacturing method of the first embodiment, following FIG. 5;

FIG. 7 is a process sectional view illustrating the manufacturing method of the first embodiment, following FIG. 6;

FIG. 8 is a process sectional view illustrating the manufacturing method of the first embodiment, following FIG. 7;

FIG. 9 is a diagram showing a relationship between a spacer length and a breakdown voltage in the diode structure of the semiconductor device of the present invention.

FIG. 10 is a diagram showing current-voltage characteristics (simulation results) of the diode structure of the semiconductor device of the present invention.

FIG. 11 is a diagram showing a conventional diode structure.

FIG. 12 is a diagram showing a conventional diode structure.

FIG. 13 is a diagram showing a conventional diode structure.

FIG. 14 is a diagram showing a conventional diode structure.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 p-type silicon substrate 2 spacer 3 silicide layer 4 interlayer insulating film 5 LOCOS oxide film 6 n diffusion layer 7 p diffusion layer 8 contact 9 wiring 10 p well 12 gate oxide film 13 gate polysilicon 14 sidewall oxide film 15 gate electrode 16 photo Resist 18 Source / drain region of nMOSFET 19 Photoresist 21 Sacrificial oxide film 22 Titanium film 23 Titanium silicide layer 24 Silicon oxide film 25 Al wiring 41 nMOSFET formation region 42 Diode formation region

Claims (8)

(57) [Claims] In a semiconductor device including a diode structure with a pn junction provided on a silicon substrate, an n-diffusion layer, a p-diffusion layer, an n-diffusion layer and a p-diffusion layer are formed on a silicon substrate on which a CMOS is formed. Provided on the substrate surface between the layers,
A semiconductor device including a diode structure having the same structure as a gate electrode of a MOSFET and having a spacer having a predetermined length corresponding to a breakdown voltage. 2. A semiconductor device including a pn junction diode structure provided on a silicon substrate, comprising: an n-diffusion layer; a p-diffusion layer; Provided on the substrate surface between the layers,
A plurality of diode structures having the same structure as the gate electrode of the MOSFET and having a spacer having a predetermined length corresponding to the breakdown voltage are formed, and the breakdown voltage of each diode is set independently of each other. Semiconductor device including a diode structure. 3. At least a part of the plurality of diode structures includes an n-diffusion layer and a p-diffusion layer common between adjacent diode structures, and are connected in series in a back-to-back and a head-to-head manner. 3. The semiconductor device including the diode structure according to claim 2, wherein the semiconductor device is arranged side by side. 4. The semiconductor device according to claim 1, further comprising a silicide layer formed on a surface of said n-diffusion layer and p-diffusion layer. 5. The semiconductor device according to claim 1, wherein said n diffusion layer is formed simultaneously with an impurity diffusion layer of an nMOS, and said p diffusion layer is formed of pMO.
The semiconductor device including the diode structure according to claim 1, wherein the semiconductor device is formed simultaneously with the S impurity diffusion layer. 6. A method of manufacturing a semiconductor device including a diode structure with a pn junction on a silicon substrate, wherein a gate electrode of a CMOSFET is formed on a silicon substrate and a breakdown voltage corresponding to the same structure as the gate electrode of the MOSFET is applied. Forming a spacer of a predetermined length, using the spacer as a mask, alternately covering the silicon substrate surfaces on both sides sandwiching the spacer with a resist,
A method of manufacturing a semiconductor device including a diode structure, comprising: ion-implanting on each side to form an n-type diffusion layer and a p-type diffusion layer having a diode structure. 7. The step of forming an n-diffusion layer and a p-diffusion layer having a diode structure, wherein the n-diffusion layer is formed simultaneously with the formation of an impurity diffusion layer of an nMOS, and the p-diffusion layer is formed. 7. The method for manufacturing a semiconductor device including a diode structure according to claim 6, wherein the method is performed simultaneously with the formation of the pMOS impurity diffusion layer. 8. The method for manufacturing a semiconductor device including a diode structure according to claim 6, further comprising a step of forming a silicide layer on a surface of the n-type diffusion layer and the p-type diffusion layer of the diode structure.