JP2585684B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly, to a complementary integrated circuit device.
The present invention relates to a technology effective when applied to a semiconductor integrated circuit device having a MISFET (CMOS).

[Conventional technology]

A semiconductor integrated circuit device having a complementary MISFET is formed by the following manufacturing method.

First, an n-channel MISFET formation region and a p-channel MISF
A gate insulating film and a gate electrode are sequentially formed on the main surface of the semiconductor substrate (or well region) in the ET formation region.
Each of the n-channel MISFET formation region and the p-channel MISFET formation region is defined by an element isolation insulating film (field insulating film).

Next, a first impurity introduction mask (stopper layer) in which only the n-channel MISFET formation region is opened is formed. That is, the first impurity introduction mask is formed with a large area as a whole, covering the p-channel MISFET formation region (activation region) and the element isolation insulating film between the MISFETs. In a semiconductor integrated circuit device under development by the present inventor, an n-channel
Since the respective area ratios of the MISFET formation region, the p-channel MISFET formation region, and the element isolation insulating film are about 1: 1: 8, the n-channel MISFET formation region and the first impurity introduction mask are respectively provided. The area ratio is about 1: 9. First
The impurity introduction mask is formed of, for example, a photoresist film.

Next, using the first impurity introduction mask, an n-type impurity is introduced by ion implantation into the main surface portion (activation region) of the semiconductor substrate in the exposed n-channel MISFET formation region. This n-type impurity forms an n-type source region and a drain region.

Next, the second region in which only the n-channel MISFET formation region is covered
An impurity introduction mask is formed. The second impurity introduction mask is formed in a pattern inverted from the first impurity introduction mask, and has a small area as a whole, exposing the p-channel MISFET formation region and the element isolation insulating film. This second impurity introduction mask is formed of, for example, a photoresist film.

Next, using the second impurity introduction mask and the element isolation insulating film, a p-type impurity is introduced by ion implantation into the main surface portion (activation region) of the semiconductor substrate in the exposed p-channel MISFET formation region. This p-type impurity forms a p-type source region and a drain region.

[Problems to be solved by the invention]

In the method for manufacturing a complementary MISFET, an n-channel
The area of the first impurity introduction mask forming the source region and the drain region of the MISFET is large as described above. The impurity introduction mask is charged (charge amplifier) at the time of ion implantation. However, since the first impurity introduction mask has a large area, a large amount of charge is charged. When each gate electrode of the complementary MISFET is integrally formed, such as a CMOS inverter circuit, the gate electrode of the n-channel MISFET is exposed, and the gate electrode of the p-channel MISFET is covered with a first impurity introduction mask. The integrally formed gate electrode crosses the first impurity introduction mask edge (stopper boundary).
In such a state, the charge charged on the first impurity introduction mask is exposed from the first impurity introduction mask.
Discharged to the gate electrode of the channel MISFET, resulting in n
A phenomenon occurred in which a gate insulating film formed of a thin silicon oxide film of a channel MISFET was destroyed. This phenomenon occurs remarkably as the process becomes finer and the gate insulating film becomes thinner.

According to the basic research of the present inventors, p-channel MISF
Since the area of the second impurity introduction mask forming the source region and the drain region of the ET is small as described above, and the amount of charge charged to the second impurity introduction mask is small, the gate insulating film of the p-channel MISFET is not broken. The result was obtained. The same results were obtained when the respective patterns of the first impurity introduction mask and the second impurity introduction mask were inverted.

The inventor of the present invention separated each gate electrode of the complementary MISFET before introducing an impurity for forming a source region and a drain region, and after introducing the impurity, in order to prevent dielectric breakdown of the gate insulating film described above. The electrical connection of each gate electrode was studied. Each gate electrode of the complementary MISFET is electrically connected by a conductive layer above the gate electrode, for example, an aluminum wiring. However, such a method has a problem in that the area of the connection portion between the gate electrode and the upper conductive layer increases, so that the degree of integration decreases.

Regarding the destruction of the gate insulating film of MISFET, please refer to the monthly Semiconductor World
d), November 1987, pp. 35-37.

An object of the present invention is to provide a technique capable of preventing a dielectric breakdown of a gate insulating film of a MISFET in a semiconductor integrated circuit device having a complementary MISFET, which is caused by charging an impurity introduction mask during ion implantation. Is to do.

Another object of the present invention is to provide a technique capable of reducing the number of manufacturing steps for achieving the above object.

The above and other objects and novel features of the present invention are as follows.
It will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a typical invention disclosed in the present application is briefly described as follows.

In a semiconductor integrated circuit device having a complementary MISFET,
Forming a gate insulating film and a gate electrode of the first and second channel MISFETs of the complementary MISFET;
Only the ET formation region is covered with the first impurity introduction mask, and the second
Impurities for forming a source region and a drain region are introduced into the channel MISFET formation region by ion implantation, only the second channel MISFET formation region is covered with a second impurity introduction mask, and the source region and the drain are formed in the first channel MISFET formation region. An impurity for forming the region is introduced by ion implantation.

[Action]

According to the above-described means, the first impurity introduction mask is formed in a small size to cover the first channel MISFET formation region, and the second impurity introduction mask is formed in the second channel MISF.
The ET formation region is formed in a small size to cover the ET formation region, and the amount of electric charge charged to the first and second impurity introduction masks at the time of ion implantation is reduced, so that the dielectric breakdown of the respective gate insulating films of the first and second channel MISFETs can be prevented. Can be prevented.

Hereinafter, the configuration of the present invention will be described together with an embodiment in which the present invention is applied to a semiconductor integrated circuit device having a complementary MISFET.

In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted.

(Example of the invention)

Complementary type of semiconductor integrated circuit device according to one embodiment of the present invention
FIG. 1 (plan view) and FIG. 2 (II shown in FIG. 1) show the MISFET.
-II sectional view taken along the section line).

As shown in FIGS. 1 and 2, the n-channel MISFET Qn of the complementary MISFET is a p ^- type semiconductor substrate 1 made of single crystal silicon.
The main surface is configured. P-channel MI of complementary MISFET
SFET Qp is formed on the main surface of n ⁻ type well region 2.

The n-channel MISFETQn is formed on a main surface in a region (activation region) of which the periphery is defined by an element isolation insulating film (field insulating film) 3 of the semiconductor substrate 1. In other words, the n-channel MISFETQn includes the semiconductor substrate (channel formation region) 1, the gate insulating film 4, the gate electrode 5, and a pair of n ⁺ -type semiconductor regions 6 serving as a source region and a drain region. The gate insulating film 4 is formed of, for example, a silicon oxide film formed by oxidizing a main surface of the semiconductor substrate 1,
It is formed with a thickness of about 300 [Å]. The gate electrode 5
For example, formed of a polycrystalline silicon film deposited by CVD, 3000
It is formed with a film thickness of about 4000 [Å].

The p-channel MISFET Qp is formed on a main surface in a region (activation region) whose periphery is defined by the element isolation insulating film 3 in the well region 2. The p-channel MISFET Qp includes a well region (channel forming region) 2, a gate insulating film 4, a gate electrode 5, and a pair of p ⁺ -type semiconductor regions 7 serving as a source region and a drain region.

Semiconductor region 6 of n-channel MISFETQn, p-channel MISF
Although not shown, each of the semiconductor regions 7 of the ETQp is configured to be connected to a metal wiring. The metal wiring is formed, for example, of aluminum on the gate electrode 5. As shown in FIG. 1, a CMOS inverter circuit, which constitutes a basic cell such as a gate array,
Gate electrode 5 of n-channel MISFETQn and p-channel MISFET
The gate electrode 5 of Qp is integrally formed.

Next, the method of manufacturing the complementary MISFET described above will be described in the third section.
A brief description will be given with reference to FIGS. 5 to 5 (cross-sectional views showing respective manufacturing steps).

First, a p ^- type semiconductor substrate 1 made of single crystal silicon is prepared.

Next, in the p-channel MISFET Qp formation region, an n ⁻ -type well region 2 is formed on the main surface of the semiconductor substrate 1.

Next, an inter-element isolation insulating film 3 is formed on the respective main surfaces of the semiconductor substrate 1 and the well region 2 between the MISFET formation regions. The element isolation insulating film 3 includes, for example, the semiconductor substrate 1,
Each of the well regions 2 is formed of a silicon oxide film formed by oxidizing the main surface thereof, and is formed to have a large thickness of about 6000 to 8000 [Å].

Next, as shown in FIG. 3, the gate insulating film 4 and the gate electrode 5 are formed on the main surface of the semiconductor substrate 1 in the n-channel MISFETQn formation region and on the main surface of the well region 2 in the p-channel MISFETQp formation region, respectively. Are sequentially formed.

Next, as shown in FIG. 4, only the p-channel MISFET Qp formation region is covered with the impurity introduction mask 8, and an n-type impurity (As or P) 9n is ion-implanted to form the main portion of the semiconductor substrate 1 in the n-channel MISFET Qn formation region. The n ⁺ -type semiconductor region 6 used as a source region and a drain region is formed in the surface portion (activation region). When introducing the n-type impurity 9n, in addition to the impurity introduction mask 8, the element isolation insulating film 3 and the gate electrode 5 are used as an impurity introduction mask (stopper layer). That is, the semiconductor region 6 can be formed mainly by self-alignment with the gate electrode 5.

4 and FIG.
As shown in the figure, the p-channel MISFETQp
N-channel MISFET covering only the formation region (activation region)
The Qn formation region and the element isolation insulating film 3 are formed so as to be exposed. That is, the impurity introduction mask 8 is formed with a minimum size so as not to introduce the n-type impurity 9n into the p-channel MISFET Qp formation region. Further, the impurity introduction mask 8 is formed with a minimum size so that the amount of charge charged during ion implantation is minimized.
Specifically, the impurity introduction mask 8 is a p-channel MISFET
It is formed to have a size equal to or larger than the size of the Qp formation region plus a mask alignment margin in the manufacturing process of the p-channel MISFET Qp formation region and the impurity introduction mask 8. The mask alignment margin ranges from sub-micron meters to several microns-meters. Further, the impurity introduction mask 8 is formed with a size not exceeding 100 times the area of the gate insulating film 4 (equivalently, the area of the gate electrode 5 in the activation region) based on the basic research of the present inventor. I have. The impurity introduction mask 8 is formed of, for example, a photoresist film patterned by a photolithography technique. By forming the semiconductor region 6, the n-channel MISFETQn is completed.

Next, similarly, as shown in FIG.
Only the ETQn formation region is covered with an impurity introduction mask 10, and a p-type impurity (B or BF ₂ ) 11p is ion-implanted into a p-channel MI.
Main surface portion of well region 2 in SFET Qp formation region (activation region)
To form ap ⁺ type semiconductor region 7 used as a source region and a drain region. When introducing the p-type impurity 11p, in addition to the impurity introduction mask 10, the element isolation insulating film 3 and the gate electrode 5 are used as an impurity introduction mask (stopper layer). That is, the semiconductor region 7
Can be formed mainly by self-alignment with the gate electrode 5.

5 and FIG.
As shown by a dashed line in the figure, similarly to the impurity introduction mask 8, only the n-channel MISFETQn formation region (activation region) is covered, and the p-channel MISFETQp formation region and the element isolation insulating film 3 are exposed. It is formed as follows. That is, the impurity introduction mask 10 is formed in a minimum size so as not to introduce the p-type impurity 11p into the n-channel MISFET Qn formation region and to minimize the amount of charge charged during ion implantation. The impurity introduction mask 10 is formed of, for example, a photoresist film patterned by a photolithography technique. By forming the semiconductor region 7, the p-channel MISFET Qp is completed.

The introduction of each of the n-type impurity 9n and the p-type impurity 11p is performed through an insulating film formed on each main surface of the semiconductor substrate 1 and the well region 2. This is performed to reduce heavy metal contamination and damage to the silicon surface due to ion implantation.

As described above, in the semiconductor integrated circuit device having the complementary MISFET, each of the gate insulating film 4 and the gate electrode 5 of the n-channel and the p-channel MISFET of the complementary MISFET is sequentially formed, and the p-channel MISFET Qp formation region is formed. Only the n-type MISFETQn forming region is covered with an impurity introducing mask 8 and an n-type impurity 9n for forming a source region and a drain region (semiconductor region 6) is introduced into the n-channel MISFETQn forming region by ion implantation. The p-type impurity 11p that forms the source and drain regions is implanted into the p-channel MISFET Qp formation region by ion implantation so that the impurity introduction mask 8 has a small size that covers the p-channel MISFET formation region Qp. And the impurity introduction mask 10 is formed in a small size to cover the n-channel MISFETQn formation region. Having reduced the amount of charge charged to each of the pure ones introducing mask 8, 10, n-channel, p-channel MISFET Qn, the dielectric breakdown of the gate insulating film 4 of each of Qp can be prevented.

In addition, since each of the impurity introduction masks 8 and 10 only changes its shape, the number of manufacturing steps for achieving the above-mentioned effect does not increase.

In the present invention, the step of forming the n-channel MISFETQn and the step of forming the n-channel MISFETQp may be interchanged.

In addition, the present invention provides an LDD ( L i) in which two or more types of ion implantation are implanted, and a double diffusion layer structure (double drain structure) or a channel formation region having a low impurity concentration.
It can be applied to a semiconductor integrated circuit device having a complementary MISFET of ghtly D oped D rain) structure.

As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and can be variously modified without departing from the gist thereof. Of course.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows.

It is possible to prevent dielectric breakdown of a gate insulating film of a semiconductor integrated circuit device having a complementary MISFET.

[Brief description of the drawings]

FIG. 1 is a plan view showing a complementary MISFET of a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of the complementary MISFET shown in FIG. 1 taken along the line II-II. FIGS. 3 to 5 are cross-sectional views showing the complementary MISFET in each manufacturing process. In the figure, 1 ... semiconductor substrate, 2 ... well region, 3 ... element isolation insulating film, 4 ... gate insulating film, 5 ... gate electrode, 6,7 ... semiconductor region, 8,10 ... Impurity introduction masks, 9n, 11p... Impurities, Qn, Qp.

Claims (2)

(57) [Claims] 1. A semiconductor substrate having a first surface of a different conductivity type on a main surface thereof.
A method for manufacturing a semiconductor integrated circuit device having a region and a second region, wherein a step of forming an element isolation insulating film for partitioning the first region and the second region on a main surface of a semiconductor substrate; A step of forming a gate insulating film on each main surface of the region; a step of forming a gate electrode on each gate insulating film of the first region and the second region; Expose the membrane,
Covering the second region with a first impurity introduction mask, introducing an impurity into the first region by ion implantation, exposing the second region and the element isolation insulating film,
A step of covering the first region with a second impurity introduction mask; and a step of implanting an impurity into the second region by ion implantation. In the mask covering step, a first impurity introduction mask and a second impurity introduction mask are provided. A method for manufacturing a semiconductor integrated circuit device, comprising forming a pattern so that a portion not covered by any of the masks is interposed in the inter-element isolation insulating film. 2. The method according to claim 1, wherein each of the first and second impurity introduction masks is formed in consideration of a mask alignment margin in a manufacturing process with respect to a size of each formation region. A manufacturing method of the semiconductor integrated circuit device according to the above.