JPS62169468A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce chip space while restraining the element performance from deteriorating due to hot carrier by a method wherein the drains of the first and the second electric field effect transistors are respectively formed of one and two layered diffused layers. CONSTITUTION:An element isolation region 102 is formed on a P type silicon substrate 101; gate silicon oxide film 103 are provided; and polycrystalline silicon gate electrode 104 are formed. The left side circuit part is covered with a resist 105 and implanted with P ion 108 in low dosage to form an N-diffusion layer 106 by heat treatment and then the resist 5 is removed. Next, overall surface is implanted with As ion 109 in high dosage to form an N<+> diffusion layer 107 by heat treatment. Through these procedures, an N channel field effect transistor mainly comprising a memory cell operating at low voltage to be miniturized is formed on the left side while another N channel field effect transistor comprising the other circuits operating at high voltage not to be miniaturized so strictly is formed on the right side.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device in which device performance is less degraded by hot carriers.

[Conventional technology]

With the development of silicon MO8 technology, increasingly fine MIS field effect transistors are being used in silicon integrated circuit devices. Along with this, deterioration of device performance due to hot carriers has become a problem. Conventionally, in order to prevent deterioration of device performance due to these hot carriers, it has been proposed to use methods such as 657).

[Problem that the invention seeks to solve]

The conventional LDD and DDD structures described above require a spacer to be self-aligned on the sidewall of the gate electrode, or an n- region formed outside the n+ diffusion layer of a normal transistor by thermal diffusion, so it is difficult to reproduce the structure. The drawback is that it is difficult to obtain a small field effect transistor with a small area from the viewpoint of performance and mass production.

[Means for solving problems]

The present invention provides a semiconductor integrated circuit device using MIS type field effect transistors, in which there is a strong demand for miniaturization of the semiconductor integrated circuit device, but a first circuit section that operates at low voltage;
The second type, which does not require much finer purification but operates at high voltage,
In the first circuit section, the drain of the field effect transistor constituting the circuit is formed of one layer of impurity diffusion layer, and in the second circuit section, the drain of the field effect transistor constituting the circuit is formed of one layer of impurity diffusion layer. It is characterized by being formed of two impurity diffusion layers, one with a low concentration and one with a high concentration.

〔Example〕

An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a cross-sectional view of each manufacturing process according to an embodiment of the present invention. There is a strong demand for miniaturization on the left side of the element isolation region, but there is a strong demand for miniaturization on the right side of the n-channel field effect transistor, which constitutes the circuit section whose main part is a memory cell that operates at low voltage. This figure shows an n-channel field effect transistor that constitutes a circuit in a circuit section other than that which operates at a high voltage. Here, a DI)D structure is taken as an example of the transistor in the right circuit section.

After forming the element isolation region 102 on the P-type silicon substrate 101 as shown in FIG.
[103 is provided, and a polycrystalline silicon gate electrode 104 is formed. After that, as shown in the same figure (bl), resist coating,
After exposure and development, the left side circuit portion is covered with a resist 105, and a low dose of phosphorus (or ions) is implanted 108.

Thereafter, as shown in FIG. 4C, heat treatment is performed to form an n'''' diffusion layer 106, and the resist is removed. Next, as shown in FIG. 10(d), a high dose of arsenic (As) is ion-implanted 109L, and heat treatment is performed to form an n+ diffusion layer 107 as shown in FIG. 2(e)K. Thereafter, by performing normal manufacturing processes, it is possible to complete the n-channel field effect transistors forming the circuits of each circuit section.

〔Effect of the invention〕

As explained above, the present invention divides an integrated circuit device into two circuit parts, and forms the drain of the n-channel field effect transistor, which constitutes the circuit in the circuit part where miniaturization is strongly required, with a single impurity diffusion layer. By forming the drain of an n-channel field effect transistor, which constitutes a circuit section that is essential for preventing hot carriers from a structural standpoint, with two layers of impurity diffusion layers, one with low concentration and the other with high concentration, deterioration of device performance due to hot carriers can be prevented. A semiconductor integrated circuit device with a small chip area and a small chip area can be obtained.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a process of manufacturing an n-channel field effect transistor according to an embodiment of the present invention. 101...Silicon single crystal substrate, 102...
...Element isolation region, 103...Silicon oxide film, 104...Gate electrode, 105...
・Resist, 1o6...n-diffusion layer, 107・
...n+ diffusion layer, 108...phosphorus implantation,
109...Arsenic injection.

Claims (1)

[Claims] In a semiconductor integrated circuit device using MIS type field effect transistors, there is a first circuit section which is strongly required to be miniaturized but operates at low voltage, and a first circuit section which is not required to be miniaturized but operates at high voltage. The drain of the field effect transistor constituting the first circuit section is formed of a single layer of impurity diffusion layer, and the drain of the field effect transistor constituting the second circuit section is formed of a layer of impurity diffusion. A semiconductor integrated circuit device characterized in that it is formed of two layers of impurity diffusion layers: a high concentration impurity diffusion layer and a high concentration impurity diffusion layer.