JPH0287567A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To introduce simultaneously N-type and P-type impurities and to contrive the improvement of quality of a semiconductor device by a method wherein N-type impurity-doped and P-type impurity-doped oxide films are respectively adhered on an N-channel MIS region and a P-channel MIS region and are heat-treated. CONSTITUTION:An N-type impurity and a P-type impurity are respectively implanted in N-channel and P-channel MOS regions on a P-type silicon substrate 1 and N-type impurity diffused layers 11 and P-type impurity diffused layers 12 are formed. Moreover, a poly silicon layer 7 is laminated, an N-type impurity- doped PSG oxide film 13 is laminated on the whole and an impurity-undoped oxide film 14a is laminated thereon. Then, the films 13 and 14a on the P-channel MOS region only are removed, a P-type impurity-doped BSG oxide film 15 is laminated on the whole and an impurity-undoped oxide film 14b is laminated thereon. After that, an annealing (a heat treatment) is conducted.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a technique that is effective when applied to a method of manufacturing a semiconductor device.
The present invention relates to a technique that can be effectively used in a method of manufacturing a semiconductor device in which an IS and a p-channel MIS are respectively formed.

[Prior Art] Conventionally, n-channel MO8 was the mainstream type of semiconductor device, but as the degree of integration increases, heat generation has become an important issue, so in recent years, CM with low power consumption has been used. OS (Complementary)
MOS) has come to be widely used.

Regarding the manufacturing process of this so-called CMO8, for example,
It is described on pages 126 to 129 of the 2nd edition of the first edition of "Ultra High Speed MOS Devices" published by Baifukan Co., Ltd. on December 15, 1986.

The outline of the manufacturing process of this CMO8 is as follows.

For example, when using a p-type silicon substrate as a semiconductor substrate, first an n-well is formed, and then a thick field oxide film and a channel stopper layer are formed under the field oxide film, and each region of NMO8 and PMO5 is formed. Inject channel ions into the Next, after forming a gate electrode doped with impurities, source and drain diffusion layers are formed in each of the NMO5 and PMO5 regions. Then, an insulating film is applied over the entire structure, contact holes are opened, wiring is made of aluminum, for example, and then a protective film is applied over the entire structure.

Here, in a semiconductor device consisting of only one of NMO5 and PMOS, polycrystalline silicon into which an impurity of the same conductivity type as the diffusion layer is introduced between the diffusion layer and the wiring metal is used. A pad is provided, and the electrode of the diffusion layer is led out through the pad.

Without directly drawing out the electrodes of this diffusion layer using wiring metal,
The reason why it was drawn out through the pad is as follows.

In other words, when the wiring metal is brought into direct contact with the diffusion layer without providing a pad, the alignment margin between the contact hole and the gate must be made so that the contact hole filled with the wiring metal does not touch the gate. It has to be large, which hinders miniaturization and high integration of semiconductor integrated circuits. On the other hand, if the pad formed by self-line on the oxide film covering the gate electrode is provided so as to overlap with the gate electrode, it is necessary to consider the alignment margin between the contact hole and gates 1 to 1. will disappear. In other words, when such a pad is provided, it is provided so that the contact hole overlaps the gate electrode, so that the semiconductor integrated circuit can be miniaturized and highly integrated.

The introduction of this pad is a combination of NMO3 and PMOS.
The same is desired for MO3.

[Problems to be Solved by the Invention] However, when the above pad is introduced into the CMO 8, there are the following problems.

In other words, since it is necessary to introduce n-type impurities into the polycrystalline silicon layer that forms the pad of the NMO8 region and p-type impurity into the polycrystalline silicon layer that forms the pad of the PMO3 region, -degree thermal diffusion is required. If an attempt is made to introduce an impurity into a pad using a method, for example, if an n-type impurity is thermally diffused, the n-type impurity will also be introduced into the butt of the PMOS region, causing a problem between the diffusion layer and the pad. A pn junction is formed in this case.

Therefore, it is necessary to introduce impurities into the pads in the NMO3 region and the pads in the PMO8 region in two separate steps.In this case, the pads in the regions that were previously heat-treated should be heat-treated twice. This makes it extremely difficult to control the concentration of impurities, which poses a quality problem.

Here, it is possible to add impurities to the pad using ion implantation, but the amount of impurity implanted into the sidewalls of the pad is small, and a reaction between the silicon that makes up the pad and the metal occurs in the neck. This is not preferable because contact resistance increases due to silicon precipitation and metal disconnection occurs at the sidewall portion.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can uniformly introduce impurities into pads and improve quality.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, oxide films doped with p-type and p-type impurities are deposited on the n-channel MIS and p-channel MS regions, respectively, and heat treated to form the n-channel MIS.
n-type impurities are simultaneously introduced into the polycrystalline silicon in the region where the MIS is to be formed, and p-type impurities are simultaneously introduced into the polycrystalline silicon in the region where the n-channel MIS is to be formed. .

[Function] According to the above-described means, when heat treatment is performed while polycrystalline silicon and the oxide film doped with impurities are in contact with each other, the impurities are uniformly diffused into the polycrystalline silicon, thereby reducing NMIS. N-type impurities are uniformly introduced into the pads within the region, and P-type impurities are uniformly introduced into the pads within the PMIS region, thereby achieving the above-mentioned objective of improving quality.

[Example] Hereinafter, an example of the method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.

FIG. 2 shows an embodiment of a semiconductor device according to the present invention.

The semiconductor device of this embodiment is a so-called CMO5 type semiconductor device, and has an n-channel MO8 and a p-channel MO8 formed on the same substrate.

An example of a method for manufacturing the semiconductor device of the above embodiment will be described below.

For example, when using a p-type silicon substrate as a semiconductor substrate, first, an n-well 2 is formed on the p-type silicon substrate 1, and by providing this n-well 2, the surface of the substrate 1 is divided into an NMOS region and a PMOS region. Separate into Next, element isolation is performed by providing a thick field oxide film 3 and a channel stopper layer 4 under this field oxide film 3, and then exposing the substrate surface and oxidizing the silicon surface to form a gate oxide film 5. . Channel ions are implanted into the NMOS and PMO 3 regions through this gate oxide film 5. Next, a gate electrode 6 doped with impurities and an interlayer oxide film 8 on the gate electrode 6 are formed, and NM is formed using the gate electrode 6 and field oxide film 3 as masks.
N-type impurities and p-type impurities are lightly implanted into each of the OS and PMO3 regions. Then, as shown in Figure 3,
An oxide film 16 is laminated on the entire surface by, for example, a CVD method,
By processing with anisotropic etching.

Forming a sidewall 16 as shown in FIG. 4,
Again, n-type impurities and p-type impurities are implanted into each of the NMOS and PMO3 regions to form an n-type impurity diffusion layer 11 and a p-type impurity diffusion layer M12 that will serve as the source/drain, respectively. n
As the type impurity, for example, arsenic is used, and as the p-type impurity, for example, boron is used. When implanting n-type impurities into the NMOS region, a mask is applied to the PMO3 region, and when implanting p-type impurities into the PMO8 region, a mask is applied to the NMOS region.

The following are the steps that are characteristic of the present invention. First, as shown in FIG.
Laminated by method. Next, an oxide film doped with phosphorus as an n-type impurity, the so-called PSG oxide film 13, is laminated over the whole, and an oxide film 14a to which no impurity is added is formed on top of the so-called PSG oxide film 13.
Laminate. The PSG oxide film 13 and oxide film 14a are formed by, for example, a CVD method. Next, using a photoresist as a mask, only the PMOS region is covered with the PSG oxide film 13. The oxide film 14a is removed. And this time,
Oxide film doped with boron, a P-type impurity, so-called BS
A G oxide film 15 is laminated over the entire surface, and an oxide film 14b to which no impurity is added is laminated thereon. The formation of the BSG oxide film 15 and the oxide film 14b includes the formation of the PSG oxide film 13, the oxide film 14. Similar to the formation of a, the CVD method is used. after that.

For example, annealing for 30 minutes at a temperature of 950°C (
heat treatment).

Here, if heat treatment is performed with the polycrystalline silicon layer and the oxide film to which impurities are added, the impurities in the oxide film will be diffused into the polycrystalline silicon layer, so the PSG oxide film The n-type impurity in 13 is added to the polycrystalline silicon layer 7 in the NMOS region, and the p-type impurity in the BSG oxide film 15
The type impurities are each diffused into the polycrystalline silicon layer 7 within the 2MO8 region. Since the impurity is diffused into the polycrystalline silicon layer 7 by heat treatment, the impurity is also diffused into the side wall portion 7a of the polycrystalline silicon layer 7 in the same way as in the flat portion.

In this way, after diffusing impurities into the polycrystalline silicon layer 7 and lowering the resistance of the polycrystalline silicon N7, for example,
The PSG oxide film 13, BSG oxide film 15, and non-additive oxide film 14a are formed using an HF-based liquid.

14b is removed.

Thereafter, in the same manner as before, this polycrystalline silicon layer 7 with reduced resistance is patterned to form a desired pad 7b as shown in FIG. 2, and then, for example, by CVD method. A PSG film 9 as an insulating film is deposited over the entire structure, and a contact hole is opened. After the formation of this contact hole is completed, a wiring layer 10 made of aluminum, for example, is formed and processed to form the
The MO8 type semiconductor device is completed.

In addition, as shown in an enlarged view in FIG. 3, the above-mentioned glabellar oxide film 8 is coated with a silicon oxide film 8a, on the electrode 6 to the gate 1.
The nitride film 17 and the silicon oxide film 8b are sequentially laminated by, for example, the CVD method.

By processing using reactive ion etching (RIE) technology, a nitride film 17 may be interposed within the glabellar oxide film 8, as shown in FIG. In this way, the interlayer oxide film 8 and the sidewall 16
Since the shoulder part of the insulating film consisting of is reinforced,
The breakdown voltage between pad 7b and gate electrode 6 can be improved.

As a result, according to the method of manufacturing a semiconductor device of the above embodiment, the following effects can be obtained.

That is, as shown in FIG. 1, a PSG oxide film 13 is formed on the polycrystalline silicon 7W7 in the NMOS region;
Since the BSG oxide film 15 is laminated on each polycrystalline silicon layer 7 in the PMO 8 region and the heat treatment is performed in this state, the polycrystalline silicon layer 7 and the impurity-added oxide film 13.15 are in contact with each other. When heat treatment is performed in this state, the impurity diffuses uniformly into the polycrystalline silicon layer 7, so that the n-type impurity is contained in the polycrystalline silicon layer 7 in the NMO5 region and the polycrystalline silicon in the PMO8 region. The p-type impurity is uniformly added and diffused into the layer 7, and the quality can be improved.

In this way, according to this embodiment, it became possible for the first time to form a highly reliable pad in a CMO8 type semiconductor device.

Furthermore, in this embodiment, the PSG oxide film 13 and the BSG
Since the additive-free oxide film 14a is provided between the oxide film 15, phosphorus and BS in the PSG oxide film 13 are separated during heat treatment.
Mutual diffusion with boron in the G oxide film 15 is prevented.

Further, since the additive-free oxide film 14b is provided on the BSG oxide film 15, out-diffusion of boron in the BSG oxide film 15 during heat treatment is also prevented.

FIG. 5 shows another CMOS obtained by applying the same example.
A longitudinal cross-sectional view of the transistor is shown.

The 0MO8 type semiconductor device of this embodiment is different from that shown in FIG. Silicon J! ! These are the points connected by 77c. The addition and diffusion of impurities into this polycrystalline silicon 17c is done in exactly the same manner as described above.
The n-type impurity is on the N-channel MO8 side, and the P-channel M
A P-type impurity will be introduced to the O5 side.

It goes without saying that this embodiment can obtain the same effect as the previous embodiment, and has the further advantage that the polycrystalline silicon layer 7c doped with and diffused with impurities can be used as a wiring. .

In this embodiment, the n-swell diffusion layer and the p-swell diffusion layer are connected by the polycrystalline silicon layer 7C, but the n-type wave diffusion layers or the p-swell diffusion layers are connected to each other by the polycrystalline silicon layer. It is also possible to connect by 7C.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, in the above embodiment, a type of CMOS, S, in which an n-well is formed on a p-type silicon substrate is described, but conversely, a type of CMOS, in which a p-well is formed on an n-type silicon substrate, is also described. Equally applicable,
It is also applicable to twin tab type CMOS.

Furthermore, in the above embodiment, the polycrystalline silicon doped with impurities is stacked in the order of the PSG oxide film 13 and the BSG oxide film 15, but it goes without saying that the order may be reversed. Nor.

Note that, depending on the case, the PSG oxide film and BSG oxide film used as the diffusion source may be used as they are as the glabellar insulating film.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, oxide films doped with n-type and p-type impurities are deposited on the n-channel MIS and p-channel MIS regions, and heat-treated to form the n-channel MIS.
By simultaneously introducing n-type impurities into the polycrystalline silicon in the region where the MIS will be formed and p-type impurities into the polycrystalline silicon in the region where the p-channel MIS will be formed, When heat treatment is performed with crystalline silicon and an oxide film doped with impurities in contact with each other, the impurities diffuse uniformly into the polycrystalline silicon, so that n-type impurities are added to the polycrystalline silicon in the NMIS region. , p-type impurities are uniformly introduced into the polycrystalline silicon in the PMIS region, thereby improving quality.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a step of laminating an oxide film doped with impurities in an embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIG. 2 is a CMOS type semiconductor device obtained by applying the same embodiment. Longitudinal cross-sectional view. FIGS. 3 and 4 are views showing the sidewall forming process of the above embodiment, respectively, and FIG. 5 is a longitudinal sectional view of another CMO8 type semiconductor device obtained by applying the above embodiment. 7.7b, 7c...polycrystalline silicon, 11...
n-channel MO8 diffusion layer, 12...p-channel MO
8 diffusion layer, 13... oxide film doped with n-type impurity, 15... oxide film doped with p-type impurity. Figure 1 /Z/) Geo vqZs is on guard

Claims (1)

[Claims] 1. In introducing impurities of the same conductivity type as the contacting diffusion layers into the polycrystalline silicon that contacts the diffusion layers constituting the n-channel MIS and the p-channel MIS,
An oxide film doped with n-type and p-type impurities is deposited on the n-channel MIS and p-channel MIS regions, and heat-treated to form an n-type oxide film on the polycrystalline silicon in the region where the n-channel MIS is to be formed. impurities in the form,
A method for manufacturing a semiconductor device 2, characterized in that a p-type impurity is simultaneously introduced into polycrystalline silicon in a region where the p-channel MIS is to be formed, the polycrystalline silicon forming a pad or wiring. A method of manufacturing a semiconductor device according to claim 1, characterized in that: 3. The method of manufacturing a semiconductor device according to claim 1 or 2, wherein a PSG oxide film and a BSG oxide film are used as the oxide film.