JPS627701B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit having complementary insulated gate field effect transistors capable of high speed and high integration, and a method of manufacturing the same.

Complementary insulated gate field effect transistors (hereinafter abbreviated as CMS transistors), which are a combination of N-channel and P-channel insulated gate field effect transistors, are widely used in low-power integrated circuits, linear circuits, and the like. Conventionally, this device has had the structure shown in FIG. That is, a P-channel transistor is formed in an n-type substrate 1, an N-channel transistor is formed in a p-type region 2 formed in the substrate 1, and a guard band (high concentration p N-type regions 3, 4 and high concentration n-type regions 5, 6) are formed. Furthermore, the channel length of each of the N-channel and P-channel transistors is relatively long, about 5 μm or more. Therefore, when the CMS transistor having the conventional structure described above is used to form an integrated circuit, the degree of integration is low, and furthermore, it is difficult to increase the speed. It is already known that in order to remove the guard band, a method of locally forming a thick oxide film using a silicon nitride film (hereinafter abbreviated as selective oxidation method) is used to improve the degree of integration ( For example, "Electronic Materials" 1974
(May 2015, P12-P15), In order to further increase integration and speed, it is necessary to shorten the channel length of MS transistors. In the CMS transistor of the conventional structure shown in Fig. 1,
When the channel length is shortened to, for example, 5 μm or less, the impurity concentration of the P-channel transistor is approximately
Since it is formed on the n-type substrate 1 with a low value of 10 ¹⁵ cm ^-3 , the electric field from the drain affects the channel region under the gate oxide film 21, resulting in a decrease in breakdown voltage due to the punch-through phenomenon and a threshold increase due to the electric field from the drain. This causes a decrease in the value voltage Vth, and the operation as a transistor is significantly impaired.

The purpose of the present invention is to improve the shortcomings of the above-mentioned prior art and to provide a short channel CMS that is capable of high speed and high integration.
An object of the present invention is to provide a semiconductor integrated circuit having a transistor and a method for manufacturing the same. In the present invention, in order to achieve this object, the periphery and bottom surface of both the source and drain of the N-channel and P-channel transistors constituting the CMS transistor are of a conductivity type opposite to that of the source and drain, and are higher than the substrate. It is surrounded by a region having a high impurity concentration, and is further characterized in that this region having a high impurity concentration is formed by adding impurities through a window of the field oxide film after growing a thick field oxide film. It is said that

Furthermore, the present invention is characterized in that when a memory section is provided in a semiconductor integrated circuit, the memory cells of the memory section are also surrounded by a region having a higher impurity concentration than the substrate. That is, according to the present invention, an excellent semiconductor memory integrated circuit using CMOS transistors can be realized.

Hereinafter, the present invention will be explained in detail with reference to Examples. Note that the following description will be made using a CMS transistor using silicon as a semiconductor as an example.

FIG. 2 shows a first embodiment of the present invention, and both N-channel and P-channel MS transistors have an impurity concentration of a substrate 22 (for example, 10 ¹⁵ cm ^-3 or less).
Impurity concentration higher than (e.g. 10 ¹⁶ cm ^-3 :
In practical terms, the impurity concentration in the well is approximately 5×10 ¹⁵ to 5
The characteristics of the element within the range of approximately ×10 ¹⁶ cm ^-3 For example,
It may be designed based on the threshold voltage, etc. ) are formed in the wells 23, 24. Therefore, in each transistor, the influence of the electric field from the drain on the channel region becomes small, and even if the channel length of each transistor is set to 5 μm or less, a decrease in breakdown voltage and a decrease in threshold voltage Vth due to the punch-through phenomenon are unlikely to occur. Furthermore, since each transistor is located in a well with a relatively high impurity concentration, the threshold voltage of the thick field oxide films 34, 35, and 36 in the well is also approximately 20V or higher, which is different from the conventional structure shown in FIG. Even without forming a guard band, the generation of parasitic MOS transistors can be prevented. In the structure shown in FIG. 2, the conductivity type of the substrate 22 may be n-type or p-type as long as its impurity concentration is lower than that of the wells 23 and 24. Even if the gate oxide film is thinned to less than 1000 Å, the threshold voltage of N-channel and P-channel MOS transistors can be easily enhanced to an absolute value of about 1 V by increasing the well impurity concentration. It is possible.

FIG. 3 shows a second embodiment of the invention. The CMS transistor shown in FIG. 3 is formed on an n-type substrate with an impurity concentration of, for example, (2 to 3)×10 ¹⁵ cm ^-3 , and the N-channel transistor is formed in the first implementation shown in FIG. As in the example, the impurity concentration is
It is formed in the P well 42 of about 10 ¹⁶ cm ^-3 , but in the P channel, the source, drain 48, 4
Both 9 have the same conductivity type as the substrate, and the impurity concentration is 10 ¹⁶
It is surrounded by n-type regions 43 and 44 which are about cm ^-3 and higher than the substrate. With this structure, the N-channel transistor has the same structure as shown in Figure 2, so the channel length can be shortened to 5 μm or less, but even in the P-channel transistor, both the source and drain have an impurity concentration of about 10 ¹⁶ cm ^-3 . Since it is surrounded by a relatively high region, the decrease in breakdown voltage and threshold voltage due to the electric field from the drain is reduced, and the channel length can be made 5 μm or less.

FIG. 4 shows a third embodiment of the present invention, in which the structures of the N-channel transistor and the P-channel transistor of the embodiment shown in FIG. 3 are interchanged.
That is, a P-type substrate 8 with an impurity concentration of, for example, 10 ¹⁵ cm ^-3
0, the P-channel transistor is formed in the well 83 with a relatively high impurity concentration of about 10 ¹⁶ cm ^-3 , and the N-channel transistor is formed in the well 83 with its source,
Both drains 84 and 85 have an impurity concentration of 10 ¹⁶ cm ^-3
It is surrounded by relatively high p-type regions 81 and 82. By shielding the electric field from the drain by this p-type region, the channel length of the N-channel can be shortened. In addition, since a lightly doped p-type substrate is used, it is necessary to form highly doped p-type regions 93 and 94, which are channel stoppers for preventing parasitic MOS transistors, only around the N-channel transistor.

What is common to the embodiments of the present invention described above is that in order to shorten the channel length of the N-channel transistor and the P-channel transistor without impairing the characteristics of the transistor, both the source and the drain are connected to the substrate of each transistor. (If the transistor is formed in a well, the well region is considered to be the substrate.) Surround the channel region with a region of the same conductivity type and with a higher impurity concentration than the substrate, and protect the channel region from the electric field from the drain. It is to shield.

Next, the manufacturing method of each embodiment of the present invention will be explained. FIG. 5 is a diagram showing the manufacturing process of the first embodiment shown in FIG. 2. First, the impurity concentration is 10 ¹⁵ cm
An n-type or p-type low concentration substrate 119 of ^-3 or less is selectively oxidized using a silicon nitride film as a mask to form a field oxide film 120 (FIG. 5A). Next, using the oxide film or photoresist film 121 as a mask,
A p-type impurity such as boron is added to the region where an N-channel transistor is to be formed to form a p-well 122.
(Figure 5B). Similarly, an n-type impurity such as phosphorus or arsenic is added to a region where a P-channel transistor is to be formed to form an n-well 124 (FIG. 5C). After that, thin gate oxide films 127 and 128 are formed, and polycrystalline silicon or molybdenum 125, which is a gate electrode, is further formed on the thin gate oxide films 127 and 128.
127 (Fig. 5D). Next, oxide film 1
29,130 as a mask for phosphorus, arsenic, etc.
A high concentration of type impurity is added to form the source and drain 131, 132 of an N-channel transistor (FIG. 5E). Next, using the oxide film 133 as a mask, p-type impurities such as boron are doped at a high concentration, and the sources and drains 135 and 13 of the P-channel transistors are
6 and a high concentration region 134 to the p-well 122 (FIG. 5F). Note that in order to reduce the change in threshold voltage due to the electric field from the drain, N
The depth of the high-concentration impurity regions of the source and drain of channel transistors and P-channel transistors
It is desirable that the thickness be 0.5 μm or less. After that, a surface protective film 137 is applied, holes are made for taking out the electrodes, and finally the electrodes 138, 139, 140, 141
(Fig. 5G). Note that the n-well can also be formed by the following method different from the above method. That is, after forming the p-well 122 by adding boron in the process shown in FIG. 5, the gate oxide film and gate electrode are immediately formed without forming the n-well, and then
Channel transistor source and drain region 1
43 and 144, then cover the N-channel transistor with an oxide film 145, and using the gate electrode 147 of the P-channel transistor as a mask, add n-type impurities sufficiently deep from where the source and drain of the P-channel transistor are to be formed. The impurity is diffused to form an n-well 146 under the gate oxide film so that the impurity distribution between the source and drain becomes substantially flat as shown in FIG. 6A. In FIG. 6, a shows the impurity distribution diffused from the drain end, b shows the impurity distribution from the source end, and c shows the combined impurity distribution of both. (Figure 5H). At this time, when phosphorus is used as the n-type impurity, the diffusion coefficient of phosphorus is sufficiently larger than that of boron, which is the p-type impurity, so the n-well is formed in a short heat treatment time, and the expansion of the p-well due to the heat treatment during this time is Can be made smaller. Next, the sources and drains 150 and 151 of the P channel transistors are formed by diffusing high concentration p-type impurities (fifth
Figure I). The subsequent steps are exactly the same as the above steps. In such an n-well formation method, since the n-well is formed by a self-alignment method that does not require a mask alignment process, it is advantageous in that the mask alignment process is performed one less time than the above process. A method similar to this n-well formation method is known (for example, Japanese Patent Publication No. 48-16033), but the impurity distribution between the source and drain under the gate oxide film in the conventional example is shown in Figure 6A. Unlike the impurity distribution in the present invention, as shown in Figure 6B (the meanings of the symbols in the figure are the same as in Figure 6A), the impurity concentration is lower in the center between the source and drain. As a result, the threshold voltage under the thick field oxide film on the region where the impurity concentration is low becomes small, making it impossible to completely isolate the devices, resulting in significant impairment of device characteristics. When the impurity distribution shown in FIG. 6A is used as in the present invention, the isolation between elements is completely achieved.

FIG. 7 shows a manufacturing method of the second embodiment shown in FIG. Step of forming p-well 155 (seventh
The steps up to Figures A and B) are the same as those shown in Figure 5, but after forming the p-well 155, high-concentration n-type impurities are added to form the source and drain 157, 160 of the n-channel transistor. (Fig. 7C) After that, n-type impurities are added using the gate electrode 162 as a mask and thermally diffused, so that the impurity concentration is 10 ¹⁶ cm ^-3 , which is higher than that of the substrate.
65, 166 (FIG. 7D). Note that the diffusion depth of these n-type regions 165 and 166 needs to be deeper than that of the source and drain formed in a later step. Next, sources and drains 169 and 170 of a P channel transistor are formed by adding p-type impurities at a high concentration (FIG. 7E).
Next, a surface protective film 175 is applied, holes are made for taking out the electrodes, and finally the electrodes 171, 172, 17
3,174 (Fig. 7F).

FIG. 8 shows a part of the manufacturing method of the third embodiment shown in FIG. 4. 3 shown in Figure 4.
In the embodiment shown in FIG. 3, the structures of the N-channel transistor and the P-channel transistor are switched, so the manufacturing method of the third embodiment is the same as that of the second embodiment shown in FIG. The manufacturing method in the example is almost the same except that the n-type impurity and the p-type impurity are replaced. However, in the third embodiment, it is necessary to form a highly doped p-type region as a channel stopper around the N-channel transistor, so as shown in FIG.
9. Using the photoresist film 190 as a mask, p-type impurities are added to form a channel stopper 191 (FIG. 8A), and the subsequent steps are the same as those shown in FIG. 7 as described above. Note that in the third embodiment, the P channel transistor is formed in the n-well, but the method for forming the n-well is as follows.
In addition to the same formation method as the p-well shown in FIG.
As shown in the steps below in Figure B, after forming an N-channel transistor, an n-channel transistor is formed to form an n-well.
Using phosphorus as a type impurity, the phosphorus is diffused sufficiently deeply using the gate electrode 202 as a mask, and as shown in FIG.
As described in step I, an n-well is formed under the gate oxide film so that the impurity distribution between the source and drain becomes substantially flat as shown in FIG. 6A (FIG. 8E). In this case, since phosphorus having a high diffusion rate is used as an impurity, the n-well 205 can be formed in a short heat treatment time without significantly changing the impurity distribution in the p-type regions 193 and 196. After that, p-type impurities are doped at a high concentration, and the source and drain 207 of the p-channel transistor are
208 (FIG. 8F), and a surface protective film 214 is formed.
Finally, the electrodes 210, 211, 212,
213 (FIG. 8G).

A common feature of the manufacturing methods of the various structures described above is that in both well regions where N-channel and P-channel transistors are formed, impurities are doped through the window of the field oxide film after selective growth of the field oxide film. It is formed by doing. FIG. 9A shows a state in which a field oxide film is formed, and FIGS. 9B, C, and D show states in which impurities are added through the window of the field oxide film.
This means that the well is formed in a self-aligned manner without the need for a mask alignment process, and there is no need to take allowances for pattern design for mask alignment, so the area of the CMS transistor can be reduced and the It becomes possible to integrate. Furthermore, since the well is formed after the oxidation step for forming the field oxide film, redistribution of impurities during oxidation is avoided, making it easier to control the impurity concentration within the well. On the other hand, in the conventional well forming method, as shown in the process diagrams of FIGS. 9E, F, and G, after the well 102 is first formed,
Mask alignment is performed so that the silicon nitride film 104, which serves as a mask for selective oxidation, is accurately positioned within the well, and then a thick field oxide film 105 is formed. This well formation method requires a margin for mask alignment (X in Figure 9F) in the pattern design for well formation, and CMS
This increases the area of the transistor, and furthermore, redistribution of impurities within the well occurs during the formation of the field oxide film, impairing the controllability of the impurity concentration, that is, the controllability of the threshold voltage of the transistor.

Short channel length with the structure described above
An example in which a CMS transistor is applied to a peripheral circuit of a dynamic memory will be explained. Figure 10,
Figure 11 is a cross-sectional view showing an example of its application, where the memory cell is a 1MS consisting of a P channel transistor.
It is a transistor type and is made of polycrystalline silicon 268,
Inversion layer capacitance formed directly under 278 and 299 and transfer electrode 2 formed of polycrystalline silicon
69, 279, 300 and p-type diffusion layers 258, 269, 289 which become data lines.
The CMS transistor forming the peripheral circuit has the structure shown in FIG. 3, so that the channel length can be shortened. In this way, the memory cells are 1MS transistor type and the peripheral circuits are CM.
The purpose of using the S transistor is to reduce the power consumption of the memory without reducing the degree of integration.

The characteristics of each structure shown in FIGS. 10 and 11 will be described. In the structures shown in FIGS. 10 and 11, the CMS transistors in the peripheral circuits are the same as those shown above, but the memory cell portion consisting of P channel transistors is
They are formed in n-wells 263 and 283 created in the same manner. The impurity concentration in the n-well is the same as that of the substrate 26.
Since it is higher than 0,280, the transfer electrode 279,3
00 channel length can be shortened. In order to set the threshold voltage under the transfer electrode to about -1V of the enhancement type, the polycrystalline silicon forming the transfer electrodes 279 and 300 is doped with a high concentration of p-type impurity. The difference between FIG. 10 and FIG. 11 is the storage electrode 27.
The polycrystalline silicon forming 8,299 is doped with n-type impurities at a high concentration in FIG.
In FIG. 11, p-type impurities are added at a high concentration.

The above memory structure can be manufactured by the manufacturing process shown in FIG. 12 according to the well formation method described above.
FIG. 12 is a manufacturing process diagram for making the memory structure shown in FIGS. 10 and 11. A p-well 325 and an n-well 328 are formed in the substrate 323 (FIGS. 12A, B, and C). Next, a gate oxide film 324 is formed, and then a first layer of polycrystalline silicon is deposited. Here, when forming the memory structure shown in FIG. 10, n-type impurities are doped at a high concentration only in the polycrystalline silicon 331 and 333 on the N-channel transistor and the memory cell, as shown in FIG. 12D. . On the other hand, when forming the memory structure shown in FIG. 11, the P
A high concentration of p-type impurities is added to the polycrystalline silicon 346 on the channel transistor and memory cell. Thereafter, an oxide film 335 is formed only in the memory cell portion, and a pattern is formed on the polycrystalline silicon by photoetching, and gate electrodes 336, 337,
A storage electrode 351 is formed (FIG. 12E). Next, after forming a thin oxide film 349, a second layer of polycrystalline silicon is deposited to form a transfer electrode 350 (FIG. 12F). Next, the P-channel transistor and the memory cell portion are covered with an oxide film 338, and n-type impurities are added at a high concentration to form the source and drain 339 of the N-channel transistor (FIG. 12G).
Next, the N-channel transistor is covered with an oxide film 340, and p-type impurities are added at a high concentration to form the p-well 32.
5, the p-type high concentration layer 341, the source and drain 342 of the P channel transistor, and the data line 3
43 (FIG. 12H). Next, a surface protective film 344 is deposited, and finally an electrode 345 is formed (FIG. 12I). Note that even if the gate electrodes 336 and 337 of the N-channel and P-channel transistors are formed using the second layer of polycrystalline silicon in FIG. 12, the memory structure can be realized in almost the same process as shown in FIG. .

Above, the structure and manufacturing method of a new CMS transistor that can reduce the channel length of the CMS transistor to 5 μm or less as the content of the present invention has been explained. The performance and operating speed will be significantly improved.

Furthermore, when a semiconductor memory integrated circuit having a CMOS transistor is configured according to the present invention,
The degree of integration, operating speed, power consumption and stability of memory operation will be improved.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a conventional CMS transistor, and FIGS. 2, 3, and 4 are cross-sectional views of a new CMS transistor according to the present invention.
5, 6, 7, 8, and 9 are diagrams showing the manufacturing method and contents of the CMS transistor according to the present invention, and FIGS. 10 and 11 are diagrams showing the CMS transistor according to the present invention. 12 is a diagram showing an example in which the method is applied to a dynamic memory, and FIG. 12 is a diagram showing a manufacturing process of the memory structure shown in FIGS. 10 and 11. Each symbol indicates the following. 1, 22, 41, 80, 119, 182, 18
8,101,260,280,301,323:
Semiconductor substrate, 2, 24, 42, 81, 82, 10
2,108,401,402,403,122,
142, 155, 193, 196, 261, 28
1,304,325: p-type impurity region, 23,4
3, 44, 83, 124, 146, 165, 16
6,205,252,262,263,283,
282, 306, 328, 329: n-type impurity region, 3, 4, 9, 10, 25, 28, 29, 4
5, 48, 49, 93, 94, 86, 88, 13
4,135,136,148,150,151,
167, 169, 170, 191, 207, 20
8,256,267,268,284,287,
288, 289, 318, 319, 342, 34
3: p-type high concentration impurity region, 7, 8, 5, 6, 2
6, 27, 46, 47, 84, 85, 88, 13
1,132,143,144,157,160,
200, 201, 203, 285, 286, 32
2,339: n-type high concentration impurity region, 20,2
1, 31, 33, 51, 53, 89, 92, 10
3,126,128,158,161,194,
198, 273, 276, 293, 297, 31
0,314,334,349: Thin oxide film, 1
1, 12, 30, 32, 50, 52, 90, 9
1,125,127,159,162,195,
197, 261, 265, 268, 269, 27
2,275,278,279,292,296,
299, 300, 307, 308, 312, 31
3,352,315,360,331,332,
333, 336, 337, 346, 347, 35
0,351,404,405: polycrystalline silicon,
14, 13, 15, 34, 35, 36, 54, 5
5, 56, 95, 105, 107, 120, 15
3,192,270,290,302,324:
Thick oxide film, 104,189: silicon nitride film,
100, 123, 130, 133, 145, 14
9,154,163,164,168,190,
199, 202, 204, 206, 209, 30
3,305,309,326,327,330,
338, 340, 348: Mask insulator when adding impurities, 311, 316, 335: Oxide film, 13
7,175,214,320,344: Surface protective film, 16,17,18,19,37,38,3
9, 40, 57, 58, 59, 60, 96, 9
7,98,99,138,139,140,14
1,171,172,173,174,210,
211, 212, 213, 271, 274, 27
7,291,294,295,298,321,
345: Electrode.

Claims (1)

[Claims] 1. An N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor, wherein at least the source and drain regions of one of the two insulated gate field effect transistors are located on the opposite side of the semiconductor substrate. a complementary insulator formed in a region having a conductivity type, and at least the other source and drain regions have the same conductivity type as the semiconductor substrate and are formed in a region having a higher impurity concentration than the substrate; A semiconductor integrated circuit having a complementary insulated gate field effect transistor, characterized in that a gate field effect transistor is used in a peripheral circuit, and a semiconductor element constituting a memory cell is formed in a region having a higher impurity concentration than the substrate. circuit. 2. A region having a higher impurity concentration than the substrate on which the semiconductor element constituting the memory cell is provided is
2. A semiconductor integrated circuit having a complementary insulated gate field effect transistor according to claim 1, wherein said complementary insulated gate field effect transistor is separated from a region in which said complementary insulated gate field effect transistor is provided.