JPH01164062A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To sharply improve an integration density and an operation speed of a large-scale integrated CMOS transistor by a method wherein a plane position between a first region whose conductivity type is opposite to that of a semiconductor substrate and a second region whose impurity concentration is higher than that of the substrate is prescribed by an identical photomask. CONSTITUTION:An n-type or a p-type low-concentration substrate 119 whose impurity concentration is 10<15>cm<-3> or below is oxidized selectively by making use of a silicon nitride film as a mask; a field oxide film 120 is formed; then, a region where an N-channel transistor is to be formed is doped with a p-type impurity such as boron or the like by making use of the oxide film or a photoresist film 121 as a mask; a p-well 122 is formed. In the same manner, an n-type impurity is doped; an n-well 124 is formed. The p-type impurity such as boron or the like is doped at high concentration by making use of an oxide film 133 as a mask; a source and a drain 135, 136 of a P-channel transistor and a high-concentration region 134 for the p-well 122 are formed. The well regions 122, 134 where the N-channel transistor and the P-channel transistor are formed after a selective growth operation of a field oxide film 120 in such a way that they are doped with the impurity from a window of the field oxide film.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a complementary insulated gate field effect transistor that can be manufactured at high speed and with high integration.

[Conventional technology]

A complementary insulated gate field effect transistor (hereinafter abbreviated as CMOS transistor), which is a combination of N-channel and P-channel insulated gate field effect transistors, is
Widely used in low power integrated circuits, linear circuits, etc.

Conventionally, this device had the structure shown in FIG. That is, a P channel transistor is formed on an n type substrate 1, the N channel transistor is formed in a p shadow region 2 formed in the substrate 1, and a guard band (high concentration p Shadow regions 3 and 4 and high-density n shadow regions 5° and 6) are formed. Furthermore, the channel length of each of the N-channel and P-channel transistors is relatively long, approximately 5 μm or more.

[Problem to be solved by the invention]

Therefore, when an integrated circuit is constructed using the CMOS transistor having the conventional structure described above, the degree of integration is low, and furthermore, it is difficult to increase the speed. It is already known that in order to remove the guard band, a method of locally forming a thick oxide film using a silicon nitride film (hereinafter abbreviated as selective oxidation method) is used to improve the degree of integration ( For example, "Electronic Materials," May 1974, P12-P15), it is necessary to shorten the channel length of MOS transistors in order to achieve higher integration and higher speed. In the CMOS transistor of the conventional structure shown in FIG. 2, when the channel length is shortened to, for example, 5 μm or less, the P-channel transistor is formed on the n-type substrate 1 with a low impurity concentration of about 10"cm-3. As a result, the electric field from the drain affects the channel region under the gate oxide film 21, resulting in a decrease in breakdown voltage due to the punch-through phenomenon and a decrease in threshold voltage Vth due to the electric field from the drain, resulting in poor operation as a transistor. will be significantly damaged.

The object of the present invention is to improve the drawbacks of the above-mentioned prior art.

An object of the present invention is to provide a method for manufacturing short channel CMOS transistors that can be manufactured at high speed and with high integration.

[Means to solve the problem]

In order to achieve this object, in the present invention, the periphery and bottom surface of both the source and drain of the N-channel and P-channel transistors constituting the CMOS transistor are of a conductivity type opposite to that of the source and drain, and are higher than the substrate. It is surrounded by a region having an impurity concentration, and is further characterized in that the region having a high impurity concentration is formed by adding impurities through a window of the field oxide film after growing a thick field oxide film.

[Effect]

After forming a thick oxide film, a well is formed through the window of this oxide film, so impurity distribution in the well due to oxidation is avoided, and the impurity concentration can be easily controlled. Furthermore, since the process of mask alignment for well formation is not necessary, the required area is reduced.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to Examples.

In addition, in the following, CMOS using silicon as a semiconductor will be explained.
This will be explained using a transistor as an example.

FIG. 1 shows a first embodiment of the present invention, in which both the N-channel and P-channel MOS transistors have an impurity concentration higher than that of the substrate 22 (for example, 1015 cm-3 or less) (for example, 1016cI11-3: In practical terms, the impurity concentration of the well is approximately 5×10” to 5×10
The well 23 has a well 23 having a device characteristic (for example, a threshold voltage, etc.) that may be designed within a range of about 100 cm.
, 24. Therefore, in each transistor, the influence of the electric field from the drain on the channel region becomes small, and the channel length of each transistor is reduced to 5 μm.
Even if it is set below, a decrease in breakdown voltage and a decrease in threshold voltage Vih due to the punch-through phenomenon are less likely to occur. Furthermore, since each transistor is in a well with a relatively high impurity concentration, thick field oxide films 34, 35 in the well
．． The threshold voltage of 36 is also about 20 V or higher, and even without forming a guard band as in the conventional structure shown in FIG.
Generation of parasitic MOS transistors can be prevented. In the case of the structure shown in FIG. 2, the conductivity type of the substrate 22 may be n-type or p-type as long as its impurity concentration is lower than that of the wells 23 and 24. The threshold voltages of the N-channel and P-channel MOS transistors are Even if the oxide film becomes thinner than 1000 Å, its absolute value can be easily reduced to about 1 V in an enhancement type by increasing the impurity concentration in the well.

FIG. 3 shows a second embodiment of the invention. C shown in Figure 3
A MOS transistor has an impurity concentration of, for example, (2 to 3
) x 10"am-", and the N-channel transistor is formed in a P-well 42 with an impurity concentration of about 101 m cm-3, as in the first embodiment shown in FIG. However, in the P channel, the source and drain 48° 49 are both of the same conductivity type as the substrate, and are surrounded by an n shadow region 43° 44 where the impurity concentration is about 10 am-' and higher than the substrate. In this structure,
Since the N-channel transistor has the same structure as shown in Figure 1, the channel length can be shortened to 5 μm or less, but even in the P-channel transistor, both the source and drain have relatively high impurity concentrations of about 10 am'3. Because the channel is surrounded by a region, the decrease in breakdown voltage and threshold voltage due to the electric field from the drain is reduced, and the channel length can be reduced to 50%.
Can be made smaller than μm.

FIG. 4 shows a third embodiment of the present invention, in which the structures of the N-channel transistor and P-channel transistor of the embodiment shown in FIG. 3 are interchanged.

That is, using a p-type part plate 80 with an impurity concentration of, for example, 10 cm -3 , a P-channel transistor is formed in a well 83 with a relatively high impurity concentration of about 10 cm -3 , and an N-channel transistor is formed in its source, drain 8
4.85 are both surrounded by a relatively high p shadow region 81.82 with an impurity concentration of about 1016 cm+-3. This p
The channel length of the N-channel can be shortened by shielding the electric field from the drain by the shadow region. In addition, low concentration p
Since a shaped substrate is used, it is necessary to form high-concentration p shadow regions 93 and 94, which are channel stoppers for preventing parasitic MOS transistors, only around the N-channel transistor.

What is common to the embodiments of the present invention described above is that N
In order to shorten the channel length of channel transistors and P-channel transistors without impairing the characteristics of the transistors, both the source and drain are connected to the substrate of each transistor (or the well region if the transistor is formed in a well). The channel region is surrounded by a region of the same conductivity type as the substrate (considered as the substrate) and has a higher impurity concentration than the substrate, and the channel region is shielded from the electric field from the drain.

Next, the manufacturing method of each embodiment of the present invention will be explained.

FIG. 5 is a diagram showing the manufacturing process of the first embodiment shown in FIG. 2. First, to form an n layer with an impurity concentration of 10"c+n-"3 or less, the p-type image concentration group Fi 119 is selectively oxidized using the silicon nitride film as a mask to form a field oxide film 120 (FIG. 5A). Next, using the oxide film or photoresist film 121 as a mask, a p-type impurity such as boron is added to a region where an N-channel transistor is to be formed to form a p-well 122 (FIG. 5B). Similarly, an n-type impurity such as phosphorus or arsenic is added to a region where a P-channel transistor is to be formed to form an n-well 124 (
Figure 5C). After that, a thin gate oxide film 127.128
is formed, and polycrystalline silicon or molybdenum 125°127, which is the gate electrode, is further deposited thereon (see Fig. 5D).
). Next, using the oxide films 129 and 130 as a mask, n-type impurities such as phosphorus and arsenic are added at a high concentration to form the source and drain 131 and 132 of the N-channel transistor (FIG. 5E).6 Next, the oxide film 133 Using this as a mask, p-type impurities such as boron are doped at a high concentration, and the source and drain of the P-channel transistor 135°136 and the p-well 1 are
22 (FIG. 5F). Note that in order to reduce changes in the threshold voltage due to the electric field at the drain, it is desirable that the depth of the high concentration impurity regions of the sources and drains of the N-channel transistor and the P-channel transistor be 0.5 μm or less. Thereafter, a medical surface protective film 137 is applied, holes are made for taking out the electrodes, and finally electrodes 138, 139, 140, and 141 are formed (FIG. 5G). Note that the n-well can also be formed by the following method different from the above method. That is, the fifth
By adding boron in the process shown in the figure, the n-well 122
After forming the N-channel transistor, a gate oxide film and a gate electrode are immediately formed without forming an N-well, and then the source and drain regions of the N-channel transistor 143°1
44 is formed, and then an oxide film 145 is formed to cover the tilted N-channel transistor, and the gate electrode 1 of the P-channel transistor is formed.
47 as a mask, n-type impurities are diffused sufficiently deep from where the source and drain of the P-channel transistor are to be formed, until the impurity distribution between the source and drain under the gate oxide film is approximately as shown in Figure 6A. An n-well 146 is formed so as to be flat. In addition, the 6th
In the figure, a shows the impurity distribution diffused from the drain end, b shows the impurity distribution from the source end, and C shows the combined impurity distribution of both. (Figure 5H). At this time, when phosphorus is used as the n-type impurity, the diffusion coefficient of phosphorus is sufficiently larger than that of boron, which is the p-type impurity, so the n-well is formed in a short heat treatment time, and the expansion of the n-well due to the heat treatment during this time is Can be made smaller. Next, sources and drains 150 and 151 of P-channel transistors are formed by diffusing p-type impurities at a high concentration (FIG. 5, 1).

The subsequent steps are exactly the same as the above steps. In this n-well formation method, since the n-well is formed by a self-alignment method that does not require a mask alignment process, it is advantageous in that there is one less mask alignment process compared to the above process. A method similar to this n-well formation method is known (for example, Japanese Patent Publication No. 48-16033), but the impurity distribution between the source and drain under the gate oxide film in the conventional example is shown in Figure 6A. Unlike the impurity distribution in the present invention shown in FIG.
is the same as ), source.

Since the impurity concentration is low in the center between the drains,
Since the threshold voltage under the thick field oxide film on the region where the impurity concentration is low becomes small, the isolation between devices cannot be completed, and device characteristics are significantly impaired. When the impurity distribution shown in FIG. 6A is used as in the present invention, the isolation between elements is completely achieved.

FIG. 7 shows a manufacturing method of the second embodiment shown in FIG. The steps up to the step of forming the n-well 155 (FIGS. 7A and B) are the same as the steps shown in FIG.
After forming, n-type high-concentration impurities are added to form the source and drain 157, 160 of the N-channel transistor (FIG. 7C).

After that, an n-type impurity is added using the gate electrode 162 as a mask, and the impurity concentration is increased to 1016 by thermal diffusion.
An n shadow region 165° 166 cm+3 higher than the substrate is formed (FIG. 7D). Note that this n shadow area 165, 16
The diffusion depth in step 6 needs to be deeper than that of the source and drain, which will be created in a later process. Next, the source and drain 169 and drain 169 and 170 of the P channel transistor are formed by adding p type impurities at a high concentration (FIG. 7E). Next, a surface protective film 175 is applied, holes are made for taking out the electrodes, and finally electrodes 171, 172, 173° 174 are formed (FIG. 7F).

FIG. 8 shows a part of the manufacturing method of the third embodiment shown in FIG. 4. The third embodiment shown in FIG.
Since the structures of the N-channel transistor and the P-channel transistor in the embodiment shown in the figure are interchanged, the manufacturing method of the third embodiment is the same as the manufacturing method of the second embodiment shown in FIG. , are almost the same except that the n-type impurity and the p-type impurity are replaced. However, in the third embodiment, it is necessary to form a high-concentration p-shade region, which is a channel stopper, around the N-channel transistor.
As shown in the figure, a p-type impurity is added using a silicon nitride film 189 and a photoresist film 190 as masks to form a channel stopper 191 (FIG. 8A), and the subsequent steps are shown in FIG. 7 as described above. The process is the same as shown. Note that in the third embodiment, the P channel transistor is n
Although it is formed in a well, as a method for forming an n-well,
In addition to the same formation method as the n-well shown in FIG. 7 above, as shown in the steps shown in FIG. Using 202 as a mask, phosphorus is diffused sufficiently deeply so that the impurity distribution between the source and drain under the gate oxide film is 6th, as described in the steps H and I in Figure 5.
An n-well is formed so as to be substantially flat as shown in Figure A (Figure 8E). In this case, since phosphorus with a high diffusion rate is used as an impurity, the p shadow region 193,
The n-well 205 can be formed in a short heat treatment time without significantly changing the impurity distribution of the n-well 205. After that, a high concentration of p-type impurity is added to the source of the p-channel transistor.
Drains 207 and 208 are formed (FIG. 8F), a surface protective film 214 is applied, and finally electrodes 210 and 211 are formed.
2.213 is formed (Fig. 8G).

A common feature of the manufacturing methods of the various structures described above is that the well regions where N-channel and P-channel transistors are formed are doped with impurities through the window of the field oxide film after selective growth of the field oxide film. It is formed by doing. FIG. 9A shows a state in which a field oxide film is formed, and FIGS. 9B, C, and D show states in which impurities are added through a window in the field oxide film.

This means that the well is formed in a self-aligned manner without the need for a mask alignment process, and there is no need to take allowances for pattern design for mask alignment, so the area of the CMOS transistor can be reduced and the It becomes possible to integrate. Furthermore, the fact that the well is formed after the oxidation process for forming the field oxide film prevents impurity redistribution during oxidation, making it easier to control the impurity concentration within the well. On the other hand, in the conventional well forming method, as shown in the process diagrams of FIGS. 9E, F, and G, after the well 102 is first formed.

Mask alignment is performed so that the silicon nitride film 104, which serves as a mask for selective oxidation, is accurately positioned within the well, and then a thick field oxide film 105 is formed. Such a well formation method requires a margin for mask alignment in the pattern design for well formation (x in FIG. 9F), which increases the area of the CMOS transistor, and furthermore,
Redistribution of impurities within the well occurs during the formation of the field oxide film, which impairs the controllability of the impurity concentration, that is, the controllability of the threshold voltage of the transistor.

CMOS with short channel length having the structure described above
An example in which a transistor is applied to a peripheral circuit of a dynamic memory will be explained. Figure 10.

Figure 11 is a cross-sectional view showing an example of its application. The memory cell is an IMOS transistor type consisting of a P-channel transistor, and the inversion layer capacitance formed directly under the polycrystalline silicon 268°278.299 and the polycrystalline silicon It consists of transfer electrodes 269, 279, 300 to be formed and p-type wave dispersion layers 258, 269, 289 which will become data lines. The CMOS transistor forming the peripheral circuit has the structure shown in FIG. 3, so that the channel length can be shortened. As described above, the purpose of using IMOS transistor type memory cells and CMOS transistor type peripheral circuits is to reduce the power consumption of the memory without reducing the degree of integration.

The characteristics of each structure shown in FIGS. 10 and 11 will be described. 1st
In the structures shown in Figures 0 and 11, the CMOS transistors in the peripheral circuits are the same as those shown above, but the P
A memory cell portion consisting of a channel transistor is formed in n-wells 263 and 28 formed in low concentration substrates 260 and 280.
It is formed within 9. Since the impurity concentration in the n-well is higher than that in the substrate 260°280, the transfer electrodes 279, 30
0 channel length can be shortened. In order to set the threshold voltage under the transfer electrode to about -1■ of the enhancement type, the polycrystalline silicon forming the transfer electrodes 279 and 300 is doped with a high concentration of p-type impurity.

The difference between Figures 10 and 11 is that the polycrystalline silicon forming the storage electrodes 278° 299 is doped with n-type impurities at a high concentration in Figure 10, and p-type impurities at a high concentration in Figure 11. It is added.

The above memory structure can be manufactured by the manufacturing process shown in FIG. 12 according to the well formation method described above.

FIG. 12 is a manufacturing process diagram for making the memory structure shown in FIGS. 10 and 11. P-well 32 in substrate 323
5. Form an n-well 328 (FIG. 12A, B, C)
Next, a gate oxide film 324 is formed, and then a first layer of polycrystalline silicon is deposited. When forming the memory structure shown in FIG. 10, only the polycrystalline silicon 331 and 333 on the N-channel transistor and memory cell are doped with n-type impurities at a high concentration, as shown in FIG. 12. On the other hand, when forming the memory structure shown in FIG. 11, p-type impurities are doped at a high concentration into the polycrystalline silicon 346 on the P-channel transistor and the memory cell, as shown in FIG. 12J. Thereafter, an oxide film 335 is formed only in the memory cell portion, and a pattern is formed on the polycrystalline silicon by photoetching, and gate electrodes 336, 337 .
A storage electrode 351 is formed (FIG. 12E). Next, after forming a thin oxide film 349, a second layer of polycrystalline silicon is deposited to form a transfer electrode 350 (FIG. 12F). Next, the P-channel transistor and memory cell portion are covered with an oxide film 338, and n-type impurities are added at a high concentration to form the source of the N-channel transistor.

A drain 339 is formed (FIG. 12G). Next, the N-channel transistor is covered with an oxide film 340, and p-type impurities are added at a high concentration to form the p-highest concentration layer 34 in the p-well 325.
1. P-channel transistor source, drain 342
Then, a data line 343 is formed (FIG. 12H). Next, a surface protective film 344 is deposited, and finally an electrode 345 is formed (FIG. 12). Note that even if the gate electrodes 336 and 337 of the N-channel and P-channel transistors are formed using the second layer of polycrystalline silicon in FIG. 12, the memory structure can be realized in almost the same steps as shown in FIG. .

〔Effect of the invention〕

As described above, the content of the present invention is a new CMOS that can reduce the channel length of a CMOS transistor to 5 μm or less.
Although the structure of the transistor and its manufacturing method have been explained, when CMOS transistors are integrated on a large scale according to the present invention, the degree of integration and operating speed will be greatly improved.

[Brief explanation of the drawing]

Figure 2 is a cross-sectional view of a conventional CMOS transistor.
Figures 1, 3, and 4 show the new CMO according to the present invention.
FIG. 5, FIG. 6, and FIG. 7 are cross-sectional views of the S transistor.
8 and 9 are diagrams showing a method for manufacturing a CMOS transistor according to the present invention and its contents, and FIGS. 10 and 11 are diagrams showing an example in which a CMo5 transistor according to the present invention is applied to a dynamic memory. FIG. 12 is a diagram showing the manufacturing process of the memory structure shown in FIGS. 10 and 11. Each symbol indicates the following. 1.22,41,80,119,182゜188.10
1,260,280,301°323 Two semiconductor substrates 2.24,42,81,82,102,108°401
．． 402, 403, 122, 142° 155.193° 196, 251, 281° 304.325: p-type impurity region 23.43, 44, 83, 124, 146° 165.1
66.205,252,262゜263.283,28
2,306,328°329: n-type impurity region 3.4,9,10,25,28,29,45°48.4
9,93,94,86,88,134°135.136
,148,150,151゜167.169,170,
191,207゜208.256,257,258,2
84°287.288,289,318,319°34
2.343: p-type high concentration impurity region 7.8, 5, 6, 2
6,27,46,47°84.85,88,131,1
32,143°144.157,180,200,20
1゜203.285, 286, 322, 339: n-type high concentration impurity region 20.21, 31, 33, 51, 53, 89゜92.1
03,126,128,158,161゜194.19
8,273,276.293°297.310,314
, 334, 349: Thin oxide film 11.12, 30, 32, 50, 52, 90°91.1
25,127,159,162,195°197.26
1,265,268,269°272.275,278
,279,292゜296.299,300,307,
308°312.313,352,315,360°3
31.332, 333, 336, 337°346.34
7,350,351,404°4o5: Polycrystalline silicon 14.13,15,34,35,36,54°55.5
6,95,105,107,120°153.192,
270, 290, 302° 324: Thick oxide film 104.189: Silicon nitride film 100.123, 130, 133, 145° 149.1
54,163,164,168゜190.199,20
2,204,206°209.303,305,309
, 326° 327.330, 338, 340.348:
Mask insulator 311, 316, 335 when adding impurities: Oxide film 137, 175, 214, 320, 344: Surface protective film 16, 17, 18, 19, 37, 38, 39° 40.5
7,58,59,60,96,97゜98.99,13
8,139,140,141゜171.172,173
,174,210゜211.212,213,271,
274°277.291,294,295,298°3
21.345: Electrode Y/'s ¥2 eyes 10 7/
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eJ et al. IAJ-5 No. 1, 2, Fig. 2 Circumference and circuit y circuit σβ-→-memory → - So 2 reeds ÷ 1 rungis 7

Claims (1)

[Claims] 1. An N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor are provided, and at least the source and drain regions of one of the N-channel and P-channel insulated gate field effect transistors are made of a semiconductor. A second region is formed in a first region having a conductivity type opposite to that of the semiconductor substrate, and at least the other source and drain region has the same conductivity type as the semiconductor substrate and has a higher impurity concentration than the substrate. In the method for manufacturing a complementary insulated gate field effect transistor formed in a region, the planar positions of the first region and the second region are as follows:
A method for manufacturing a semiconductor device, characterized in that the manufacturing method is defined by the same photomask. 2. A method for manufacturing a semiconductor device according to claim 1, wherein the same photomask is a first photomask in the method for manufacturing a semiconductor device. 3. An N-channel insulated gate field effect transistor and a P-channel insulated gate field effect transistor are provided, and at least the source and drain regions of one of the N-channel and P-channel insulated gate field effect transistors have a conductivity opposite to that of the semiconductor substrate. at least the other source and drain regions are formed in a second region that has the same conductivity type as the semiconductor substrate and has a higher impurity concentration than the substrate. A method of manufacturing a complementary insulated gate field effect transistor, wherein the first region and the second region are provided in a self-aligned manner.