JPH0786388A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To lessen a space between a well region and a diffusion without producing a leakage current by a method wherein a P-type guard ring region higher in impurity concentration than a Si substrate is formed under a field oxide film between an N-type well region and a high concentration second conductivity type (N<+>) diffusion layer through an ion implantation method without enhancing a first conductivity type (P-type) Si substrate and a second conductivity type (N-type) well in concentration. CONSTITUTION:An n well region 4 is provided under a field oxide film 6 formed on a P-type Si substrate 1, and a channel stopper layer 5 is formed under the field oxide film 6 adjacent to an N well region 4. An N<+> diffusion layer 8 is provided under a gate oxide film 7 linked to the field oxide film 6 adjacent to the channel stopper layer 5, and a P-type guard ring layer 13 higher in impurity concentration than the P-type Si substrate 1 is formed spreading over the channel stopper layer 5 and the N well region 4 from a part under the N<+> diffusion layer 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, in particular, an N-well CM for a device with a large capacity ROM or a high voltage device.
The present invention relates to a structure of an OS and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, there were the following. FIG. 2 is a cross-sectional view of a manufacturing process of such a conventional semiconductor device. First, FIG.
As shown in (a), a P-type Si substrate as the first conductivity type [impurity concentration (hereinafter simply referred to as concentration) 10 ¹⁴ to 10 ¹⁵
cm ⁻³ ] 1, a SiO ₂ film 2 is formed on the entire surface by thermal oxidation, and a photolithography process is performed to pattern the SiO ₂ film 2 in the N-type well region of the second conductivity type to be removed by etching. Inject 3.

Then, as shown in FIG.
While thermally oxidizing at a high temperature of 0 to 1200 ° C, phosphorus ions 3
Is thermally diffused to form the N well region 4, and the SiO ₂ film 2
Are removed by etching. Here, the diffusion depth is 3 ~
The concentration is about 5 μm, and the concentration is set to a value higher by about one digit than the P-type substrate concentration (about 3 × 10 ¹⁶ cm ⁻³ ).

Next, as shown in FIG. 2C, a normal L
Element isolation is performed by forming a channel stopper layer 5 and a field oxide film 6 by the OCOS method. Here, the concentration of the channel stopper layer 5 is about 10 ¹⁷ cm ⁻³ ,
The thickness of the field oxide film 6 is 4000 to 6000Å.
Further, the gate oxide film 7 is formed on the entire surface. Then, FIG.
As shown in (d), by ion implantation and heat treatment, N ⁺
The diffusion layer 8 (about 10 ²⁰ to 10 ²¹ cm ⁻³ ) and the P ⁺ diffusion layer (concentration about 10 ²⁰ to 10 ²¹ cm ⁻³ ) 9 were formed.

[0005]

However, in the conventional method of manufacturing a semiconductor device described above, a large-capacity ROM is used.
In order to increase the concentration of the Si substrate of the first conductivity type or the well concentration of the second conductivity type, such as a device having a built-in device or a high breakdown voltage device, a well region of the second conductivity type and a diffusion of the high concentration second conductivity type are formed. There is a problem that the pattern becomes large because the layer interval cannot be narrowed.

In order to eliminate the above-mentioned problem that the interval between the well region of the second conductivity type and the diffusion layer of the high-concentration second conductivity type cannot be narrowed, that is, the pattern cannot be made small, the first aspect of the present invention is provided. Without increasing the conductivity type Si substrate concentration or the second conductivity type well concentration, the first conductivity type is formed by ion implantation directly below the field oxide film between the second conductivity type well region and the high concentration second conductivity type diffusion layer. By forming the guard ring region for increasing the type concentration, the well region of the second conductivity type and the high concentration second type are formed without leak current flowing.
An object of the present invention is to provide a semiconductor device capable of reducing the distance between conductive type diffusion layers and a method for manufacturing the same.

[0007]

In order to achieve the above object, the present invention provides: (1) In a semiconductor device, it is formed immediately below a field oxide film formed on a first conductivity type (P type) Si substrate. A second conductivity type (N-type) well region, a channel stopper layer immediately below the field oxide film and adjacent to the well region, and a gate oxide film connected to the field oxide film. A high concentration second conductivity type (N ⁺ ) diffusion layer adjacent to the stopper layer and a concentration higher than the concentration of the first conductivity type (P type) Si substrate extending from below the diffusion layer to the channel stopper layer and the well region are set. The first conductivity type (P type) guard ring layer is provided.

(2) In a method of manufacturing a semiconductor device, a well region of a second conductivity type (N type) is formed immediately below a field oxide film formed on a Si substrate of a first conductivity type (P type), A channel stopper layer is formed immediately below the field oxide film and adjacent to the well region, and is formed immediately below a gate oxide film connected to the field oxide film and adjacent to the channel stopper layer. ⁺ ) Diffusion layer is formed, and a first conductivity type (P-type) guard ring layer is formed by ion implantation to reinforce the impurity concentration of the field oxide film lower channel stopper layer from the lower portion of the diffusion layer. Is.

[0009]

According to the present invention, for example, by ion implantation of boron between the N well region formed immediately below the field oxide film and the N ⁺ diffusion layer adjacent to the channel stopper layer, P
A P-type guard ring layer having a concentration higher than that of the type Si substrate is formed.

Therefore, the distance between the N well region and the N ⁺ diffusion layer can be reduced without causing a leak current, and the degree of integration of the device can be improved accordingly.

[0011]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a sectional view of a main part manufacturing process of a semiconductor device showing an embodiment of the present invention. First, the conventional manufacturing method described above is performed up to the step of FIG. 2D, and thereafter, as shown in FIG. 1A, the resist 10 is patterned to form the guard ring region 12, that is, the N well region 4. And the channel stopper region of the N ⁺ diffusion layer 8 is opened.

The guard ring region 12 is shown in FIG.
SiO when forming the N well region shown in (a)₂Membrane 2
From the edge of the ching edge or the N well region
From the field of 2.0 μm from the field oxide edge
N of 1.0 μm or more⁺It is a region up to the diffusion layer 8. Next
Then, boron ions 11 are implanted into the guard ring region 12.
It The ion implantation conditions at this time are as follows:
Penetrating acceleration energy (field oxide film thickness 400
In case of 0Å, 140 KeV or more is required. At this time, R
_p= 4179Å). Channel stopper for dose
Concentration of layer 5, ie about 10¹⁷cm ^-3More than twice
10¹⁷cm^-3The above concentration is directly under the field oxide film.
X less than 0.4 μm_jIs required.

Then, as shown in FIG. 1B, a P-type card ring layer 13 is formed as a concentration reinforcement of the lower portion of the N ⁺ diffusion layer 8 and the channel stopper layer 5. FIG. 3 shows the N well region of the threshold (V _th ) of the field transistor and N
FIG. 6 is a diagram showing a space dependency with a ⁺ diffusion layer. Here, the vertical axis represents the threshold voltage V _th (V), the horizontal axis represents the distance between the N well region and the N ⁺ diffusion layer, and the lateral diffusion of the N well region is 3 μm.
2 and the edge portion of the N well region 4 is shown in FIG.
The etching edge portion of the SiO ₂ film 2 shown in (a) and the edge portion of the N ⁺ diffusion layer 8 are the field-etched portions shown in FIG. 2 (a). Line A shows the case of the present invention, and line B shows the case of the prior art.

As is apparent from FIG. 3, in the conventional case,
When the distance between the N well region and the N ⁺ diffusion layer becomes 5.5 μm or less, the threshold value (V _th ) drops sharply. That is, a leak current occurs (becomes a low impedance state and a latch-up phenomenon occurs). On the other hand, in the case of the present invention,
A constant threshold value (V _th ) can be maintained up to 2.5 μm.

In other words, according to the present invention, when the lateral diffusion of the N well region 4 is 3 μm, the gap between the N well region and the N ⁺ diffusion layer is about 3 μm in the case of the present invention as compared with the conventional case. It turns out that can be narrowed. That is, the P-type region between the N well region and the N ⁺ diffusion layer can be narrowed. Moreover, the current gain of the field transistor (current amplification factor) is a h _FE = 1 / _{[(ρ E · W B / ρ} B · L E) + (W B 2/2 × L B 2) ].

Where ρ _E is the emitter resistivity, ρ _B is the base resistivity, W _B is the base width, L _E is the emitter diffusion length,
L _B is the base diffusion length. FIG. 4 is a diagram showing a calculation example of the current gain (current amplification factor) h _FE of the field transistor. Here, the vertical axis represents the current gain (h _FE ) and the horizontal axis represents the pace width (P-type region corresponding to the distance between the N well region and the N ⁺ diffusion layer) W _B (μm), and ◯ is the P-type. The region concentration is 6 × 10 ¹⁷ cm ⁻³ , and the black circle indicates the concentration is 1 × 10 ¹⁷ cm ⁻³ .

As is apparent from FIG. 4, when the current gain h _FE is 16, the base width W _B is about 11 μm for ◯ and about 16 μm for ●. That is, the higher the concentration, the base width W
_B (P-type region between N well region and N ⁺ diffusion layer) can be narrowed. Therefore, according to the present invention, the distance between the N well region and the N ⁺ diffusion layer can be made narrower than in the conventional case.

In the above embodiment, the Si substrate was P type, the well region was N type, the diffusion layer was N ⁺ diffusion layer, and the guard ring layer was P type. N
Alternatively, the well region may be P type, the diffusion layer may be P ⁺ diffusion layer, and the guard ring layer may be N type. Further, the present invention is not limited to the above-described embodiments, and various modifications can be made based on the spirit of the present invention, and they are not excluded from the scope of the present invention.

[0019]

As described above in detail, according to the present invention, the second conductivity type (P-type) Si substrate concentration and the second conductivity type (N-type) well concentration can be increased without increasing the second conductivity type (P-type) Si substrate concentration. Immediately below the field oxide film between the conductivity type (N type) well region and the high concentration second conductivity type (N ⁺ ) diffusion layer, the first conductivity type (P type) Si is formed.
Since the first conductivity type (P-type) guard ring layer having a higher concentration than the substrate concentration is formed by ion implantation, the leak current does not flow and the second conductivity type (N-type) well region and the high concentration second conductivity type are formed. The distance between the (N ⁺ ) diffusion layers can be reduced, and the degree of integration of the device can be improved accordingly.

[Brief description of drawings]

FIG. 1 is a sectional view of a main part manufacturing process of a semiconductor device showing an embodiment of the present invention.

FIG. 2 is a diagram showing a dependence of a threshold value (V _th ) of a field transistor on a distance between an N well region and an N ⁺ diffusion layer.

FIG. 3 is a cross-sectional view of a manufacturing process of a conventional semiconductor device.

FIG. 4 is a diagram showing a calculation example of a current gain (current amplification factor) h _FE of a field transistor.

[Explanation of symbols]

1 P-type Si substrate 2 SiO ₂ film 3 Phosphorus ion 4 N-well region 5 Channel stopper layer 6 Field oxide film 7 Gate oxide film 8 N ⁺ diffusion layer 9 P ⁺ diffusion layer 10 Resist 11 Boron ion 12 Guard ring region 13 P-type Card ring layer

Claims (2)

[Claims] 1. A well region of a second conductivity type formed immediately below a field oxide film formed on a Si substrate of a first conductivity type, and (b) immediately below the field oxide film, wherein: A channel stopper layer adjacent to the well region, (c) a high-concentration second conductivity type diffusion layer formed immediately below the gate oxide film connected to the field oxide film, and adjacent to the channel stopper layer, (d) the diffusion A semiconductor device comprising a first conductivity type guard ring layer having a concentration higher than an impurity concentration of the Si substrate extending from the lower portion of the layer to the channel stopper layer and the well region. 2. A well region of a second conductivity type is formed immediately below a field oxide film formed on a Si substrate of the first conductivity type, and a well region immediately below the field oxide film. Forming a channel stopper layer adjacent to the region, (c) forming a high-concentration second conductivity type diffusion layer formed immediately below the gate oxide film connected to the field oxide film, and adjacent to the channel stopper layer; ) A method of manufacturing a semiconductor device, wherein a first conductivity type guard ring layer is formed by ion implantation to reinforce the impurity concentration of the lower channel stopper layer of the field oxide film from the lower portion of the diffusion layer.