JPS6047457A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a CMOS device having high surge resistance by forming P type source and drain to an N type tab on an N<-> type Si substrate, shaping a P layer under a selective oxide film between the drain and a gate and forming a high withstand voltage FET and forming a low withstand voltage FET to a P type tab. CONSTITUTION:An SiO2 film 16 and an Si3N4 film 17 to which an opening is bored by a resist 18 are superposed to an N<-> type Si substrate 5 with an N type 6 and a P type 15, resists 19 are applied, and ions are implanted to form P<+> layers 8, 9. The resists 18, 19 are removed, and selective oxide films 7 are shaped. The Si3N4 film 17 is removed, and ions are implanted, thus forming a CMOS device containing a P type high withstand voltage FET as well as an N type low withstand voltage FET 14. When withstand voltage between the tab 6 and a drain electrode 4 is made previously lower than that between a source electrode 1 and the drain electrode 4 by selecting impurity concentration in the N tab, a gate oxide film 10 can be protected, and the CMOS device having high surge resistance is obtained.

Description

[Detailed Description of the Invention] [Prior Art] As a conventional semiconductor device of this type, T, Yan+agu
ehi, S, Morkmoto (IEDM'8l-
There is a field effect transistor with a drift layer shown by No. 255). This concept is illustrated in FIG. 1 for a P-type transistor. That is, in this FIG. 1, symbol (1) is a source electrode, (2) is a gate electrode, (3) is a drift layer, (4) is a drain electrode, and (
5) is an N-type silicon substrate, and (1) is selective oxidation! (SOP
), (9) Drift layer low concentration P current part, (10)
is the gate oxide film, (11) is the source high concentration P-type Uli,
(12) is a drain high concentration Pi portion.

The manufacturing process for this transistor begins with a 3Ω
- A silicon oxide film of about 500A on the high resistance N-type substrate (5) on the sub-plate, 1. After sequentially growing a silicon nitride film of about ooo A low concentration P type layer layer (9) is formed. Then, after removing the photoresist mask, using the silicon nitride film as a mask,
Selective oxidation is performed to form a selective oxide film (SOP) (7). Next, after removing the silicon nitride film, a gate oxide film (10) is formed, and this gate oxide film (10) is formed.
0) A gate electrode (2) is formed continuously from a part on the top to a part on the selective oxide film (7) of the drift layer (3). Then, using the resist and selective oxide film (7) on the gate electrode (2) as a mask, 1015/crn! Boron is implanted at a density of about
11) and a drain high concentration P type part (12) are formed and annealed. After that, a CVD silicon oxide film as a gate oxide film (10) is further formed on the entire surface of the substrate (5), and a contact hole is formed in this, and then electrode wiring is formed.

A source electrode (1) and a drain electrode (4) are formed.

In this transistor configuration, when a high voltage is applied to the drain electrode (4), the depletion layer becomes gate oxidized.
(10) It spreads into the low concentration P-type part of the drift layer from the end of the channel part immediately below, and in this way, this depletion layer increases the withstand voltage of the potential difference between the bottom electrode (1) and the drain electrode (4). is decided.

In addition, the selective oxide film (7) in the drift layer (3) part functions to improve the breakdown voltage between the gate electrode (2) and the drain electrode (4) and to equalize the electric field applied to the depletion layer. There is. And the operation of this transistor is
When the gate electrode (2) exceeds the threshold voltage, the channel directly under the gate oxide film (10) is turned on and holes begin to flow, passing through the depletion layer to the drain high concentration P portion (12). ).

However, in such a conventional field effect transistor with a drift layer, as mentioned above, the breakdown voltage between the source electrode and the drain electrode is determined by the breakdown voltage of the depletion layer, so if for some reason the drain electrode If a surge voltage is applied to the depletion layer and the voltage exceeds the withstand voltage of the depletion layer, the gate oxide film is easily destroyed, which is undesirable.

[Summary of the invention]

In view of these conventional drawbacks, the present invention provides a diffusion region (hereinafter referred to as TAB) of a conductivity type opposite to that of the substrate only in the portion of a high voltage field effect transistor incorporated in a semiconductor substrate.
) is provided, and the relationship between this tab and the drain electrode is
The voltage is lower than the withstand voltage of the source electrode and the drain electrode to maintain the gate oxide film.

[Embodiments of the invention]

Hereinafter, the second embodiment of the semiconductor device according to the present invention will be described.
This will be described in detail with reference to the drawings to FIG. 5. FIG. 2 shows a schematic configuration of a semiconductor device to which an embodiment of the present invention is applied, in this case a field effect transistor with a drift layer. In the device of the embodiment shown in FIG. 2, the same reference numerals as in the conventional device shown in FIG.
) J: ! Q is also a highly concentrated N-type tab.

In the manufacturing process of the transistor in the embodiment shown in FIG. 2, first, a silicon oxide film of about 500A is grown on a high-resistance P-type substrate (5) of 3Ω·tan or more, and the corresponding part of the high-voltage transistor is , using a photoresist mask to selectively ion-implant phosphorus at a density of about 10 cm and thermally diffusing it to form an N-type tub (6) with a higher concentration than the substrate (5). A high breakdown voltage field effect transistor is formed on this tab (6) by the same process as the conventional example shown in FIG. Also, the impurity placement of this tab (6) is determined so that the junction reverse breakdown voltage between the tab (6) and the drain high concentration P type portion (12) is lower.

Therefore, for some reason, the drain electrode (4) is
When a surge voltage is applied to the part where the surge rises quickly, the capacitance partial voltage is dominant, so the drain which is directly connected to the substrate (5) K as in the conventional example is The junction capacitance in contact with the tab (6) in this example is larger than the junction capacitance of the high concentration P-type part (12).
The voltage actually applied to the drain is lower in this embodiment.

In addition, in the case of this embodiment, for a negative surge that rises slower than this, the source electrode (1) and the drain electrode (4
) than the withstand voltage between the tab (6) and the drain/electrode (4).
), the drift layer (3)
Before the depletion layer generated in the channel area under the gate oxide film (10) exceeds the withstand voltage and destroys the gate oxide film (10), the charge applied to the drain electrode (4) reaches the gate oxide film (10). 6) to protect this gate oxide film (10). And even when a positive surge is applied,
Since the sheet resistance of the tab (6) is lower than that of the substrate (5), it provides better protection.

In the embodiment shown in FIG. 2, an N-type silicon substrate was used, but a P-type silicon substrate was used, and P was selectively applied to it.
Of course, the same effect can be achieved even if a semiconductor device including an NmO high iJ piezoelectric field effect transistor is constructed by providing a mold tab.

Next, this invention is 0MO8 (complementary is field effect transistor) 4? A manufacturing process according to an embodiment of the present invention is shown in FIGS. In this embodiment, in particular, the number of manufacturing steps for a C'MO8 semiconductor device to which the present invention is applied is different from that of a conventional C'MO8 semiconductor device that does not include a high-voltage transistor.
The number of manufacturing steps is the same as that of the semiconductor device having the same configuration, and the steps can be performed without changing the thin tube.

In this embodiment of FIG. 3 as well, the same reference numerals as in the embodiment of FIG. 2 indicate the same or corresponding parts.

In this example, first, a high resistance N vortex substrate of 3Ω・m or more (
5) Grow a silicon oxide film of about 500A on top, selectively implant phosphorus ions at a density of about 10'Kpm2 into the corresponding part of the high voltage transistor using a photoresist mask, and remove this resist once. After that, apply a new photoresist mask to the corresponding part of the low-voltage transistor other than the high-voltage transistor part for 10 minutes.
In the same way, boron with a density of about 1cm is selectively implanted into 1C, and after this resist is also removed, it is thermally diffused to form a highly concentrated N-type tab (
6) and a P-type tab (15) are formed, and the remaining silicon oxide film is removed (FIG. 3(a)).Next, a silicon oxide film 1 (16) of about 500A is formed on the substrate (5).
Then, silicon nitride films (17) are sequentially formed, and then a photoresist mask (18) is used to remove the silicon nitride film corresponding to the formation region of the selective oxide film (SOP) (7) for element isolation and drift layer. (17) is selectively removed (FIG. 3(b)). Next, using a photoresist mask (19) for element isolation, a low concentration P-type part (8) for element isolation and a low concentration Pff1 part (9 ) are simultaneously implanted with boron (20) (FIG. 3(c)), followed by each of the photoresist masks Cl8).

After removing (19), oxygen or H2O is thermally diffused to form a selective oxide film (1T) in the area where silicon nitride is not present.
SOP (7) is formed, and at the same time, an element isolation (SOP) and a trit layer (SOP) are also formed (FIG. 3(d)). In addition, silicon nitride film (
After removing 17) and performing channel implantation,
The silicon oxide film (16) is removed and the gate oxide film (10) is removed.
), and hereafter, in the same process as the conventional example except for the ion implantation process of the source and drain of the NN) runlister, a P-type high-voltage field effect transistor (14) is formed together with F and N-type low-voltage field effect transistors (14). This constitutes a semiconductor device including a transistor (FIG. 3(e)).

That is, in this step 9 and the embodiment shown in FIG.
) (7) and the low concentration P-type part of the drift layer (9
) and selective oxidation M (SOP ) ff) are CMO8s containing highly integrated, high-performance, high-voltage P-type transistors, which are formed using the same process without increasing the number of processes. The semiconductor device depicted can be manufactured in the same process as a normal CMO 8'M semiconductor device which does not include this.

In addition, here, as shown in FIG.
8) and the low-concentration P-type part (9) of the drift layer can be formed simultaneously in the same process. This is because optimal performance can be achieved when the impurity concentration of the P-type portion (8) is equal to .

As experimental data, changes in transistor characteristics when the amount of boron implanted to form the low concentration P-type part (9) of the drift layer is varied are shown in FIGS. The conditions at this time are that the lift length (21) shown in FIG. 3 (, ) is 4 μm.
, the gate length (22) is also 4 μm, and the gate width is 100
/1m, the thickness of the gate oxide film (10) is 600^, and the amount of boron implanted is 3.5X1013/1m in Figure 4 (,).
, the figure (b) is 5. OX 1013/cm2. The figure (c) is 8, OX 10 "/cm".

In the fourth case (c), when the potential difference between the drain electrode (4) and the source electrode (1) exceeds 40V, bipolar operation begins and the current suddenly increases;
The drain current tends to increase even below 0V. This tendency is observed in the low concentration P-type region where the depletion layer is a drift layer (9).
It extends more toward the channel region than the actual gate length, and the effective gate length becomes shorter. Therefore, in this case, it is shown that there is little point in using a drift layer to increase the breakdown voltage. Further, in the case of FIG. 4(b), when the potential difference between the drain electrode (4) and the source electrode (1) increases between 70 V or less and 20 V or more, the drain current tends to increase slightly.

In other words, this shows that the depletion layer is expanding in the channel region. Furthermore, FIG. 4(,) shows that the depletion layer almost extends toward the drift layer X.

Furthermore, in Fig. 4(,) and (b), the current value in the linear region and the current value in the saturation region are equal to each other, t''!, and their characteristics are also optimized, so there is no drift. The optimum boron implantation amount for forming the low concentration P-type part (9) of the layer is approximately 3.5-5.
OX 10"/cm2, and it can be said that there is no problem within this range. On the other hand, the impurity concentration of the low concentration P type part (8) for element isolation is a selective oxide film (SOP). (7) Determined by the withstand voltage between the threshold value of the Fisaki field transistor inevitably created above and the high concentration N current region and the low concentration Pi region for element isolation (8), both of which are usually around 20V. At that time, the amount of boron implanted to form the low concentration P-type part (8) for element isolation is approximately 3.5 x 10 "7 cm". The amount of boron implanted to form the acoustic P-type part (9) and the amount of boron implanted to form the low concentration P-type part (8) for the element part are shown in the same view, that is, 3. It can be set to 5 x 10”/cm2.

Furthermore, in the high-voltage field effect transistors of the above embodiments, the gate electrode (and the drift layer (3)) is preferably formed so as to surround the drain high concentration Pi portion (12), that is, in an annular shape. Although it is common, the gate electrode (2) can also be formed in a linear shape.

However, in this case, the following restrictions arise due to the mask alignment accuracy in the manufacturing process.

A situation for this purpose is shown in an embodiment in FIG. In the embodiment shown in FIG. 5 as well, the same reference numerals as in the embodiments shown in FIGS.
) is the length and drain width of the drain in the direction perpendicular to the current flow direction of the field effect transistor), (24) is the length and north width of the source in the same upward direction, and (25) is the length of the drift layer in the same upward direction. Drift layer width)
, (26) is a photoresist mask for element isolation with mask displacement, and (27) is the gate length due to mask displacement.

In this embodiment of FIG. 5, if the drift layer 11 (25) is designed to match the source width (24), the mask misaligned elements will be Heat photoresist mask (2G
), the end of the drift layer (3) protrudes from the end of the source region, and the gate length (27) due to this mask shift becomes shorter than the intended gate length, making it impossible to control the gate length. There is a risk that it will disappear. Therefore, in this embodiment, the width of the drift layer (25) is larger than the width of the source (24).
) is set shorter to improve this. Additionally, since the withstand voltage at the end of the drain highly doped P-type portion (12) decreases, a lightly doped P-type portion must be formed around the P-type portion (12). Therefore, in this embodiment, a photoresist mask (19) for element isolation is provided outside the drain heavily doped P-type region (12), and the drain center (23) is set shorter than the source width (24). We are improving this. That is, the gate electrode (2) can be formed in a straight line in this way.

〔Effect of the invention〕

As detailed above, according to the present invention, the high withstand voltage field effect transistor is formed in the tab which is selectively formed on the semiconductor substrate and is higher than the substrate, so the surge resistance is significantly improved. It can be improved to 0 MO8 compared to conventional
It can be applied to semiconductor devices with the same structure without changing or increasing any part of the manufacturing process, and the gate electrode of this high-voltage field effect transistor can also be formed in a straight line, which contributes to miniaturization. It has advantages such as advantages.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the general structure of a semiconductor device including a conventional high voltage field effect transistor, FIG. 2 is a cross-sectional view showing the general structure of the same semiconductor device according to an embodiment of the present invention, and FIG. , ) or ) are sectional views sequentially showing the manufacturing process when an embodiment of the present invention is applied to a semiconductor device with 0MO8 configuration, and FIGS.
) is a characteristic diagram when the impurity concentration of the low concentration P-type part of the drift layer of the high voltage field effect transistor is changed, and FIG. 5 is a cross-sectional view showing the general structure of the semiconductor device according to another embodiment. (1)...Source electrode, (2)...Gate electrode, (3)...Drift layer, (4)...Drain electrode, (5)...N-type silicon Substrate, (6)
...N-type tab, (T) ... selective oxide film (sop
), (8)...Low concentration P type part for element isolation, (9)...
...Drift layer low concentration Pi part, (io)...Φ
Fist gate oxide film, (11)...Source high concentration P type part, (12)...Drain high concentration P type part, (13)...
...High concentration N-type part for channel cut, (14?...
・N-type field effect transistor, (15)...P-type tub, (16)...silicon oxide film, (17)...
- Silicon nitride L (1B) - Exposure... Photoresist mask, (19)... Photoresist mask for element isolation. Agent Masuo Oiwa 23 Figure 1 Figure 2 Figure 4 VDS VDS VDS Figure 5 Procedural amendment (voluntary) 3. Person making the amendment 5. Detailed description of the invention in the specification to be amended 6. Amendment Contents (1) Correct "Gate film/oxide film (10) J" on page 3, lines 18 to 19 of the specification to be "smooth coat film." (2) "Opposite conductivity type to the substrate" on page 5, line 10 of the same book
is corrected to "same conductivity type as the substrate". (3) "P type" on page 6, line 7 of the same book is corrected to "1N type". (4) r 10 ”cm2J on page 6, line 10 of the same book [
10′2/cm” J. (5) In the same book, page 8, line 19, “the high withstand voltage” is changed to “the P
Corrected as "high pressure resistance". (6) "High withstand voltage" on page 9, line 2 of the same book is rP type Takaichi/l
Correct it as "pressure". (7) "Low pressure" on page 9, line 3 of the same book is corrected to "1N type". (8) "N-type high-rigidity voltage field effect transistor and low voltage" on page 9, lines 16 to 17 of the same book is corrected to "N-type". ”2

Claims (3)

[Claims] (1) On the semiconductor substrate of the first conductivity type, diffusion regions of the first conductivity type and the second conductivity type, which are also highly concentrated in this substrate, are selectively formed. In this method, a source and a drain of the second conductivity type are formed, a selective oxide film is formed between the drain and the gate part, and a region is formed by implanting impurities of the second conductivity type under the selective oxide film. 1. A semiconductor device comprising a high voltage field effect transistor and a low voltage field effect transistor formed on a second conductivity type diffusion region. (2) The impurity implantation region under the selective oxide film is formed in the same manner as the impurity implantation region for element isolation formed under the selective oxide film on the substrate other than the first conductivity type diffusion region. A semiconductor device according to claim 1. (3) Source rflt of high voltage field effect transistor
- The semiconductor device according to claim 1, characterized in that the drain width is also increased. The present invention relates to a semiconductor device, particularly a semiconductor device VC including a high voltage field effect transistor.