JPS63308385A - Manufacture of buried-gate field-effect transistor - Google Patents

Abstract

PURPOSE:To enable the fine processing to be performed without any mask matching by a method wherein, after forming.source drain regions without previously burying a gate electrode in a semiconductor substrate, the gate electrode is formed in a selfalignment manner by impurity implantation using the source.drain regions as masks. CONSTITUTION:A semiconductor substrate 1 is oxidized to form a gate oxide film 5 and then a polycrystalline silicon layer 7 to be a source.drain region of a buried gate type FET is formed. Next, a resist 33 is patterned and the uncovered polycrystalline Si layer 7 is etched away. At this time, both source.drain regions 8 are formed while the space between the two regions 8 is made into a window to form the buried gate electrode as well as a channel region 9. Furthermore, phosphorus ions 4 are implanted in the buried gate region through the gate oxide film 5 by ion implantation process. Through these procedures, an n<+> gate electrode 6 can be formed in a selfalignment manner through the gate oxide film 5 using the polycrystalline Si layers forming the source.drain regions as masks to enable the fine processing to be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a buried gate field effect transistor (hereinafter referred to as FET), which is employed, for example, in a silicon thin film transistor.

[Conventional technology]

A buried-gate FET uses a low-resistance semiconductor region buried in a high-resistance semiconductor substrate as a gate, and a channel region and source region of a semiconductor thin film formed on the substrate via an insulating film.
It has a drain region. Figure 2 (al~tc
+ indicates the conventional manufacturing method. First, as shown in Figure (al), an oxide film 2 is first formed on a silicon substrate 1, and a resist 31 with selective openings only at the gate portion is formed by photolithography. After partially etching away the oxide film 2, when forming an n-type gate electrode, for example, impurity diffusion is performed by implanting phosphorus ions 4. Instead of ion implantation, a conventional gas diffusion method using PoCj2 is used. As shown in FIG. 2), the gate oxide film 5 is formed by reoxidation, and at the same time, the n-type diffusion N6 of the buried gate electrode portion is formed by heating at that time. Thereafter, a polycrystalline silicon layer 7, which will become the channel region and source/drain region of the FET, is deposited by CVD, and after forming a pattern of resist 32 with openings only in the source/drain region, phosphorus ions 4 are implanted again. Thereafter, source/drain regions 8 are formed in the polycrystalline silicon by annealing as shown in FIG. 2 tc+, and a channel region 9 remains between them.

[Problem that the invention seeks to solve]

In such a step in the conventional manufacturing method, the alignment of the buried gate electrode 6 and the source/drain region 8 depends on the mask alignment accuracy of photolithography technology. Since the accuracy of the aligner is at the level of ±1 to 1.5 n, conventional methods that require consideration of this alignment margin have a limit to the microfabrication of transistors.

SUMMARY OF THE INVENTION An object of the present invention is to address the above-mentioned problems, improve alignment accuracy of gate electrodes with source/drain regions, and improve the alignment accuracy by 8i compared to conventional methods. 1. It is an object of the present invention to provide a method for manufacturing a buried gate type FET suitable for miniaturization.

[Means for solving problems]

In order to achieve the above object, the method of the present invention forms an insulating film on a semiconductor substrate, and then forms two source/drain regions made of a semiconductor layer with a low impurity concentration on the insulating film, separated from each other. Next, using the source/drain regions as a mask, impurities are introduced into the semiconductor substrate to form a buried gate electrode, and furthermore, a channel region made of a semiconductor layer with a low impurity concentration is formed between the source/drain regions.

[Effect]

In the above method, the buried gate electrode is formed in self-alignment by introducing impurities using the already formed source/drain regions as a mask, so there is no need to consider alignment margins, and pattern miniaturization is possible. It becomes possible.

〔Example〕

An embodiment of the present invention is shown in FIG.
Parts common to those in the figure are given the same reference numerals.

First, the semiconductor substrate 1 is oxidized to form a gate oxide film 5 (Fig. a). Here, the material of the substrate 1 may be monocrystalline silicon or polycrystalline silicon, which is often used in thin film transistors. Source of gate type FET
Form a polycrystalline silicon layer 7 that will become a drain region (
Figure b), which is deposited in the form of doped polycrystalline Si by a conventional low pressure CVD method. However, after depositing undoped polycrystalline St, impurities may be introduced by Poα gas diffusion or ion implantation.A typical value is a sheet resistance of 20 to 40 Ω/gate for the source/drain region. As shown in FIG. 1 (C1), a resist 33 selectively covers the source/drain region.
The polycrystalline St layer 7 not covered is etched away by dry etching. At this time,
Figure 1! Both source/drain regions 8 shown at d+ are formed, and the space between them serves as a window for forming a buried gate electrode, and is also a portion where a channel region is formed. Next, gate oxidation It! is performed by ion implantation. Phosphorus ions 4 are implanted into the buried gate region at 150 ksV to a density of about 5×10 15 /c++1 through J5.

At this time, the region away from the gate electrode is covered with a resist 34, but the pattern does not require alignment precision.In this way, the gate oxide film is formed using the polycrystalline 5iJi8 that forms the source/drain regions as a mask. Since the n-layer gate electrode 6 shown in FIG. A crystalline Si layer 9 is formed by a low pressure CVD method.This creates a buried gate FET using a diffusion layer in a semiconductor substrate with the gate as a pole opposite to a normal insulated gate FET.
can be made using self-alignment technology between the gate and source/drain regions.

Note that terminal electrodes or wiring for connecting the buried gate 7 and the source/drain region 8 with an external circuit or with elements formed in other regions of the semiconductor substrate 1 are connected to the buried gate or the source/drain region, respectively. It can be formed in a similar manner at the same time as the formation.

〔Effect of the invention〕

According to the present invention, the gate electrode is not buried in the semiconductor substrate in advance, and after the source/drain '1IJr region is formed, it is formed in self-alignment by introducing impurities as a mask, so there is no need for mask alignment. Since this method is not affected by mask alignment accuracy, fine processing becomes possible, and it is effective for miniaturizing devices and increasing their density. Furthermore, since the capacitance of the gate type is also reduced, the speed of the buried gate type FET can be increased.

[Brief explanation of drawings]

FIGS. 1A to 1E are cross-sectional views sequentially showing the manufacturing process of an embodiment of the present invention, and FIGS. 2A to 2C are cross-sectional views sequentially showing the manufacturing process of a conventional method. , semiconductor substrate, 4: phosphorus ion, 5: gate oxide film, 6
: gate electrode, 8: source/drain region. m-, generation:,'1M+c・Kamijoyama 1-1 i+42゛Figure 1

Claims (1)

[Claims] 1) After forming an insulating film on a semiconductor substrate, two source/drain regions made of a semiconductor layer with a high impurity concentration are formed on the insulating film, separated from each other, and then, using the source/drain regions as a mask, the semiconductor substrate is A method for manufacturing a buried gate field effect transistor, comprising the steps of: introducing impurities to form a buried gate electrode; and further forming a channel region made of a semiconductor layer with a low impurity concentration between the source and drain regions.