JPH0461164A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To simplify a manufacturing process by etching the poly-Si film of a depletion transistor conducting ROM coding up to the intermediate section of film thickness thereof, implanting arsenic ions to the whole surface and simultaneously forming source-drain and a channel impurity diffusion layer. CONSTITUTION:A gate oxide film 12 is formed onto a p-type Si substrate 11 through thermal oxidation, and B<+> ions are implanted to form a p- channel diffusion layer 13. Poly-Si is deposited in a region 11A, in which a depletion transistor is shaped, and a region 11B, in which an enhancement transistor is formed, through the gate oxide film 12, phosphorus is doped, and poly-Si films 14A, 14B are formed through patterning. A resist film 15 is shaped on the whole surface on the substrate 11, an opening section is formed in the region 11A, the poly-Si film 14A is exposed, and film thickness required is left through etching. The resist film 15 is removed, and As<+> ions are implanted to the whole surface of the substrate 11, thus simultaneously forming source S.drain D and an impurity diffusion layer 16. Accordingly, manufacturing cost can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a method for manufacturing an Nf-v channel vertical product AND type read-only semiconductor memory device. It is.

<Mouth> Conventional technology FIGS. 2 to 4 are explanatory diagrams related to conventional examples.

Figure 2 is a block diagram of a Nf~Nel vertical product AND type read-only semiconductor memory device (NehAND type ROM), and the portions surrounded by broken lines are matrix transistors (depression transistors, enhancement transistors).
It shows.

FIG. 3 shows a dabre-methion transistor (LA) and an enhancement transistor (IB) manufactured according to the conventional example. In the figure, 1) is P-type Si
A substrate, (2) a selectively oxidized (gate oxidized) Si-film, (S) a source, (G) a gate, and (D) a drain.

Figure 4 shows the RO of the depletion transistor (IA)
It is a process diagram when performing M coding.

In the figure, (3) is a resist film, (4) is a P-channel diffusion layer formed by implanting B1 ions for the enhancement transistor (IB), (5) is a poly-Si film for gate, and (6) is a P-channel diffusion layer formed by implanting B1 ions for the enhancement transistor (IB). ) is a BoJSi film (
5) is an impurity that is implanted into the source (S) and drain (D> formation regions by ion implantation method, and is phosphorus (P).
+).

Note that such prior art includes Japanese Patent Application Laid-Open No. 6O-Q157 (HOIL 27/10).

<C> Problems to be Solved by the Invention According to the conventional example, ion implantation for Rolff-ding of a depletion transistor (IA) is performed through a poly-Si film (5) as shown in FIG. Then, phosphorus ions must be implanted into the P-type Si substrate (1).

Therefore, an accelerating voltage of about 300 KeV to 400 KeV is required to cause the phosphorus ions to pass through the poly-Si film (<5), and there is a problem in that this accelerating voltage cannot be obtained with a normal ion implanter.

The present invention has been made in view of the problems of the conventional method, and an object of the present invention is to provide a method for manufacturing a semiconductor device that enables ROM coding using an ion implantation device that normally has a voltage of about 50 KeV to 15 OKeV. do.

(d) Means for Solving the Problems The method for manufacturing a semiconductor device of the present invention is described in the first embodiment.
As shown in Figures A to 1P, a P-type Si substrate (11)
A step of forming a gate oxide film (12) in the region where the first transistor is to be formed (IIA) and the region where the second transistor is to be formed (IIB), and the region where the first transistor is to be formed (IIA) and a step of forming a ℃ poly-Si film (14A) (14B) through the gate oxide film 12) in the region (IIB) where the second transistor is to be formed, and forming a resist film (14B) on the entire surface of the substrate (11). 15), forming an opening in the region (IIA) where the first transistor is to be formed, and exposing the poly-Si film (14A); A step of etching halfway through the film thickness, removing the resist film (15), and implanting arsenic ions over the entire surface. By including the process of simultaneously forming the source (S) and drain (D) of the second transistor and the N-type channel impurity diffusion layer (16) of the first transistor, the above objective is repeatedly defeated. .

According to the present invention, the poly-Si film (14A) serving as the gate electrode of the first transistor (depletion transistor) for ROM coding is etched to the middle of the film thickness, and then the resist film (15) is etched. The source (S) and drain (D) of the first and second transistors and the N-type channel impurity diffusion layer (16) of the first transistor are simultaneously formed by removing arsenic ions over the entire surface. I need work.

This allows 300 Ke for ROM coding.
It becomes possible to eliminate the need for a high-energy ion implantation device such as V to 400 KeV. Furthermore, the manufacturing process can be simplified because the conventional ion implantation for forming the source (S) and drain (D>) can also be used as ion implantation for ROMT-J-ding.

(f) Example Next, an example of the present invention will be described with reference to the drawings.6 Figures 1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an example of the present invention. .

First, as shown in FIG. 1A, a region (IIA) where a depletion transistor is to be formed on a P-type Si substrate 11)
and the region where the enhancement transistor is formed (II
B) Approximately 300 deer gate oxide films (1
2> and then accelerates B+ ions with an energy of 70
KeV, injection volume I x 10'! ion, s/c
A P''-f-v tunnel diffusion layer (13) is formed by ion implantation under the condition of m''.

Next, as shown in FIG. 1B, the region (IIA) where the deep transistor is formed and the region (IIB) where the enhancement transistor is formed are formed through the gate oxide film (12). After depositing about 4,000 silicon oxides by LPCVD, doping with phosphorus to lower the resistance, buttering, etching, and forming a poly-Si film (14A>(14B)) that will become the gate electrode. .

Next, as shown in FIG. 1C, a resist film (15) of about 1.0 μm is formed on the entire surface of the group &(11)
A ℃ photolithography process is performed using a photomask for coding, an opening is made in the region (ilA) where the depletion transistor is to be formed, and a poly-Si film (], 4A) is formed.
expose. Next, the poly-Si film (
14A) for about 2000 people, 1 go, tupung, 2000
In order to prevent the etching of the Ga (oxide film <12) by leaving a film thickness of approximately 0.1 DEG, etching is carried out under conditions with a high -1 etching speed ratio of poly-Si to Sin. ,,i: The etching of the octopus is anisotropic error ring (
For example, RIE method) or isotropic coupling (drycoping using a gas, or wet or gouging using an etching solution) may be used.6 When isotropic -C coupling is used, it is possible to
Although the controllability of the Yuppungu lid is inferior to that of tucking, since the tubbing progresses in the lateral direction of the poly-Si film (14A), the gate length is reduced by 1. It has the advantage of being able to direct GM. After that, as shown in the first diagram, the oxide film (1
5) is removed, and As "ions" are implanted onto the entire surface of the substrate <11) using the ion implantation method under the following conditions: acceleration, energy 80 keys, implantation amount 5 x 10 "1 ounces, and the source (S). N-type Nayan channel impurity diffusion Jti (
16) are formed at the same time.

In this way, the poly-Si film (14A) as the gate electrode of the depletion transistor (ilA) is etched to a zero film thickness of about 2000 using a photomask for ROM coding. By performing ion implantation for drain formation, As+ ions are passed through the poly-Si film (14A) and N
type channel impurity diffusion layer <16) can be formed at the same time.

(G) Detailed description of the invention As described above, according to the present invention, the conventional ion implantation for forming the source/domain can also be used as the ion implantation for ROM coding of the depletion transistor. It becomes possible to significantly reduce the manufacturing cost of semiconductor devices and speed up the processing process. .

[Brief explanation of drawings]

1A to 1A are cross-sectional views for explaining the method of manufacturing a semiconductor device according to the present invention, and FIGS. 2 to 4 are explanatory views for a conventional example. Fig. 1 Hachidou Flash Fig. 2 Fig. DD 113 Fig. II Fig. 4

Claims (1)

[Claims] (1) A step of forming a gate oxide film in a region where a first transistor is to be formed and a region where a second transistor is to be formed on a semiconductor substrate of one conductivity type; forming a polycrystalline semiconductor film via the gate oxide film in a region where a first transistor is to be formed, forming a resist film over the entire surface of the substrate, and providing an opening in a region where a first transistor is to be formed; a step of exposing the polycrystalline semiconductor film; a step of etching the polycrystalline semiconductor film exposed in the above step to the middle of its film thickness; removing the resist film, implanting impurities of opposite conductivity type into the entire surface, and etching the polycrystalline semiconductor film exposed in the above step to the middle of its film thickness; 1. A method for manufacturing a semiconductor device, comprising the steps of simultaneously forming a source/drain of a second transistor and a channel impurity diffusion layer of opposite conductivity type of a first transistor. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the transistor is a depletion transistor, the second transistor is an enhancement transistor, and the impurity is a phosphorus ion or an arsenic ion.