JPS5917865B2 - hand tai souchi no seizou houhou - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and an object of the present invention is to reduce the difference in surface unevenness in each manufacturing process of so-called MOSIC, etc., and to facilitate the manufacture of ICs with minute patterns. , and provides a manufacturing method that reduces the influence of mask misalignment, etc.

The manufacturing method of so-called Si gate, P-channel MOSIC is to first form a thick field oxide film (about 1 μm in thickness), then etch the parts where the source, drain, gate, etc. will be formed, and then add a new gate oxide film. film (thickness approx. 100
0λ).

Therefore, the difference in thickness between the field oxide film and the gate oxide film on the surface of the semiconductor substrate is approximately 1 μm, resulting in a large step. Grow polycrystalline silicon (approximately 8000A thick) on the gate oxide film and field oxide film to form a gate pattern, and use this gate as a mask to etch the gate oxide film to form the source and drain. expose the place. Next, P-type impurities are diffused into the polycrystalline silicon and the source and drain regions.

Next, silicon dioxide is grown by CVD '0 or the like, and a window is opened in the contact area to form a metal wiring. In such a manufacturing method, the height difference due to polycrystalline silicon is approximately 8000Λ.

The size of this step makes it difficult to form minute patterns. Further, the metal wiring that crosses the polycrystalline silicon layer often shows disconnection at the step portion. Furthermore, when forming a field oxide film, for example, in the case of a substrate containing phosphorus as an impurity, a pile-up of phosphorus impurities occurs near the oxide film interface, which has the effect of lowering the threshold voltage VT of the field oxide film. A thicker field oxide film thickness is required.Also, the source and drain locations where contacts are to be formed are located at the lowest points relative to the substrate surface, while the contact locations for the gates are located at the lowest points relative to the substrate surface. ,
The field 5 is located at a height equal to the thickness of both the oxide film and the polycrystalline silicon. For this reason, when photoresist is applied to the surface of the substrate, the thickness of the photoresist film differs greatly in the area where the contact area should be opened, and for this reason, in the case of minute patterns, it is difficult to open the window in the thick photoresist film. becomes difficult. The present invention solves the above-mentioned conventional drawbacks and provides a manufacturing method particularly suitable for MOSIC, and one embodiment thereof will be described below with reference to the drawings.

The embodiment of the invention shown in FIGS. 1-9 is a silicon gate, P
This is an example of a channel type MOSIC. In FIG. 1, 1 is an n-type silicon substrate, with phosphorus as an impurity.
It has a concentration of about 1×10 16 at0 ms/Crll. 2 is an insulating layer formed by oxidizing the substrate 1, which is to become a part of the gate oxide film or field oxide film, and has a thickness of 100 mm.
The width is approximately 0λ, and a window is opened in a portion where a diffusion layer is to be formed, exposing the silicon surface of the substrate.

3 is a polycrystalline silicon layer having a thickness of about 2000λ and is formed on the entire surface.

After this, a silicon nitride 4 which is an oxidation-resistant film is formed on the silicon layer 3, and this silicon nitride 4 is selectively etched using the pattern of the photoresist 5.

Impurity ions 6 are used to form a channel stopper for preventing parasitic MOSTr operation, and are selectively implanted into the semiconductor substrate in the pattern of the photoresist 5.

7 indicates implanted ions.

For 6 and 7, phosphorus is used for the P channel, and boron is used for the N channel, but they do not necessarily have to be used (FIG. 2).

Next, when the photoresist 5 is removed and oxidation is performed to form a field oxide film, the silicon nitride 4 is removed.
The portion of the polycrystalline silicon 3 not covered by the oxide becomes a field oxide film 8 (FIG. 3).

Next, the silicon nitride 4 is removed and polycrystalline silicon 9 is formed on the entire surface to a thickness of about 2000 nm. In FIG. 4, 9' is a portion where polycrystalline silicon intersects with field oxide film 8. In FIG. Next, a pattern of the phosphorus-doped oxide film 10 is formed to make ohmic contact with the n-type substrate, and boron impurities are diffused over the entire surface, and the area under the phosphorus-doped oxide film 10 becomes n-type polycrystalline silicon. An n-type diffusion layer 12 is also formed in the substrate, and boron is diffused in other areas, so that the polycrystalline silicon 9 becomes P-type polycrystalline silicon, and a P-type diffusion layer 11 is also formed in the substrate. Next, the glass layer and phosphorus-doped oxide film 10 on the surface are removed, and silicon nitride 13 is formed on the entire surface (
Figure 5).

Next, a pattern 14 is formed by depositing aluminum, for example, on the entire surface to serve as a mask for ion implantation, and silicon nitride 13 and a portion of polycrystalline silicon 9 are selectively etched using this pattern.

The thickness of the polycrystalline silicon 17 in the etched portion is, for example, 1500λ. Next, impurity ions 15 for forming the source and drain, such as boron ions, are introduced into the substrate by an ion implantation method using the aluminum pattern as a mask to form the source and drain 16 (FIG. 6).

In this ion implantation, impurities must be introduced into the substrate through the polycrystalline silicon 17 and the gate oxide film 2'. On the other hand, impurities must not be introduced into the channel stopper 7, so the thickness of the oxide film at 8 is equal to the thickness of the oxidized polycrystalline silicon 3 added to the gate oxide film 1000. There is. When silicon is oxidized, the oxide film is almost twice as thick, so at point 8, 20008 of the polycrystalline silicon 3 becomes an oxide film of 4000, for a total thickness of 5000λ. When performing ion implantation, assuming that the range of impurity ions is approximately the same for silicon and silicon dioxide, impurity ions are introduced into the substrate through a thickness of 2500λ in terms of silicon where the source and drain 16 are to be formed. There must be. On the other hand, at this time, the field oxide film 8 has a thickness of 5,000 silicon equivalents at the channel stopper 7, and if the ion acceleration voltage is appropriately selected, impurities can be introduced only into the source and drain regions, and virtually no other parts can be introduced. It may not be possible to introduce it. During this ion implantation, a mask may be provided in addition to the locations where the source and drain are to be formed. Next, the aluminum pattern 14 serving as a mask is removed, and the polycrystalline silicon in the portions not covered by the silicon nitride 13 is oxidized (FIG. 7).

For example, polycrystalline silicon 17 with a thickness of 1500λ is oxidized to silicon dioxide 18 with a thickness of approximately 3000λ. Next, the silicon nitride 13 is removed, and a silicon dioxide layer 19 is grown on the entire surface by CVD (FIG. 8).

Next, a window is opened in the silicon dioxide layer 19 to expose a portion of the surface of the polycrystalline silicon layer that is required as a contact. By the way, the silicon nitride 13 does not necessarily need to be removed as described above, but is left in place, a CVD silicon dioxide layer is grown, a window is formed in the silicon dioxide layer, and then the silicon nitride 13 is removed. 13 may be exposed to expose the polycrystalline surface as a contact. Next, aluminum is vapor-deposited and the wiring pattern 20
By forming a MOSIC as shown in FIG.
can be formed. The manufacturing method described above is
It becomes possible to use the same ion implantation mask for the channel stopper and the same pattern for forming the field oxide film.

Further, since the semiconductor substrate is not oxidized when forming the field oxide film, the threshold value of the parasitic MOSTr does not vary due to impurity segregation. Furthermore, since the field oxide film is formed by selective oxidation of polycrystalline silicon, the height difference between the field oxide film and other parts is less than % of that of the conventional method. Furthermore, the source and drain are formed in a self-aligned manner, and
Since oxidation and insulation are performed in the same pattern, an extremely flat surface can be obtained. Furthermore, since the locations where contacts with the metal wiring are to be provided are at approximately the same height, opening the window is extremely easy. Thus, the method of the present invention
It has excellent industrial value by making it possible to reduce the difference in surface unevenness during the manufacturing process, making it easier to manufacture ICs with smaller patterns, and reducing the effects of misalignment of IC masks. be.

[Brief explanation of drawings]

1 to 9 are cross-sectional views of the manufacturing process of a P-channel silicon gate MOSIC according to an embodiment of the present invention. 1... n-type semiconductor substrate, 2, 8, 18, 19.
...Silicon dioxide, 3,9,91,17...
...Polycrystalline silicon, 4,13...Silicon nitride, 5...Photoresist, 6...
... Phosphorus ion, 7 ... Injected phosphorus impurity, 10 ... Phosphorus dope [■■ type diffusion layer, 1
4...Mask material for ion implantation, 15...
- Boron ion, 16... Injected boron impurity, 20... Aluminum wiring.

Claims (1)

[Claims] 1. An insulating film in which diffusion layer formation portions adjacent to the source and drain of a transistor are formed on one main surface of a semiconductor substrate, and a first polycrystalline semiconductor layer provided thereon, the first polycrystalline semiconductor layer A first oxidation-resistant film is provided on a portion of the first polycrystalline semiconductor layer other than the upper field oxide film forming portion, and
oxidizing the portions not covered with the oxidation-resistant film to form a field oxide film, and removing the first oxidation-resistant film and depositing a second polycrystalline semiconductor layer on the first polycrystalline semiconductor layer. a step of growing a crystalline semiconductor layer, a step of introducing an impurity into the semiconductor substrate in the opening of the insulating film to form a diffusion layer adjacent to the source and drain, and a step of forming a diffusion layer on the second polycrystalline semiconductor layer. A second oxidation-resistant film is provided on the source and drain forming regions, and a portion of the second oxidation-resistant film and the second polycrystalline semiconductor layer on the source and drain forming regions are etched, and the source and drain regions of the semiconductor substrate are etched.
A step of introducing impurities into the drain formation region to form source and drain regions, and a step of oxidizing the portion of the polycrystalline semiconductor layer not covered with the second oxidation-resistant film to form an insulating film. A method for manufacturing a semiconductor device, comprising: