JPS60261172A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the expansion of a diffused layer into a channel part and to prevent the deterioration of characteristics of an element, by suppressing the elongation of the diffused layer in a direct contact part. CONSTITUTION:A thin oxide film 23 is formed on a first conducting P type silicon substrate 21. The direct-contact forming region of the oxide film 23 is partially removed. Then a polycrystalline silicon film 24 is deposited on the entire surface of the semiconductor substrate 21 by a CVD method. Thereafter, a control layer for impurities, e.g., a CVD oxide film, is formed at a part corresponding to the direct contact region on the polycrystalline silicon film 24. Then, phosphorus is added as the second conducting type impurities into the polycrystalline silicon film 24. The phosphorus is simultaneously introduced into the semiconductor substrate 21 directly below the polycrystalline silicon film 24, and an N layer 26 is formed. Since the control layer is provided in this way, the amount of impurity introduction into the silicon substrate becomes less.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a contact between a semiconductor substrate and an electrode layer in an MO8 type semiconductor device.

[Technical Background of the Invention] Generally, in a silicon gate MO8 type semiconductor device, contact is made between an impurity layer (source, drain) formed in a silicon substrate and a polycrystalline silicon wiring layer on the silicon substrate. In this case, so-called direct contact is used.

Conventionally, this direct contact is formed, for example, by a method as shown in FIG. That is, first, a thick (approximately 1 μm) separation region is formed on the surface of the P-type semiconductor substrate 11.
At the same time as the oxide film 12 is formed, a thin (approximately 700 wafer) oxide film 13 is formed in regions that will become transistors and diffusion wiring. Thereafter, ion implantation is performed through oxidation [113] into the region that will become the channel of the transistor, and the threshold value VT is controlled. Next, etching is performed to locally remove the oxide film 13 in the portions that will become direct contacts, and then a polycrystalline silicon film 14 with a thickness of about 4,000 wafers is deposited over the entire surface. Then, in order to use this polycrystalline silicon M14 as a wiring, the semiconductor substrate 11 is POC+
3. After leaving in the atmosphere for several minutes, P (phosphorus) is added into the polycrystalline silicon film 14 to obtain a desired resistance value, and impurities are introduced into the silicon substrate 11 through this polycrystalline silicon film 14 to add N. Form layer 15. After this, polycrystalline silicon l1l114 was coated with PEP (Photo [ng
raving process) to form wiring. In addition, 16.17 is the N'' layer which becomes the source and drain, 18 is the gate electrode of polycrystalline silicon,
Reference numeral 19 indicates an AI (aluminum) electrode lead terminal, and 20 indicates an insulating layer.

Problems with Background Art] However, in the above conventional method, polycrystalline silicon l
! The N layer 15 formed in the silicon substrate 11 immediately below through the N layer 14 is heated to a high temperature (~1000 nm
C) for a long time (several tens of minutes to several tens of minutes), it penetrates deeply into the silicon substrate 11 and spreads widely. In deep objects, the vertical depth x, L is 2 μm or more, which also extends in the lateral direction, and its spread (lateral
) is close to 2 μm.

Therefore, it is difficult to miniaturize the area around the direct contact. Furthermore, if a direct contact is formed near the MO8 type transistor, the diffusion layer extends below the gate, resulting in degraded characteristics.

Furthermore, in a pattern in which direct contacts are adjacent to each other, the lateral Xj extends from both scattering layers, so the influence thereof becomes large, resulting in a design drawback in that the distance of the diffusion pattern cannot be reduced.

[Purpose of the Invention] The present invention has been made in view of the above-mentioned circumstances, and its purpose is to provide a method for manufacturing a semiconductor device that prevents deterioration of characteristics due to direct contact formation and allows for miniaturization. .

[Summary of the Invention] The present invention forms a thin oxide film on a semiconductor substrate of a first conductivity type, partially removes a direct contact formation region of this oxide film, and then deposits polycrystalline silicon over the entire surface of the semiconductor substrate. Depositing a film.

Thereafter, a control layer for impurities, such as a cvoiia film, is formed on the polycrystalline silicon film at a portion corresponding to the direct contact region. Thereafter, impurities of a second conductivity type are added to the polycrystalline silicon substrate, and at the same time, impurities are introduced into the semiconductor substrate below the same polycrystalline silicon substrate to form a direct contact.

According to the above method, since there is a control layer, the amount of impurities introduced into the silicon substrate is reduced. For this reason, even if heat treatment is performed in a post-process, the expansion of the diffusion layer in the direct contact portion is reduced, thereby preventing deterioration of device characteristics and also making it possible to miniaturize the device.

[Embodiments of the Invention] Hereinafter, an example in which an embodiment of the present invention is applied to a manufacturing process of an N-channel MO8 type transistor will be described with reference to the drawings. First, as shown in Figure 2 ('a), P
After pre-oxidizing the entire surface of the mold silicon substrate 21, a nitride film (
Si 3 N41 is deposited only on the region where the element is to be formed. Subsequently, oxidation is performed using this nitride film as a mask to form a field oxide film 22 with a thickness of approximately 1 μm.

Next, after removing the nitride film, thermal oxidation is performed to
0 gate oxidation [123] is formed. Here, Ejξ−nhancement), D (De
Ions are implanted into the channel region using a pletion type mask. After that, shown in the same figure (b)! The gate oxide film 23 in the area where the direct contact is to be formed is locally removed in this manner. Subsequently, a polycrystalline silicon film 24 is deposited over the entire surface by CVD. Thereafter, control is applied to a portion of the polycrystalline silicon substrate 21 corresponding to the region where the direct contact is to be formed.
A pattern of the D oxide film 25 is formed.

Thereafter, this silicon substrate 21 is placed in a POC+3 atmosphere for several minutes, and P (phosphorus) is added into the polycrystalline silicon film 24 to obtain a desired resistance value ρB, and at the same time, P is introduced into the silicon substrate 21. An N layer 26 is formed. That is,
In this case, P is added into the polycrystalline silicon III 24 and further penetrates and diffuses into the silicon substrate 21 from the periphery of the CVD IIF film 25.

Next, as shown in the same figure (c'), the CVD oxide film 25
After removing the polycrystalline silicon film 24, the polycrystalline silicon film 24 is patterned by PEP to form a gate electrode 27. Then, using this polycrystalline silicon film 24 as a mask, gate oxidation It! of the region where the source and drain are to be formed is performed. 23 was removed by etching, and then the entire surface was coated with A[)S (Arsenic [
)oped 5ilicon)11928 is deposited.

Thereafter, drive-in diffusion of As (arsenic) is performed in an oxidizing atmosphere to form a source and a source within the silicon substrate 21.
N+ layers 29 and 30 are formed to serve as drains.

Thereafter, as shown in FIG. 3(d'), after removing the ADS film 28, post-oxidation is performed to form an oxide film 31.

Furthermore, as shown in FIG. 3(e'), CV
A D oxide film 32 is formed. After that, an insulating film 32 is formed on the entire surface, and then a contact hole 33 is formed in this insulating film 32 and oxide film 31, and an aluminum wiring layer 34 is formed.

In the above process, when introducing P into the polycrystalline silicon film 24 as shown in FIG.
- The resistance ρS of the polycrystalline silicon wiring in the contact portion can be lowered to a required value, and the lateral Xj of the N layer 26 in the direct contact portion can be suppressed.

In the above embodiment, the source and drain N'' layers 29
．． As a way to form 30, ADSI! Although the impurity is diffused from 2B, other methods such as ion implantation of AS or the like may be used. In this case, the elongation of the source and drain diffusion depth xJ and lateral
It becomes easy to increase the density of SI.

Further, the control layer is not limited to the CVD oxide film 25 described above, but it is also possible to use an oxide film obtained by oxidizing only the portion of the polycrystalline silicon film 24 corresponding to the direct contact formation region. Furthermore, the control layer does not have to act as a complete stopper for impurities like an oxide film,
Any material that can control the amount of diffusion may be used.

Further, in the above embodiment, after forming the N layer 26, the CV
Although the D oxide film 25 was removed, in order to shorten the manufacturing process, the process of removing this control layer may be omitted and the control layer may be left without any significant effect on the device characteristics.

Further, in the above embodiments, the present invention has been described with respect to the manufacturing process of an 81-gate N-channel MO8 type transistor, but the present invention can also be applied to the manufacturing process of a P-channel MO8 type transistor or a C (β-omp1ementary)-MoS type transistor. Of course, it can also be applied to Furthermore, although the polycrystalline silicon film 24 is used as the electrode material in the explanation, other materials such as molybdenum polycide may be used, as long as impurities are added to lower the resistance value.

[Effects of the Invention] As described above, according to the present invention, it is possible to suppress the elongation of the diffusion layer in the direct contact part, so that it is possible to prevent the spread of the diffusion layer to the channel part, and to prevent deterioration of device characteristics. , high integration can also be achieved.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing the manufacturing process of a conventional MO8 type semiconductor device, and FIG. 2 is a sectional view showing the manufacturing process of an MO8 type semiconductor device according to an embodiment of the present invention. 21... Silicon substrate, 22... Field oxide film, 23... Gate oxide film, 24... Polycrystalline silicon film, 25... CVD oxide film (control layer), 26... N
Layer, 27... Gate electrode, 29.30... N4 layer. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] a step of forming a thin oxide film on a semiconductor substrate of a first conductivity type; a step of depositing an electrode material on the semiconductor substrate to form a film after selectively removing the oxide film; and a step of forming a film on the semiconductor substrate; forming a control layer for impurities on a portion of the film of the electrode material corresponding to the removed portion of the oxide film, and forming a second control layer on the film of the electrode material.
A method for manufacturing a semiconductor device, comprising the step of adding an impurity of a conductivity type and simultaneously introducing an impurity into the semiconductor substrate in contact with the semiconductor substrate to form an impurity layer of a second conductivity type.