JPH03125479A - Manufacture of semiconductor integration circuit with non-volatile memory element - Google Patents

Abstract

PURPOSE:To shorten a process and improve yield by adopting silicate glass available through oxidation of polycrystal silicon which contains high density impurities for a diffusion source required for formation of a high density impurity region in a non- volatile storage element. CONSTITUTION:Side wall spacers 58 and 59 are used as a mask so that n-type high density impurity layers 60 and 61 may be formed by ion plantation. Heat treatment is carried out under a nitrogen atmosphere to activate the impurities contained in low density impurity layers 56 and 57, and first high impurity layers 60 and 61 and diffuse n-type impurities contained in silicate glass over the surface of a silicone substrate 41, thereby forming a second n-type high density impurity layer 62. The first high density impurity layer 61 and the second high density impurity layer 62 are placed into contact with each other, and act electrically as the same impurity layers. Almost no type impurities is contained in the gate electrode 50 of a MOS transistor at the point of time when a mask oxide film 53 is formed or only a trace of impurities is contained therein. Therefore, this construction prevents impurities from being defused on the surface of the silicon substrate 41 under the gate electrode from the mask oxide film.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention provides a floating gate type nonvolatile memory element and a MOS transistor for controlling the nonvolatile memory element formed on a common silicon semiconductor substrate. It relates to a method for manufacturing semiconductor integrated circuits, and particularly relates to a method for manufacturing semiconductor integrated circuits (MOS) and LDD (lightly d
The present invention relates to a method of manufacturing a semiconductor integrated circuit having an open drain (open drain) structure.

(Prior Art) Generally, when integrating a floating gate type non-volatile memory element and a MOS transistor that controls this non-volatile memory element, along with the demand for miniaturization of the element, the control MOS transistors usually have an LDD structure to suppress short channel effects. On the other hand, in a floating gate type nonvolatile memory element, it is preferable to use a single drain structure due to the second problem of write characteristics.

A conventional manufacturing method of a semiconductor integrated circuit in which a single drain structure is adopted for a floating gate type nonvolatile memory element and an LDD structure is adopted for a control MOS transistor will be described with reference to FIG.

First, as shown in FIG. 2A, a p-type silicon substrate 11 is
A first element formation region 13 in which a field oxide film 12 is formed on the surface to form a MOS transistor having an LDD structure, and a second element formation region 14 in which a floating gate type nonvolatile memory element is to be formed. Separate into two parts.

Next, gate insulating films 15 and 16 are formed on the surfaces of the first and second element formation regions 13 and 14, respectively,
Further, a gate electrode 17 made of a polycrystalline silicon film is selectively formed on the gate insulating film 15 in the first element forming region, and a floating gate is later formed on the gate insulating film 16 in the second element forming region 14. A first polycrystalline silicon film 18 is formed.

Next, as shown in FIG. 2B, the second element formation region 14
A second polycrystalline silicon film 20, which will later constitute a control gate, is formed between the interlayer insulating film 19 and the first polycrystalline silicon film 18 formed in the step. Furthermore, the entire surface of the first element formation region 13 and the second element formation region 14
A photoresist film 21 is formed on a portion of the wafer.

Next, as shown in FIG. 2C, this photoresist film 21
Using as a mask, the second polycrystalline silicon film 20, interlayer insulating film 19, and first polycrystalline silicon film 18 are sequentially etched to form a floating gate 18a and a control gate 20a in a self-aligned manner. Further, after removing the photoresist film 21, oxide films 22 and 23 are formed on the surfaces of the gate electrode 17 of the MOS transistor and the floating gate 18a and control gate 20a of the nonvolatile memory element, respectively. moreover,
Using these oxide films 22 and 23 as masks, n-type impurities are implanted into the surface of silicon substrate 11 to form low concentration impurity layers 24 and 25.

Next, as shown in the second diagram, the first element formation region 13
After forming a photoresist film 26 on the surface of
5 to form source/drain regions of the nonvolatile memory element.

Furthermore, as shown in FIG. 2E, after the photoresist film 26 is removed, a side wall spacer 28 made of silicon oxide is placed on the side surface of the oxide film 22 covering the gate electrode 17.
form. In this step, sidewall spacers 29 are also formed on the side surfaces of the oxide film 23 covering the gate electrode of the nonvolatile memory element, but these sidewall spacers are not essentially necessary. Next, using the sidewall spacers 28 as a mask, n-type impurities are implanted to form a highly concentrated impurity layer 30. This impurity layer 30 is continuous with the previously formed low concentration impurity layer 24 to form the source/drain regions of the MOS transistor.

Finally, as shown in FIG. 2F, after forming an interlayer insulating film 31 on the entire surface of the first and second element forming regions 13 and 14, a contact window is opened and a metal wiring 32 is formed. In this way, a semiconductor integrated circuit is obtained in which a MOS transistor having an LDD structure and a floating gate type nonvolatile memory element having a single drain structure are formed on a common silicon substrate 11.

(Problems to be Solved by the Invention) In the conventional manufacturing method described above, MO of LDD structure
S) The high concentration impurity layer 30 of Ranjisk and the high concentration impurity layer 27 of the transistor of the floating gate type non-volatile memory element with a single drain structure are separated from each other.
Since it needs to be formed by a lithography process, the manufacturing process becomes complicated and time consuming, resulting in high manufacturing costs and poor yields. In an attempt to solve these drawbacks, the high concentration impurity layer 3 of the MOS transistor
When forming the sidewall spacer 28 that acts as a mask for forming 0, it is sufficient to selectively remove the sidewall spacer 29 of the oxide film 23 on the nonvolatile memory element side. However, the manufacturing process becomes complicated and manufacturing costs cannot be reduced.

An object of the present invention is to solve the above-mentioned problems and to create a semiconductor integrated circuit in which a MOS transistor having an LDD structure and a floating gate type non-volatile memory element having a single drain structure are integrated in a simple and time-saving process. The purpose of this study is to provide a method that can produce .

(Means for Solving the Problems) The present invention manufactures a semiconductor integrated circuit having a floating gate type non-volatile memory element having a single drain structure and a MOS transistor having an LDD structure for controlling this non-volatile memory element. A first element formation region for forming the MOS transistor by selectively forming a field insulating film on a silicon substrate of a first conductivity type, and a second element for forming a nonvolatile memory element. forming a first gate insulating film on the surface of the second element forming region; and forming a first gate insulating film on the first gate insulating film formed on the second element forming region. a step of selectively forming a polycrystalline silicon film of the first polycrystalline silicon film; a step of introducing a large amount of a second conductivity type impurity into the first polycrystalline silicon film; forming an interlayer insulating film on the first polycrystalline silicon film; forming a gate insulating film in the first element forming region; A step of forming a second polycrystalline silicon film on the interlayer insulating film formed in the formation region, and etching the second polycrystalline silicon film formed in the first element formation region to form the gate electrode of the MOS transistor. forming a nonvolatile memory element having a control gate and a floating gate by etching the first polycrystalline silicon film, the interlayer insulating film, and the second polycrystalline silicon film formed in the second element formation region in a self-aligned manner; The MO
a step of coating the gate electrode of the S transistor and the gate electrode structure of the nonvolatile memory element with a silicon oxide film, and coating the side surface of the floating gate with silicate glass containing a large amount of impurities of a second conductivity type; and forming a low concentration impurity layer by introducing impurities of a second conductivity type into the second element formation region using the respective gate electrodes as masks; a step of forming a sidewall spacer on the side surface of the gate electrode structure in the first element formation region; and introducing an impurity of a second conductivity type using the gate electrode having the sidewall spacer as a mask; MO continuously with low concentration impurity layer
forming a first high concentration impurity layer constituting the source/drain regions of the S transistor, and also forming a first high concentration impurity layer so as to cover part of the low concentration impurity layer in the second element formation region; A heat treatment is performed to diffuse the second conductivity type impurity contained in the silicate glass into the silicon substrate to cover the remainder of the low concentration impurity layer and form a nonvolatile memory continuously with the first high concentration impurity layer. After forming a second high concentration impurity layer constituting the source/drain region of the device and forming an interlayer insulating film on the entire surface of the first and second device formation regions, forming a contact window, and further The method is characterized by comprising a step of applying metal wiring.

(Function) According to the manufacturing method of the present invention, the side surface of the floating gate electrode is coated with silicate glass containing a high concentration of impurities, and the source/drain high concentration layer of the transistor constituting the nonvolatile memory element is formed. By acting as an impurity diffusion source for forming an impurity, high-concentration ion implantation into the source and drain of an LDD structure MOS transistor and high-concentration ion implantation into the source and drain of a floating gate nonvolatile memory element transistor can be performed simultaneously. can. Therefore, the manufacturing process is simplified and
The time can also be shortened, the manufacturing cost can be reduced, and the yield can also be improved.

(Embodiment) FIG. 1 is a cross-sectional view showing the structure of a semiconductor device in successive steps of an embodiment of the manufacturing method of the present invention.

First, as shown in FIG. 1, a p-type silicon substrate 41 is
A thick field insulating film 42 is formed on M.
It is separated into a first element formation region 43 for forming an OS transistor and a second element formation region 44 for forming a nonvolatile memory element. Furthermore, a film thickness of 10 mm is applied to the surfaces of these first and second element forming regions 43 and 44.
First gate insulating films 45 and 46 of ~30 nm are formed, respectively. Furthermore, a first polycrystalline silicon film having a thickness of about 400 nm is uniformly formed by, for example, chemical vapor deposition (CVD). The first polycrystalline silicon film thus formed is subjected to heat treatment in, for example, a mixed atmosphere of phosphine (PH3) and oxygen to introduce a large amount of n-type impurity, that is, phosphorus, into the first polycrystalline silicon film. . Next, a photoresist is selectively formed and the first polycrystalline silicon film 47 is selectively etched using a known technique so as to leave the first polycrystalline silicon film 47 that will later constitute the floating gate. Form. Furthermore, using this first polycrystalline silicon film 47 as a mask, a first
The first gate insulating film 45 in the element forming region 43 is removed by etching.

Next, as shown in FIG.
By heat treatment in an oxidizing atmosphere at 00'C, the first
A second gate insulating film 49 with a thickness of 10 to 30 nm is formed on the surface of the element forming region 43, and an interlayer insulating film 48 is formed in the second element forming region 44. A second polycrystalline silicon film 70 with a thickness of about 400 nm is formed.

Furthermore, as shown in FIG. 1C, a photoresist is selectively formed and the polycrystalline silicon film 70 is selectively removed.
A gate electrode 50 is left in the element formation region 43, and a polycrystalline silicon film 51, which will later become a control gate, is left. Further, a photoresist 52 is formed on the entire surface of the first element formation region 43, and a photoresist 53 is selectively formed on the portion where the gate structure of the nonvolatile memory element is to be formed.

Next, as shown in the first diagram, the second polycrystalline silicon film 51, second gate insulating film 48, first polycrystalline silicon film 47, and first gate insulating film 46 are sequentially formed using the photoresist 53 as a mask. Etching is performed to form a floating gate 47a and a control gate 51a in a self-aligned manner.

Furthermore, in an oxidizing atmosphere, e.g. 900-1000°C
A heat treatment is performed to form oxide films 53 and 54 acting as masks on the surfaces of the gate electrode 50 of the MOS transistor and the gate electrode structures 47a and 51a of the nonvolatile memory element. At this time, silicate glass 55 containing a large amount of n-type impurities is formed on the side surface of the floating gate 47a containing a large amount of n-type impurities. As will be described later, this silicate glass 55 acts as an ion diffusion source when forming the source/drain regions of the nonvolatile memory element. Furthermore, gate electrodes 50 and 51a, 4 covered with oxide films 53 and 54
Using 7a as a mask, n-type impurity ions are implanted to form low concentration impurity layers 56 and 57. Of these low concentration impurity layers, the one 56 formed in the first element formation region 43 effectively acts as a low concentration impurity layer of the LDD structure MOS transistor, but the single drain layer 56 in the second element formation region 44 acts effectively as a low concentration impurity layer of the MOS transistor of the LDD structure. The area 57 formed in this area is unnecessary because it forms a type of non-volatile memory element.

Next, as shown in FIG. 1E, sidewall spacers 58 and 59 are formed on the sides of gate electrode 50 and gate electrode structures 47a and 51a, respectively. The method of forming the sidewall spacers 58 and 59 itself is well known as a manufacturing technology for LDD structure MOS transistors.
It can be formed by etching a 102 film. Using the thus formed sidewall spacers 58 and 59 as a mask, the η-type high concentration impurity layer 6
0 and 61 are formed by ion implantation. Further, heat treatment is performed at 900 to 1000°C in a nitrogen atmosphere to activate the impurities in the low concentration impurity layers 56, 57 and the first high concentration impurity layers 60, 61, and to activate the impurities contained in the silicate glass 55. The n-type impurity contained in the silicon substrate 41 is diffused into the surface of the silicon substrate 41 to form an n-type second high concentration impurity layer 62. At this time, the first high concentration impurity layer 61 and the second high concentration impurity layer 62 come into contact with each other and act as electrically the same impurity layer. On the other hand, since the gate electrode 50 of the MOS transistor contains almost no or only a small amount of n-type impurity at the time when the mask oxide film 53 is formed, the gate electrode 50
Impurities do not diffuse from the mask oxide film 53 to the surface of the silicon substrate 41 below.

Next, as shown in FIG. 1F, an interlayer insulating film 63 doped with phosphorus, for example, is formed by CVD. Further, a contact window is opened in the interlayer insulating film 63 using a known technique, and a metal wiring 64 made of aluminum doped with silicon, for example, is provided. In this way, a MOS transistor having an LDD structure can be formed in the first element forming region 43, and a floating gate nonvolatile memory element having a single drain structure can be formed in the second element forming region 44. In the above embodiment, the n-type impurity is introduced into the first polycrystalline silicon film 47 at a phosphine flow rate of 60 m1/m i
n.

Oxygen flow rate 9Qmjl! /min, nitrogen flow rate 5.9fl/
The test was carried out at a temperature of 900°C in a mixed gas of min.

The present invention is not limited to the embodiments described above, and numerous changes and modifications are possible. For example, in the above-described embodiments, a case has been described in which an n-channel type transistor is formed using an n-type silicon substrate, but an n-channel type transistor using an n-type silicon substrate can also be manufactured.

In this case, the first polycrystalline silicon film is doped with p-type impurities,
For example, boron can be introduced. Furthermore, the control MOS transistors can be of complementary type.

(Effects of the Invention) According to the manufacturing method of the present invention described above, silicate glass obtained by oxidizing polycrystalline silicon containing a high concentration of impurities is diffused to form a high concentration impurity region of a nonvolatile memory element. By using the high concentration impurity layer as a source, the ion implantation process of the high concentration impurity layer into the floating gate type nonvolatile memory element transistor and the ion implantation process of the high concentration impurity layer of the peripheral MOS transistor that controls the nonvolatile memory element can be performed simultaneously. The high-concentration impurity layer formation process, which conventionally required two IJ photolithographic processes, can now be completed in one photolithographic process, which shortens the process and reduces manufacturing costs. Furthermore, it is also possible to improve the yield.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the structure of a semiconductor device in successive steps in an embodiment of the manufacturing method of the present invention, and FIG. 2 is a sectional view showing the structure of a semiconductor device in successive steps of a conventional manufacturing method. . 41...Silicon substrate 42...Field insulating film 43...First element formation region 44...Second element formation region 45.46...First gate insulating film 47...First polycrystal Silicon film 47a...Floating gate 48...Interlayer insulating film 49...Second gate insulating film 50...Gate electrode 51...Second polycrystalline silicon film 51a...Control gate 52... Photoresist 53.54...Mask oxide film 55...Silicate glass 56.57...Low concentration impurity layer 58.59...Side wall spacer 60.61...
... High concentration impurity layer 62 ... High concentration impurity layer 63 ... Interlayer insulating film 64 ... Metal wiring

Claims (1)

[Claims] 1. In manufacturing a semiconductor integrated circuit having a floating gate non-volatile memory element having a single drain structure and a MOS transistor having an LDD structure for controlling this non-volatile memory element, a first conductive A field insulating film is selectively formed on the silicon substrate of the mold to separate it into a first element formation region for forming the MOS transistor and a second element formation region for forming a nonvolatile memory element. forming a first gate insulating film on the surface of the second element forming region; and forming a first polycrystalline silicon film on the first gate insulating film formed on the second element forming region. a step of selectively forming a film; a step of introducing a large amount of impurities of a second conductivity type into the first polycrystalline silicon film; a step of forming an interlayer insulating film; a step of forming a gate insulating film in the first element forming region; an interlayer insulating film formed on the gate insulating film formed in the first element forming region and on the second element forming region. forming a second polycrystalline silicon film thereon; etching the second polycrystalline silicon film formed in the first element formation region to form a gate electrode of a MOS transistor; Step of etching the first polycrystalline silicon film, interlayer insulating film, and second polycrystalline silicon film formed in the element formation region in a self-aligned manner to form a gate electrode structure of a nonvolatile memory element having a control gate and a floating gate. By performing an oxidation treatment, the gate electrode of the MOS transistor and the gate electrode structure of the nonvolatile memory element are covered with a silicon oxide film, and the side surface of the floating gate is coated with silicate glass containing a large amount of impurities of the second conductivity type. a step of introducing impurities of a second conductivity type into the first and second element formation regions using the respective gate electrodes as masks to form a low concentration impurity layer; forming sidewall spacers on the side surfaces of the gate electrode in the element formation region and the gate electrode structure in the second element formation region; introducing impurities of a second conductivity type using the gate electrode having the sidewall spacers as a mask; In the first element formation region, a high concentration impurity layer constituting the source/drain region of the MOS transistor is formed continuously with the low concentration impurity layer, and in the second element formation region, a part of the low concentration impurity layer is formed. forming a first high concentration impurity layer so as to cover the silicate glass; and performing heat treatment to diffuse the second conductivity type impurity contained in the silicate glass into the silicon substrate to remove the remainder of the low concentration impurity layer. while covering the first
forming a second high concentration impurity layer contiguous with the high concentration impurity layer constituting the source/drain region of the nonvolatile memory element; and forming an interlayer insulating film on the entire surface of the first and second element forming regions. 1. A method of manufacturing a semiconductor integrated circuit having a non-volatile memory element, the method comprising the steps of: forming a contact window, and further applying metal wiring.