JPH05304169A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH05304169A JPH05304169A JP13451292A JP13451292A JPH05304169A JP H05304169 A JPH05304169 A JP H05304169A JP 13451292 A JP13451292 A JP 13451292A JP 13451292 A JP13451292 A JP 13451292A JP H05304169 A JPH05304169 A JP H05304169A
- Authority
- JP
- Japan
- Prior art keywords
- opening
- semiconductor substrate
- ion implantation
- angle
- mask material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000000463 material Substances 0.000 claims abstract description 12
- 238000005468 ion implantation Methods 0.000 claims description 30
- 238000009792 diffusion process Methods 0.000 abstract description 22
- 238000000034 method Methods 0.000 abstract description 19
- 150000002500 ions Chemical class 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 32
- 229920002120 photoresistant polymer Polymers 0.000 description 14
- 239000012535 impurity Substances 0.000 description 12
- 238000002513 implantation Methods 0.000 description 9
- 238000009826 distribution Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
- H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- High Energy & Nuclear Physics (AREA)
- Manufacturing & Machinery (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Non-Volatile Memory (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に異なる不純物濃度のイオン注入層を有する半
導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having ion-implanted layers having different impurity concentrations.
【０００２】[0002]
【従来の技術】従来、ＭＯＳ型半導体装置の製造工程に
於いて、半導体表面の２箇所に各々別の濃度の不純物を
イオン注入法により導入しようとすると、２回のマスク
工程が必要となる。例えば、図３にＭＯＳ型半導体記憶
装置の製造方法を例を示す。先ず、図３（ａ）のよう
に、半導体基板１上に第１絶縁膜２として、熱酸化法に
より 400Å程度の酸化膜を形成した後、フォトレジスト
３Ａを形成して所定の領域を開口し、このフォトレジス
ト３Ａをマスクとして第１イオン注入を行い、第１注入
層４を形成する。2. Description of the Related Art Conventionally, in the process of manufacturing a MOS type semiconductor device, if an impurity of different concentration is to be introduced into two points on the semiconductor surface by an ion implantation method, two masking steps are required. For example, FIG. 3 shows an example of a method for manufacturing a MOS semiconductor memory device. First, as shown in FIG. 3A, an oxide film of about 400 Å is formed as a first insulating film 2 on the semiconductor substrate 1 by a thermal oxidation method, and then a photoresist 3A is formed to open a predetermined region. First ion implantation is performed using the photoresist 3A as a mask to form a first implantation layer 4.
【０００３】次いで、図３（ｂ）のように、前記フォト
レジスト３Ａを除去した後に改めてフォトレジスト３Ｂ
を形成して所定の領域を開口し、フォトレジスト３Ｂを
マスクとして第２イオン注入を行い、第２注入層５を形
成する。そして、フォトレジスト３Ｂを除去した後に、
高温の例えば1200℃の熱処理を行い、図３（ｃ）のよう
に、第１ウェル拡散層６及び第２ウェル拡散層７を形成
する。しかる後、図３（ｄ）のように、素子分離領域８
を形成した後、第２ウェル拡散層７には第１ゲート絶縁
膜１７、浮遊ゲート１２、第２ゲート絶縁膜１８、制御
ゲート１３、拡散層１０を形成してＭＯＳ型記憶素子を
形成し、第１ウェル拡散層６には第３ゲート絶縁膜１
１、ゲート９、拡散層１０を形成してＭＯＳトランジス
タを構成し、かつ全面に層間絶縁膜１４、電極配線１
５、カバー絶縁膜１６を順次形成し、半導体記憶装置を
形成する。Next, as shown in FIG. 3 (b), after removing the photoresist 3A, the photoresist 3B is newly formed.
Is formed, a predetermined region is opened, and second ion implantation is performed using the photoresist 3B as a mask to form a second implantation layer 5. Then, after removing the photoresist 3B,
Heat treatment at a high temperature of, for example, 1200 ° C. is performed to form the first well diffusion layer 6 and the second well diffusion layer 7 as shown in FIG. Then, as shown in FIG. 3D, the element isolation region 8
Then, a first gate insulating film 17, a floating gate 12, a second gate insulating film 18, a control gate 13 and a diffusion layer 10 are formed on the second well diffusion layer 7 to form a MOS type memory element. The third gate insulating film 1 is formed on the first well diffusion layer 6.
1, a gate 9 and a diffusion layer 10 are formed to form a MOS transistor, and an interlayer insulating film 14 and electrode wiring 1 are formed on the entire surface.
5, the cover insulating film 16 is sequentially formed to form a semiconductor memory device.
【０００４】[0004]
【発明が解決しようとする課題】この従来の製造方法に
於けるイオン注入工程では、２種類の濃度の異なる拡散
層を形成する場合には、２度のフォトリソグラフィ（写
真蝕刻）工程が必要となり、半導体装置の製造期間が長
期化すると言う問題があった。又、従来では、ＭＯＳト
ランジスタのソースとドレインの不純物分布を非対称に
する為に、ゲート電極形成後に、ある注入角度，注入量
で第１イオン注入を行い、また別の注入角度，注入量で
第２イオン注入を行ってＭＯＳトランジスタのソース，
ドレインとする方法が提案されている（例えば、特開昭
63−184365）。In the ion implantation step in the conventional manufacturing method, two photolithography steps are required when forming two kinds of diffusion layers having different concentrations. However, there is a problem that the manufacturing period of the semiconductor device is extended. Further, conventionally, in order to make the impurity distribution of the source and the drain of the MOS transistor asymmetric, the first ion implantation is performed at a certain implantation angle and a certain implantation amount after the gate electrode is formed, and at the other implantation angle and another implantation amount. 2 Ion implantation is performed to source the MOS transistor,
A method of using a drain has been proposed (see, for example, Japanese Patent Laid-Open No.
63-184365).
【０００５】しかしながら、この方法では、ソースとド
レイン共に２度のイオン注入が行われる為、ソースとド
レインの不純物分布を変える事は出来るが不純物濃度を
変える事は出来ない。又、所定の領域のソース、所定の
領域のドレインの不純物濃度を変えようとすると当然の
事ながら、２度のフォトリソグラフィ工程が必要とな
り、半導体装置の製造期間が長期化してしまう。本発明
の目的は、２種類の異なる拡散層を形成する際のマスク
工程を削減した半導体装置の製造方法を提供することに
ある。However, according to this method, since the ion implantation is performed twice for both the source and the drain, the impurity distribution of the source and the drain can be changed, but the impurity concentration cannot be changed. In addition, if the impurity concentration of the source in a predetermined region and the drain concentration in a predetermined region are changed, two photolithography steps are naturally required, and the manufacturing period of the semiconductor device is lengthened. An object of the present invention is to provide a method for manufacturing a semiconductor device in which a mask process for forming two different diffusion layers is reduced.
【０００６】[0006]
【課題を解決するための手段】本発明は、半導体基板上
に所要厚さのマスク材を形成する工程と、このマスク材
には第１イオン注入層に相当する領域はマスク材の厚さ
に対して開口寸法の小さな複数の第１の開口を形成する
一方、第２イオン注入層に相当する領域は略全領域にわ
たって第２の開口を形成する工程と、第１の開口に対し
て半導体基板が露呈されない角度でイオン注入を行う工
程と、第１の開口に対して半導体基板が露呈される角度
でイオン注入を行う工程とを含んでいる。例えば、マス
ク材の厚さをＨ，半導体基板の法線方向に対するイオン
注入角度をθ１（θ１≠０°）とした時に、第２の開口
は短辺の長さをＡ１として（Ｈ／Ａ１）＜ tan（90°−
θ１）の関係に設定し、第１の開口は開口部の対角線の
長さをＢ３として、（Ｈ／Ｂ３）＞ tan（90°−θ１）
の関係となるように設定し、角度θ１で前記半導体基板
を法線方向を軸に回転させながらイオン注入を行い、第
１の開口の短辺の長さをＢ１として（Ｈ／Ｂ１）＜ tan
（90°−θ２）となる角度θ２で、前記半導体基板を法
線方向を軸に回転させながらイオン注入を行う。According to the present invention, a step of forming a mask material having a required thickness on a semiconductor substrate, and a region corresponding to the first ion implantation layer in the mask material has a thickness of the mask material. On the other hand, a step of forming a plurality of first openings having a small opening size while forming the second openings over substantially the entire area corresponding to the second ion implantation layer, and a semiconductor substrate for the first openings. And the step of performing ion implantation at an angle at which the semiconductor substrate is exposed to the first opening. For example, when the thickness of the mask material is H and the ion implantation angle with respect to the normal direction of the semiconductor substrate is θ1 (θ1 ≠ 0 °), the second opening has a short side length of A1 (H / A1). <Tan (90 °-
θ1), and the first opening is (H / B3)> tan (90 ° -θ1), where B3 is the length of the diagonal line of the opening.
And ion implantation is performed while rotating the semiconductor substrate about the normal direction as an axis at an angle θ1 and the length of the short side of the first opening is B1 (H / B1) <tan
Ion implantation is performed while rotating the semiconductor substrate about the normal direction at an angle θ2 of (90 ° −θ2).
【０００７】[0007]
【実施例】次に、本発明について図面を参照して説明す
る。図１は本発明の一実施例を製造工程順に示す図であ
り、特に同図（ａ），（ｃ），（ｄ），（ｅ）は、同図
（ｂ）のＡ−Ａ線に沿う断面図である。先ず、図１
（ａ）のように、半導体基板１上に第１絶縁膜２として
例えば熱酸化法により酸化膜を 400Å程度形成し、フォ
トレジスト３を膜厚Ｈの厚さで形成し、図１（ｂ）のよ
うに、開口部の短辺の長さがＡ１の比較的に大きな開口
１９と、開口部の短辺の長さがＢ１，対角線の長さがＢ
３の比較的に小さな開口２０を形成する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a view showing an embodiment of the present invention in the order of manufacturing steps. Particularly, FIGS. 1 (a), (c), (d) and (e) are along the line AA in FIG. 1 (b). FIG. First, Fig. 1
As shown in FIG. 1A, an oxide film is formed on the semiconductor substrate 1 as the first insulating film 2 by, for example, a thermal oxidation method to a thickness of about 400 Å, and a photoresist 3 is formed to a film thickness H. As described above, the opening 19 has a relatively large short side length A1, and the opening side has a short side length B1 and a diagonal length B.
3 relatively small openings 20 are formed.
【０００８】そして、半導体基板１を法線方向を軸に回
転させながら角度θ１（θ１≠０°）で第１イオン注入
を行う。ここで、Ａ１＞Ｈ／ tan（90°−θ１），Ｂ３
＜Ｈ／ tan（90°−θ１）と設定する事により、開口２
０では半導体基板１がイオン注入方向に露呈されず、開
口１９では露呈されるため、開口１９にのみ第１注入層
４を形成する事ができる。例えば、Ｈ＝ 1.5μｍ，θ１
＝45°とするとＡ１＞1.5μｍ，Ｂ３＜ 1.5μｍとな
る。Then, the first ion implantation is performed at an angle θ1 (θ1 ≠ 0 °) while rotating the semiconductor substrate 1 about the axis of the normal line. Where A1> H / tan (90 ° -θ1), B3
By setting <H / tan (90 ° -θ1), opening 2
At 0, the semiconductor substrate 1 is not exposed in the ion implantation direction, but at the opening 19, the first implantation layer 4 can be formed only in the opening 19. For example, H = 1.5 μm, θ1
= 45 °, A1> 1.5 μm and B3 <1.5 μm.
【０００９】続いて、フォトレジスト３を残したまま
で、図１（ｃ）のように、第２イオン注入を tan（90°
−θ２）＞Ｈ／Ｂ１となる角度θ２で半導体基板１を法
線方向を軸に回転させながら行うことで、開口１９，２
０の双方に対してイオン注入ができ、第２注入層５を形
成する。例えば、Ｂ１＝ 1.0μｍとするとθ２＜33.6°
となる。この後、高温の熱処理を例えば、1200℃程度で
行い、図１（ｄ）のように、不純物濃度の異なる２つの
第１ウェル拡散層６及び第２ウェル拡散層７を形成す
る。Then, as shown in FIG. 1C, the second ion implantation is performed at tan (90 °) with the photoresist 3 left.
-[Theta] 2)> H / B1 is performed while rotating the semiconductor substrate 1 around the normal direction as an angle [theta] 2.
Ions can be implanted into both 0 and 0 to form the second implantation layer 5. For example, if B1 = 1.0 μm, θ2 <33.6 °
Becomes After that, high temperature heat treatment is performed at, for example, about 1200 ° C. to form two first well diffusion layers 6 and 7 having different impurity concentrations as shown in FIG.
【００１０】その後、図１（ｅ）のように、素子分離絶
縁膜８を形成した後、第２ウェル拡散層７に、第１ゲー
ト絶縁膜１７、浮遊ゲート１２、第２ゲート絶縁膜１
８、制御ゲート１３、拡散層１０を形成してＭＯＳ型記
憶素子を形成する。又、第１ウェル拡散層６に第３ゲー
ト絶縁膜１１、ゲート９、拡散層１０を形成してＭＯＳ
トランジスタを形成する。更に、全面に層間絶縁膜１
４、電極配線１５、カバー絶縁膜１６を順次形成し、半
導体装置を形成する。以上の様に、本発明では、マスク
材としてのフォトレジストに、大きさの異なる２種類の
開口領域を形成し、角度の異なる２回のイオン注入を行
う事により、１回のフォトリソグラフィ工程で不純物濃
度の異なる２種類の拡散層を形成出来る。Thereafter, as shown in FIG. 1E, after forming an element isolation insulating film 8, a first gate insulating film 17, a floating gate 12 and a second gate insulating film 1 are formed on the second well diffusion layer 7.
8, the control gate 13 and the diffusion layer 10 are formed to form a MOS type memory element. In addition, the third gate insulating film 11, the gate 9 and the diffusion layer 10 are formed on the first well diffusion layer 6 to form a MOS.
Form a transistor. Further, the interlayer insulating film 1 is formed on the entire surface.
4, the electrode wiring 15 and the cover insulating film 16 are sequentially formed to form a semiconductor device. As described above, according to the present invention, two types of opening regions having different sizes are formed in the photoresist as the mask material, and the ion implantation is performed twice at different angles. Two types of diffusion layers having different impurity concentrations can be formed.
【００１１】本発明の他の実施例を図２に示す。同図
（ａ），（ｃ），（ｄ），（ｅ）は同図（ｂ）のＢ−Ｂ
線に沿う断面図を示している。先ず、図２（ａ）のよう
に、例えばＰ型不純物を含有した半導体基板１上に、第
１ゲート絶縁膜１７として熱酸化法により膜厚50Å〜 2
00Å程度の熱酸化膜を形成し、その上に浮遊ゲート１
２、第２ゲート絶縁膜１８、制御ゲート１３を順次形成
する。更に、この上にフォトレジスト３を膜厚Ｈの厚さ
で形成した上で、図２（ｂ）のように、開口部の短辺の
長さがＡ１の比較的に大きな開口領域１９と、開口部の
短辺の長さがＢ１，対角線の長さがＢ３の比較的に小さ
な開口領域２０を形成する。Another embodiment of the present invention is shown in FIG. (A), (c), (d), and (e) of the same figure are BB of the same figure (b).
A cross-sectional view along a line is shown. First, as shown in FIG. 2A, for example, on the semiconductor substrate 1 containing P-type impurities, a film thickness of 50Å to 2 is formed as the first gate insulating film 17 by a thermal oxidation method.
A thermal oxide film of about 00Å is formed, and a floating gate 1 is formed on it.
2, the second gate insulating film 18 and the control gate 13 are sequentially formed. Further, a photoresist 3 having a thickness of H is formed thereon, and then, as shown in FIG. 2B, a relatively large opening region 19 in which the length of the short side of the opening is A1 and A relatively small opening region 20 having a short side length B1 and a diagonal length B3 is formed.
【００１２】そして、第１イオン注入として例えば、基
板と同一導電型の不純物ボロンを、半導体基板１を法線
方向を軸に回転させながら角度θ１（θ１≠０°）で注
入する。ここで、Ａ１＞Ｈ／ tan（90°−θ１），Ｂ３
＜Ｈ／ tan（90°−θ１）と認定する事により開口領域
１９にのみ第１注入層４を形成する事が出来る。例え
ば、Ｈ＝ 1.5μｍ，θ１＝45°とするとＡ１＞ 1.5μ
ｍ，Ｂ３＜ 1.5μｍを満たせば実現出来ることになる。Then, as the first ion implantation, for example, impurity boron having the same conductivity type as the substrate is implanted at an angle θ1 (θ1 ≠ 0 °) while rotating the semiconductor substrate 1 around the axis of the normal line. Where A1> H / tan (90 ° -θ1), B3
By recognizing <H / tan (90 ° −θ1), the first injection layer 4 can be formed only in the opening region 19. For example, if H = 1.5 μm and θ1 = 45 °, A1> 1.5 μ
It can be realized by satisfying m, B3 <1.5 μm.
【００１３】続いて、図２（ｃ）のように、フォトレジ
スト３を残したままで、第２イオン注入として、半導体
基板１と反対導電型の不純物ヒ素を、 tan（90°−θ
２）＞Ｈ／Ｂ１となる角度θ２で半導体基板１を法線方
向を軸として回転させながら注入し、第２注入層５を形
成する。次いで、熱処理を例えば 800℃〜 900℃で行
い、図２（ｄ）のように、ドレイン拡散層５Ａ及びソー
ス拡散層５Ｂを形成する。この後、図２（ｅ）のよう
に、層間絶縁膜１４、電極配線１５、カバー絶縁膜１６
を順次形成しＭＯＳ型半導体記憶素子を形成する。この
実施例においても、マスク材としてのフォトレジスト
に、大きさの異なる２種類の開口領域を形成し、角度の
異なる２回のイオン注入を行う事により、１回のフォト
リソグラフィ工程だけで、所定の領域のドレイン拡散層
とソース拡散層の不純物分布を異なる状態に設定出来
る。Then, as shown in FIG. 2C, with the photoresist 3 left as it is, impurity arsenic having a conductivity type opposite to that of the semiconductor substrate 1 is changed to tan (90 ° -θ) as a second ion implantation.
2) Implant while rotating the semiconductor substrate 1 at an angle θ2 such that> H / B1 with the normal direction as an axis, to form the second implantation layer 5. Next, heat treatment is performed at, for example, 800 ° C. to 900 ° C. to form the drain diffusion layer 5A and the source diffusion layer 5B as shown in FIG. After that, as shown in FIG. 2E, the interlayer insulating film 14, the electrode wiring 15, and the cover insulating film 16 are formed.
Are sequentially formed to form a MOS type semiconductor memory element. Also in this embodiment, two types of opening regions having different sizes are formed in the photoresist as the mask material, and ion implantation is performed twice at different angles, so that a predetermined photolithography process is required. The impurity distributions of the drain diffusion layer and the source diffusion layer in the region can be set to different states.
【００１４】[0014]
【発明の効果】以上説明した様に本発明は、イオン注入
のマスクとなるフォトレジストに大きさの異なる２つの
開口領域を設け、小さい開口においては半導体基板が露
呈されない角度でのイオン注入を行い、その後小さい開
口においても半導体基板が露呈される角度でのイオン注
入を行うことにより、１度のフォトリソグラフィ工程に
より、濃度分布の異なる２種類の拡散層を、所定の領域
に形成出来るという効果を有する。As described above, according to the present invention, the photoresist serving as the ion implantation mask is provided with two opening regions having different sizes, and the ion implantation is performed at an angle such that the semiconductor substrate is not exposed in the small opening. Then, by performing ion implantation at an angle at which the semiconductor substrate is exposed even in a small opening, two types of diffusion layers having different concentration distributions can be formed in a predetermined region by one photolithography process. Have.
【図１】本発明の一実施例を製造工程順に示す図であ
る。FIG. 1 is a diagram showing an embodiment of the present invention in the order of manufacturing steps.
【図２】本発明の他の実施例を製造工程順に示す図であ
る。FIG. 2 is a diagram showing another embodiment of the present invention in the order of manufacturing steps.
【図３】従来の製造方法を製造工程順に示す図である。FIG. 3 is a diagram showing a conventional manufacturing method in the order of manufacturing steps.
１ 半導体基板 ３ フォトレジスト ４ 第１注入層 ５ 第２注入層 ６ 第１ウェル拡散層 ７ 第２ウェル拡散層 １９ 開口（大きな開口） ２０ 開口（小さな開口） 1 Semiconductor Substrate 3 Photoresist 4 First Injection Layer 5 Second Injection Layer 6 First Well Diffusion Layer 7 Second Well Diffusion Layer 19 Opening (Large Opening) 20 Opening (Small Opening)
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 29/788 29/792 8617−4Ｍ Ｈ０１Ｌ 21/265 Ｌ 29/78 ３７１ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI Technical indication location H01L 29/788 29/792 8617-4M H01L 21/265 L 29/78 371
Claims (2)
オン注入層と第２イオン注入層を形成するに際し、半導
体基板上に所要厚さのマスク材を形成する工程と、前記
マスク材には第１イオン注入層に相当する領域はマスク
材の厚さに対して開口寸法の小さな複数の第１の開口を
形成する一方、第２イオン注入層に相当する領域は略全
領域にわたって第２の開口を形成する工程と、第１の開
口に対して半導体基板が露呈されない角度でイオン注入
を行う工程と、第１の開口に対して半導体基板が露呈さ
れる角度でイオン注入を行う工程とを含むことを特徴と
する半導体装置の製造方法。1. A step of forming a mask material having a required thickness on a semiconductor substrate when forming a first ion implantation layer and a second ion implantation layer having different concentrations on a semiconductor substrate, The region corresponding to the first ion-implanted layer forms a plurality of first openings having a small opening size with respect to the thickness of the mask material, while the region corresponding to the second ion-implanted layer covers the second region over substantially the entire region. A step of forming an opening, a step of performing ion implantation at an angle at which the semiconductor substrate is not exposed to the first opening, and a step of performing ion implantation at an angle at which the semiconductor substrate is exposed to the first opening. A method of manufacturing a semiconductor device, comprising:
方向に対するイオン注入角度をθ１（θ１≠０°）とし
た時に、第２の開口は短辺の長さをＡ１として（Ｈ／Ａ
１）＜ tan（90°−θ１）の関係に設定し、第１の開口
は開口部の対角線の長さをＢ３として、（Ｈ／Ｂ３）＞
tan（90°−θ１）の関係となるように設定し、角度θ
１で前記半導体基板を法線方向を軸に回転させながらイ
オン注入を行い、第１の開口の短辺の長さをＢ１として
（Ｈ／Ｂ１）＜ tan（90°−θ２）となる角度θ２で、
前記半導体基板を法線方向を軸に回転させながらイオン
注入を行う請求項１の半導体装置の製造方法。2. When the thickness of the mask material is H and the ion implantation angle with respect to the direction normal to the semiconductor substrate is θ1 (θ1 ≠ 0 °), the second opening has a short side length of A1 (H / A
1) <tan (90 ° -θ1), and the first opening is (H / B3), where the diagonal length of the opening is B3.
Set so that the relationship of tan (90 ° -θ1) is satisfied and the angle θ
In step 1, ion implantation is performed while rotating the semiconductor substrate about the axis of the normal line, and the length of the short side of the first opening is B1 and the angle θ2 is (H / B1) <tan (90 ° −θ2). so,
2. The method of manufacturing a semiconductor device according to claim 1, wherein ion implantation is performed while rotating the semiconductor substrate about a normal line direction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13451292A JPH05304169A (en) | 1992-04-28 | 1992-04-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13451292A JPH05304169A (en) | 1992-04-28 | 1992-04-28 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05304169A true JPH05304169A (en) | 1993-11-16 |
Family
ID=15130062
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13451292A Pending JPH05304169A (en) | 1992-04-28 | 1992-04-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05304169A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997005649A1 (en) * | 1995-07-25 | 1997-02-13 | Siemens Aktiengesellschaft | Process for manufacturing a self-aligned contact and doped region |
| EP0696059A3 (en) * | 1994-08-03 | 2001-08-01 | Kabushiki Kaisha Toshiba | Semiconductor device having trenches and method of forming trenches |
| JP2004071664A (en) * | 2002-08-02 | 2004-03-04 | Sony Corp | Semiconductor device and its manufacturing method |
| DE102004009521A1 (en) * | 2004-02-27 | 2005-09-15 | Austriamicrosystems Ag | High-voltage PMOS transistor |
| US7315062B2 (en) | 2004-03-31 | 2008-01-01 | Eudyna Devices Inc. | Semiconductor device, mask for impurity implantation, and method of fabricating the semiconductor device |
| JP2011171603A (en) * | 2010-02-19 | 2011-09-01 | Oki Semiconductor Co Ltd | Method of manufacturing semiconductor element |
-
1992
- 1992-04-28 JP JP13451292A patent/JPH05304169A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0696059A3 (en) * | 1994-08-03 | 2001-08-01 | Kabushiki Kaisha Toshiba | Semiconductor device having trenches and method of forming trenches |
| EP1569265A2 (en) * | 1994-08-03 | 2005-08-31 | Kabushiki Kaisha Toshiba | Semiconductor device having trenches and method of forming trenches |
| EP1569265A3 (en) * | 1994-08-03 | 2008-06-04 | Kabushiki Kaisha Toshiba | Semiconductor device having trenches and method of forming trenches |
| WO1997005649A1 (en) * | 1995-07-25 | 1997-02-13 | Siemens Aktiengesellschaft | Process for manufacturing a self-aligned contact and doped region |
| JP2004071664A (en) * | 2002-08-02 | 2004-03-04 | Sony Corp | Semiconductor device and its manufacturing method |
| DE102004009521A1 (en) * | 2004-02-27 | 2005-09-15 | Austriamicrosystems Ag | High-voltage PMOS transistor |
| US7663203B2 (en) | 2004-02-27 | 2010-02-16 | Austriamicrosystems Ag | High-voltage PMOS transistor |
| DE102004009521B4 (en) * | 2004-02-27 | 2020-06-10 | Austriamicrosystems Ag | High-voltage PMOS transistor, mask for manufacturing a tub and method for manufacturing a high-voltage PMOS transistor |
| US7315062B2 (en) | 2004-03-31 | 2008-01-01 | Eudyna Devices Inc. | Semiconductor device, mask for impurity implantation, and method of fabricating the semiconductor device |
| JP2011171603A (en) * | 2010-02-19 | 2011-09-01 | Oki Semiconductor Co Ltd | Method of manufacturing semiconductor element |
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