JP2582931B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2582931B2 JP2582931B2 JP2238409A JP23840990A JP2582931B2 JP 2582931 B2 JP2582931 B2 JP 2582931B2 JP 2238409 A JP2238409 A JP 2238409A JP 23840990 A JP23840990 A JP 23840990A JP 2582931 B2 JP2582931 B2 JP 2582931B2
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- insulating film
- forming
- diffusion layer
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】 （イ）産業上の利用分野 この発明は半導体装置の製造方法に関し、更に詳しく
はEEPROMやEPROMなどのメモリ素子におけるキャパシタ
形成方法に関するものである。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a capacitor in a memory element such as an EEPROM or an EPROM.
（ロ）従来の技術 従来この種の方法としては、第１のフォトレジストを
用いて、シリコン基板上に、ゲート酸化膜を介してイオ
ン注入によりキャパシタ下部電極並びにこれに隣接して
キャパシタに接続するEPROMのソース・ドレイン領域を
含むN+拡散層を形成し、第１のフォトレジストを除去し
た後、第１のフォトレジストよりも狭いパターンを有す
る第２のフォトレジストを形成し、それによってキャパ
シタ下部電極直上のゲート酸化膜を除去して開口を設
け、第２のフォトレジストを除去した後、続いて開口内
にキャパシタ絶縁膜としてのトンネル酸化膜を熱処理に
よって形成し、しかる後そのトンネル酸化膜を覆ってキ
ャパシタ上部電極としてのN+ポリシリコンのフローティ
ングゲートを形成していた。(B) Conventional technology Conventionally, as a method of this type, a first photoresist is used to connect a capacitor lower electrode and a capacitor adjacent thereto by ion implantation through a gate oxide film on a silicon substrate. After forming an N + diffusion layer including source / drain regions of the EPROM and removing the first photoresist, a second photoresist having a pattern narrower than the first photoresist is formed, thereby forming the lower portion of the capacitor. After removing the gate oxide film just above the electrode to form an opening and removing the second photoresist, a tunnel oxide film as a capacitor insulating film is formed in the opening by heat treatment, and then the tunnel oxide film is removed. A floating gate of N + polysilicon was formed as a capacitor upper electrode to cover.
（ハ）発明が解決しようとする課題 しかし、キャパシタ下部電極を形成する際に、パター
ン幅の広い第１のフォトレジストを用い、キャパシタ絶
縁膜を形成する際に、パターン幅の狭い第２のフォトレ
ジストを用いているので、アライメント余裕に問題があ
る。(C) Problems to be Solved by the Invention However, when forming a capacitor lower electrode, a first photoresist having a large pattern width is used, and when forming a capacitor insulating film, a second photo resist having a small pattern width is used. Since a resist is used, there is a problem in alignment margin.
この発明は１回のフォトパターンでイオン注入窓とキ
ャパシタ絶縁膜を決定する事により、デザインマージン
を０μｍに近付けることができる半導体装置の製造方法
を提供することを目的とするものである。An object of the present invention is to provide a method of manufacturing a semiconductor device in which a design margin can be made close to 0 μm by determining an ion implantation window and a capacitor insulating film by one photo pattern.
（ニ）課題を解決するための手段および作用 この発明は、（ｉ）ゲート絶縁膜を有する半導体基板
上に、全面に、イオン注入窓のパターンを有するフォト
レジストパターンを形成し、これをマスクとして半導体
基板表面のキャパシタ形成領域に、イオン注入により第
１不純物拡散層を形成してこれをキャパシタ下部電極と
し、（ii）上記フォトレジストパターンをマスクとして
上記第１不純物拡散層直上のゲート絶縁膜を除去してキ
ャパシタ絶縁膜形成用開口を形成し、上記フォトレジス
トパターンを除去した後、（iii）キャパシタ絶縁膜形
成用開口を含む半導体基板上に、全面に、熱処理を付
し、上記開口内に熱酸化膜を形成してこれをキャパシタ
絶縁膜とし、（iv）上記熱酸化膜を含む半導体基板上
に、全面に、導電層を形成した後、これをパターン化し
て少なくとも導電膜を上記開口を覆って残存させ、その
残存された導電膜をキャパシタ上部電極とし、（ｖ）こ
の残存された導電膜をマスクにしてイオン注入によって
半導体基板表面に、上記第１不純物拡散層に電気的に接
続する第２不純物拡散層を形成することを特徴とする半
導体装置の製造方法である。(D) Means and Action for Solving the Problems According to the present invention, (i) a photoresist pattern having an ion implantation window pattern is formed on the entire surface of a semiconductor substrate having a gate insulating film, and this is used as a mask. A first impurity diffusion layer is formed by ion implantation in a capacitor formation region on the surface of the semiconductor substrate and used as a capacitor lower electrode. (Ii) A gate insulating film immediately above the first impurity diffusion layer is formed using the photoresist pattern as a mask. After removing to form an opening for forming a capacitor insulating film and removing the photoresist pattern, a heat treatment is applied to the entire surface of the semiconductor substrate including the opening for forming the capacitor insulating film, and A thermal oxide film is formed and used as a capacitor insulating film. (Iv) After forming a conductive layer on the entire surface of the semiconductor substrate including the thermal oxide film, Is patterned to leave at least a conductive film covering the opening, and the remaining conductive film is used as a capacitor upper electrode. (V) The remaining conductive film is used as a mask to perform ion implantation on the surface of the semiconductor substrate. A method for manufacturing a semiconductor device, comprising forming a second impurity diffusion layer electrically connected to a first impurity diffusion layer.
すなわち、この発明はイオン注入窓とキャパシタ絶縁
膜を１回のフォトパターンで決定する事により、イオン
注入により形成されるN+拡散層キャパシタ下部電極とポ
リシリコンN+デポキャパシタ上部電極のデザインマージ
ンを０μｍにするようにしたものである。That is, the present invention determines the ion implantation window and the capacitor insulating film by a single photo pattern, thereby reducing the design margin of the N + diffusion layer capacitor lower electrode and the polysilicon N + deposition capacitor upper electrode formed by ion implantation. The thickness is set to 0 μm.
（ホ）実施例 以下図に示す実施例にもとづいてこの発明を詳述す
る。なお、これによってこの発明は限定を受けるもので
はない。(E) Embodiment The present invention will be described below in detail based on an embodiment shown in the drawings. The present invention is not limited by this.
以下、第１図を用いて本発明の一実施例によるEEPROM
の製造方法について説明する。Hereinafter, an EEPROM according to an embodiment of the present invention will be described with reference to FIG.
A method of manufacturing the device will be described.
まず、第１図（ａ）に示すように、400Å厚のゲート
絶縁膜３を有するSi基板１上に、全面に、イオン注入窓
4aのパターンを有するフォトレジストパターン４を形成
し、これをマスクとしてSi基板表面のキャパシタ形成領
域（Ｒ）に、イオン（75As+）5aの注入によりN+拡散層
（第１不純物拡散層）５を形成してこれをキャパシタ下
部電極とする。First, as shown in FIG. 1 (a), an ion implantation window is
Forming a photoresist pattern 4 having a pattern of 4a, which in the capacitor formation region of the Si substrate surface as a mask (R), ion (75 As +) 5a N + diffusion layer by implantation (first impurity diffusion layer) 5 is formed and used as a capacitor lower electrode.
この際、イオン注入前に、Si基板表面にはVth注入層
２が形成されている。At this time, a Vth implantation layer 2 is formed on the surface of the Si substrate before ion implantation.
次に、フォトレジストパターン４をマスクとして拡散
層５直上のゲート絶縁膜3aを除去してキャパシタ絶縁膜
形成用開口11を形成し［第１図（ｂ）参照］、フォトレ
ジストパターン４を除去した後、キャパシタ絶縁膜形成
用開口11を含むSi基板上に、全面に、熱処理を付し、開
口11内にSiO2のトンネル酸化膜（熱酸化膜）６を100Å
厚に形成してこれをキャパシタ絶縁膜とし［第１図
（ｃ）参照］、 熱酸化膜６を含むSi基板１上に、全面に、N+ポリシリ
コン層（導電層）を形成した後、これをパターン化して
導電膜を開口11を覆って残存させ、その残存された導電
膜をフローティングゲート（キャパシタ上部電極）７と
する［第１図（ｄ）参照］。Next, using the photoresist pattern 4 as a mask, the gate insulating film 3a immediately above the diffusion layer 5 was removed to form an opening 11 for forming a capacitor insulating film [see FIG. 1 (b)], and the photoresist pattern 4 was removed. Thereafter, a heat treatment is applied to the entire surface of the Si substrate including the opening 11 for forming a capacitor insulating film, and a tunnel oxide film (thermal oxide film) 6 of SiO 2 is formed in the opening 11 by 100 μm.
After forming an N + polysilicon layer (conductive layer) on the entire surface of the Si substrate 1 including the thermal oxide film 6, the resultant is used as a capacitor insulating film (see FIG. 1C). This is patterned to leave a conductive film covering the opening 11, and the remaining conductive film is used as a floating gate (capacitor upper electrode) 7 [see FIG. 1 (d)].
この際、同時に、セレクトゲート7aも残存される。 At this time, the select gate 7a also remains.
次にこの残存されたフローティングゲート７をマスク
にしてセルフアライン的にイオン（75As+）10a注入によ
5Si基板表面に、N+拡散層５に電気的に接続するN+の拡
散層（ソース・ドレイン）10を形成する［第１図（ｅ）
参照］。Then the self-aligned manner ion (75 As +) 10a injected to the floating gate 7, which is the remaining mask
An N + diffusion layer (source / drain) 10 electrically connected to the N + diffusion layer 5 is formed on the surface of the 5Si substrate [FIG. 1 (e)].
reference].
最後に、フローティングゲート７上に絶縁膜８を介し
てN+ポリシリコンのコントロールゲート９を形成して素
子が完成する［第１図（ｆ）参照］。Finally, an N + polysilicon control gate 9 is formed on the floating gate 7 via an insulating film 8 to complete the device [see FIG. 1 (f)].
このように本実施例では、同一のマスク４を使ってフ
ローティングゲート７とN+拡散層５のデザインマージン
を０μｍにすることができる。従って、N+拡散層５を必
要最小径まで小さくできる。As described above, in this embodiment, the design margin of the floating gate 7 and the N + diffusion layer 5 can be reduced to 0 μm using the same mask 4. Therefore, the N + diffusion layer 5 can be reduced to the required minimum diameter.
（ヘ）発明の効果 以上のようにこの発明によれば、１回のフォトパター
ンでイオン注入窓とキャパシタ絶縁膜を決定するように
したので、デザインマージンを０μｍにでき、その結
果、キャパシタ下部電極層を必要最小限まで小さくで
き、それによってセルサイズを小さくすることができる
効果がある。(F) Effects of the Invention As described above, according to the present invention, the ion implantation window and the capacitor insulating film are determined by one photo pattern, so that the design margin can be reduced to 0 μm, and as a result, the capacitor lower electrode can be formed. The effect is that the layer can be made as small as necessary, thereby reducing the cell size.
第１図はこの発明の一実施例を説明するための製造工程
説明図である。 １……Si基板、３……ゲート酸化膜、 ４……フォトレジスト、4a……イオン注入窓、 5a,10a……75As+, 5a……N+拡散層（キャパシタ下部電極）、 ６……SiO2のトンネル酸化膜（キャパシタ絶縁膜）、 ７……フローティングゲート（キャパシタ上部電極）。FIG. 1 is an explanatory view of a manufacturing process for explaining an embodiment of the present invention. 1 ... Si substrate, 3 ... Gate oxide film, 4 ... Photoresist, 4a ... Ion implantation window, 5a, 10a ... 75 As + , 5a ... N + diffusion layer (capacitor lower electrode), 6 ... ... SiO 2 tunnel oxide film (capacitor insulating film) 7 ... Floating gate (capacitor upper electrode)
Claims (1)
に、全面に、イオン注入窓のパターンを有するフォトレ
ジストパターンを形成し、これをマスクとして半導体基
板表面のキャパシタ形成領域に、イオン注入により第１
不純物拡散層を形成してこれをキャパシタ下部電極と
し、 （ii）上記フォトレジストパターンをマスクとして上記
第１不純物拡散層直上のゲート絶縁膜を除去してキャパ
シタ絶縁膜形成用開口を形成し、上記フォトレジストパ
ターンを除去した後、 （iii）キャパシタ絶縁膜形成用開口を含む半導体基板
上に、全面に、熱処理を付し、上記開口内に熱酸化膜を
形成してこれをキャパシタ絶縁膜とし、 （iv）上記熱酸化膜を含む半導体基板上に、全面に、導
電層を形成した後、これをパターン化して少なくとも導
電膜を上記開口を覆って残存させ、その残存された導電
膜をキャパシタ上部電極とし、 （ｖ）この残存された導電膜をマスクにしてイオン注入
によって半導体基板表面に、上記第１不純物拡散層に電
気的に接続する第２不純物拡散層を形成することを特徴
とする半導体装置の製造方法。(1) A photoresist pattern having an ion implantation window pattern is formed on the entire surface of a semiconductor substrate having a gate insulating film, and the photoresist pattern is used as a mask to ion-implant a capacitor forming region on the surface of the semiconductor substrate. By first
Forming an impurity diffusion layer and using this as a capacitor lower electrode; (ii) removing the gate insulating film immediately above the first impurity diffusion layer using the photoresist pattern as a mask to form an opening for forming a capacitor insulating film; After removing the photoresist pattern, (iii) heat treatment is applied to the entire surface of the semiconductor substrate including the opening for forming the capacitor insulating film, and a thermal oxide film is formed in the opening to form a capacitor insulating film; (Iv) After a conductive layer is formed on the entire surface of the semiconductor substrate including the thermal oxide film, the conductive layer is patterned to leave at least the conductive film covering the opening, and the remaining conductive film is placed on top of the capacitor. (V) a second impurity diffusion layer electrically connected to the first impurity diffusion layer on the surface of the semiconductor substrate by ion implantation using the remaining conductive film as a mask; Method of manufacturing a semiconductor device and forming.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2238409A JP2582931B2 (en) | 1990-09-08 | 1990-09-08 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2238409A JP2582931B2 (en) | 1990-09-08 | 1990-09-08 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04118960A JPH04118960A (en) | 1992-04-20 |
| JP2582931B2 true JP2582931B2 (en) | 1997-02-19 |
Family
ID=17029782
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2238409A Expired - Fee Related JP2582931B2 (en) | 1990-09-08 | 1990-09-08 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2582931B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1112731C (en) * | 1997-04-30 | 2003-06-25 | 三星电子株式会社 | Method for making capacitor used for analog function |
-
1990
- 1990-09-08 JP JP2238409A patent/JP2582931B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04118960A (en) | 1992-04-20 |
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