JPH02209767A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the number of steps by forming gates for an enhancement type and depletion type transistor on a gate insulating film, forming source/drain diffused layer with the electrodes as masks, and forming a program diffused layer of a mask for forming the program diffused layer to cover the gate for the enhancement type transistor. CONSTITUTION:Polysilicon is deposited on a gate insulating film 4, selectively etched to form a gate electrode 5a for an enhancement type transistor and a gate electrode 5b for a depletion type transistor. With the electrodes 5a, 5b as masks impurity is implanted into a substrate 1 to form source/drain diffused layer 6. Then, a resist is so patterned as to cover the electrode 5a for the enhancement type transistor to form a mask 7 for forming a program diffused layer, an impurity is implanted into the substrate 1 with the mask 7 to form a program diffused layer 8. Thus, the number of steps after the program diffused layer is formed is reduced to accelerate a TAT.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a semiconductor device, TAT can be achieved by reducing the number of steps after forming a programmed diffusion layer.
The purpose of the present invention is to provide a method for manufacturing a semiconductor device that can speed up the turn around time and easily deliver the product within the deadline, by sequentially forming a field oxide film and a gate insulating film on a substrate. a step of forming a gate electrode for an enhancement type transistor and a gate electrode for a depletion type transistor on the gate insulating film; and forming a source/drain diffusion layer by introducing impurities into the substrate using each of the gate electrodes as a mask. a step of forming a mask for forming a program diffusion layer covering the gate electrode for the enhancement type transistor; and a step of introducing impurities into the substrate using the mask for forming a program diffusion layer to form a program diffusion layer. and a step of removing the mask for forming the program diffusion layer, or a step of sequentially forming a field oxide film and a gate insulating film on the substrate, and a step of forming an enhancement type transistor gate on the gate insulating layer. A step of forming an electrode and a gate electrode for a depletion type transistor, a step of forming a mask for forming a program diffusion layer covering the gate electrode for the enhancement type transistor, and a step of forming an impurity in the substrate using the mask for forming a program diffusion layer. a step of removing the mask for forming the program diffusion layer; and a step of introducing impurities into the substrate using each of the gate electrodes as a mask to form a source/drain diffusion layer. Configure to include.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and particularly relates to a semiconductor device using an insulated gate field effect transistor, particularly a NAN device.
It can be applied to the manufacturing method of D-type mask ROM, and for details, especially TAT (Turn Around Timing).
The present invention relates to a method for manufacturing a semiconductor device that can speed up e).

In recent years, semiconductor devices such as semiconductor memories, which are widely used in computer systems, measurement systems, and various electronic devices, are required to have a high degree of integration, especially in response to demands for storage density. Mask RO functions as semiconductor memory
A semiconductor device called M is attracting attention because of its feature that information can be written in advance during the manufacturing process (ROM data writing). Semiconductor devices called mask ROMs include NOR type mask ROMs and NAND type mask ROMs.

Here, the NOR type mask ROM can select one transistor by selecting one word line and one bit line, and is configured with one contour ball for one or two transistors. (1 or 2 contact holes for 2 transistors). On the other hand, NAND mask ROM can be configured with multiple transistors such as 8 or 16 to be selected for one bit line, and can be configured with one contact hole for multiple transistors. can do.

For this reason, with the demand for integration, NAND mask ROMs, which can be integrated even with a reduced number of contact holes, have become mainstream.

However, NAND type mask ROM is N.

Compared to the R-type mask ROM, it has the disadvantage that the process period from receiving data from the user to shipping it, that is, the TAT, is longer.

Therefore, there is a need for a method of manufacturing a semiconductor device that can be integrated and have a quick turnaround time.

(Prior Art) The prior art will be specifically described below with reference to the drawings.

3 to 5 are diagrams for explaining the conventional method of manufacturing a semiconductor device. FIGS. 3(a) and 5(b) are diagrams showing the details of the structure of the conventional example, and FIG. 4 is the diagram of the conventional example. Circuit diagram, Figure 5 (la)
-(7a) are diagrams illustrating the manufacturing process of a conventional example. Note that Fig. 3(a) is a plan view, and Fig. 3(b) is a plan view of Fig. 3(a).
) is a sectional view taken in the A1-A2 direction. Note that the illustrated semiconductor device can be applied to a NAND type mask ROM.

In these figures, 21 is a substrate made of Si, for example;
22 is a channel cut, and 23 is a field oxide film made of, for example, SiO□, which functions as an element isolation region. 24 is a mask for forming a program diffusion layer, 25 is a program diffusion layer, 26 is a gate insulating film made of, for example, SiO□, and 27a and 27b are gate electrodes made of, for example, polysilicon (for example, metal silicide such as WSi). It also functions as a line. The gate electrode 27a is a gate electrode for an enhancement type transistor, and the gate electrode 27b is a gate electrode for a depletion type transistor. 28 is a source/drain diffusion layer, 29 is a silicon oxide film made of, for example, Sin, 30 is a bit line, 31 is a word line, 32 is an enhancement type transistor, and 33 is a depletion type transistor.

Note that the operation here is not the same as in the NOR type, where vth (threshold voltage) is raised or lowered to determine whether the bit line potential drops or not.
As shown in FIG. 4, a method is used in which a depletion type transistor 33 and an enhancement type transistor 32 are used to identify whether the potential of the bit line is lowered or not.

Next, the manufacturing process will be explained.

Note that FIG. 5(1a) is a cross-sectional view taken in the B1-82 direction of the plan view shown in FIG. 5(2a), and FIG. 5(3a)
, (5a) to (7a) are C1-C shown in FIG. 5 (4a).
It is a sectional view in two directions.

First, as shown in FIGS. 5(1a) and 5(2a), after forming a channel cut 22 by selectively introducing an impurity of, for example, B into the substrate 21, the substrate 21 is formed by field oxidation.
1 is selectively oxidized to form a field oxide film 23 which functions as an element isolation region.

Next, as shown in FIGS. 5(3a) and 5(4a), after patterning the resist to form a mask 24 for forming a program diffusion layer on the base 21, an ion implantation method in which the impurity is, for example, P. Accordingly, the mask 2 for forming the program diffusion layer is
4 to introduce a dull material into the substrate 21 to form a program diffusion layer 25. This is the so-called ROM data writing process.

Next, as shown in FIG. 5 (5a), after removing the program diffusion layer forming mask 24, the substrate 2 is heated by thermal oxidation.
1 is selectively oxidized to form a gate insulating film 26.

Next, as shown in FIG. 5(6a), polysilicon is deposited on the entire surface by, for example, the CVD method, and then the polysilicon is selectively etched by, for example, by the RIE method to form the gate electrode 27a for the enhancement type transistor and the depletion type transistor. A transistor gate electrode 27b is formed.

Next, as shown in FIG. 5 (7a), for example, if the impurity is
After forming the source/drain diffusion layer 28 by introducing impurities into the substrate 21 by the ion implantation method of s', as shown in FIG.
As shown in b), the gate electrode 2 is formed by thermal oxidation, for example.
A silicon oxide film 29 is formed by selectively oxidizing 7a and 27b. Then, an interlayer insulating film made of, for example, PSG is formed on the entire surface, and a contact hole is formed by selectively etching the insulating film between the eyebrows. A semiconductor device is completed by forming a wiring layer consisting of the following.

Note that the gate insulating film 26 shown in FIG. 5(5a) may be formed after the field oxide film 23 is formed before the program diffusion layer forming mask 24 is formed.

(Problems to be Solved by the Invention) However, in such a conventional method for manufacturing a semiconductor device, as shown in FIGS. 5(3a) and (4a),
The program diffusion layer 25 formation process (ROM data writing process) for forming the depression type transistor 33 is performed before the gate electrode 27 is formed as shown in FIG. T
It had the disadvantage that AT was not very fast. For this reason, when the delivery date is short, there is a problem in that it becomes difficult to deliver the product within the delivery date.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device, which can reduce the number of steps after forming a program diffusion layer, thereby speeding up TAT, and making it easier to deliver a product on time.

(Means for Solving the Problems) In order to achieve the above object, a method for manufacturing a semiconductor device according to the first invention includes a step of sequentially forming a field oxide film and a gate insulating film on a substrate, and an enhancement film on the gate insulating film. a step of forming a gate electrode for a type transistor and a gate electrode for a depletion type transistor, a step of introducing impurities into the substrate using each gate electrode as a mask to form a source/drain diffusion layer, and a step of forming a source/drain diffusion layer for the enhancement type transistor. a step of forming a program diffusion layer formation mask covering the electrode; a step of introducing impurities into the substrate using the program diffusion layer formation mask to form a program diffusion layer; and a step of forming the program diffusion layer formation mask. The method includes a step of removing.

In order to achieve the above object, a method for manufacturing a semiconductor device according to a second invention includes a step of sequentially forming a field oxide film and a gate insulating film on a substrate, and a gate electrode for an enhancement type transistor and a gate electrode for a depletion type transistor on the gate insulating film. a step of forming a mask for forming a program diffusion layer covering the gate electrode for the enhancement type transistor; and a step of introducing impurities into the substrate using the mask for forming a program diffusion layer to perform program diffusion. The method includes a step of forming a layer, a step of removing the mask for forming the program diffusion layer, and a step of introducing impurities into the substrate using each of the gate electrodes as a mask to form a source/drain diffusion layer.

[Effect]

In the first invention, after a field oxide film and a gate insulating film are sequentially formed on a substrate, and a gate electrode for an enhancement type transistor and a gate electrode for a depletion type transistor are formed on the gate insulating film, each of the gate electrodes is Impurities are introduced into the substrate as a mask to form source/drain diffusion layers. Next, the enhancement transistor gate electrode is covered to form a program diffusion layer formation mask, and the program diffusion layer formation mask is used to introduce impurities into the substrate to form a program diffusion layer. The forming final mask is removed.

Therefore, as shown in FIG. 1(7a), the process of forming the program diffusion layer 8 for forming the depletion type transistor 33 is performed to form the gate electrodes 5a and 5b shown in FIGS. 1(4a) and 1(5a). Since it is performed after the formation of the source/drain diffusion layer 6 shown in FIG. 1 (6a) later, the number of steps after the formation of the program diffusion layer 8 can be reduced compared to the conventional method, and the TAT can be made faster. You will be able to do this. This makes it easier to deliver products on time than with conventional methods.

In the second invention, a field oxide film and a gate insulating film are sequentially formed on a substrate, and a gate electrode for an enhancement type transistor and a gate electrode for a depletion type transistor are formed on the gate insulating film. A mask for forming a program diffusion layer is formed by covering the gate electrode. Next, impurities are introduced into the substrate using a program diffusion layer formation mask to form a program diffusion layer, and after the program diffusion layer formation mask is removed, impurities are introduced into the substrate using each gate electrode as a mask. A source/drain diffusion layer is formed.

Therefore, as shown in FIG. 2(1a), since the step of forming the program diffusion layer 8 for forming the depletion type transistor 33 is performed after the formation of the gate electrodes 5a and 5b, the process of forming the program diffusion layer 8 is performed after the formation of the program diffusion layer 8, compared to the conventional method. The number of steps can be reduced, and TAT can be made faster. For this reason, it becomes easier to deliver products on time than with conventional methods.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

FIGS. 1(a) to 1(8a) are diagrams illustrating manufacturing steps of an embodiment of the method for manufacturing a semiconductor device according to the first invention. In addition, detailed diagrams of the structure (Fig. 3 (a), (b)) are shown here.
) and the circuit diagram (FIG. 4) are the same as the conventional one, and therefore will be omitted. The illustrated semiconductor device is a NAND type mask RO.
It can be applied to M.

In these figures, ■ is a substrate made of, for example, Si;
3 is a channel cut, and 3 is a field oxide film made of, for example, SiO□, which functions as an element isolation region. 4 is a gate insulating film made of, for example, SiOz; 5a;
Reference numeral 5b denotes a gate electrode made of polysilicon (for example, metal silicide such as WSi), which also functions as a word line. The gate electrode 5a is a gate electrode for an enhancement type transistor, and
The electrode 5b is a gate electrode for a depression type transistor. 6 is a source/drain diffusion layer, 7 is a mask for forming a program diffusion layer made of, for example, resist, and 8 is a program diffusion layer.

Next, the manufacturing process will be explained.

In addition, here, Fig. 1 (la) and (3a) are shown in Fig. 1 (2a).
) is a cross-sectional view in the Di-D2 direction of the plan view shown in FIG.
Figures (4a), (6a) to (8a) are cross-sectional views taken in the El-22 direction shown in Figure 1 (5a).

First, as shown in FIGS. 1(1a) and (2a), after selectively introducing an impurity, for example, B into the substrate 1 to form a channel cut 2, the substrate 1 is selectively removed by field oxidation. The thickness of the film that is oxidized and functions as the element valve If region is, for example, 5000 + 1 - 2 formed by field oxidation.

Next, as shown in FIG. 1(3a), the substrate 1 is selectively oxidized by, for example, a thermal oxidation method to obtain a film with a thickness of, for example, 200 to 200 nm.
50 gate insulating films 4 are formed.

Note that when controlling the channel of an enhancement type transistor, it is preferable to introduce P-type impurities by ion implantation.

Next, as shown in FIGS. 1(4a) and 1(5a), polysilicon is deposited on the gate insulating film 4 to a thickness of, for example, 3,000 to 4,000 by, for example, the CVD method, and by, for example, RIE.
After selectively etching polysilicon by a method to form a gate electrode 5a for an enhancement type transistor and a gate electrode 5b for a depletion type transistor, the gate electrodes are etched by an ion implantation method using impurities such as A s '' and an acceleration energy of 70 KeV, for example. 5a,
Impurities are introduced into the substrate 1 using the mask 5b as a mask to form a source/drain diffusion layer 6.

Next, as shown in FIG. 1 (7a), after applying a resist to the entire surface, the resist is exposed and developed so as to cover the gate electrode 5a for the enhancement type transistor, and a mask 7 for forming a program diffusion layer is formed. After forming, the impurity is, for example, As” (also P”),
The program diffusion layer 8 is formed by introducing impurities into the base 415.1 using the program diffusion layer forming mask 7 by ion implantation with an acceleration energy of, for example, 70 to 180 KeV.

Here, it is preferable that the structure of the debension type transistor 33 composed of the program diffusion layer 8 has a source-drain distance (effective channel length) smaller than that of the enhancement type transistor 32, and the gate electrode is Even if the transistor is OV, the structure is such that when a drain voltage is applied, a current flows between the source and the drain and the transistor is turned on. For this reason, ions are implanted only into the portion where the depletion transistor is to be formed, with the acceleration energy and implantation amount being larger than when forming the source/drain diffusion layer 6. Further, depending on the acceleration energy conditions or the gate length, the source/drain regions may be connected at the channel portion, but they may be connected. Further, the source-drain current can be adjusted as appropriate by adjusting the acceleration energy and implantation amount when ions are implanted into the depletion type transistor 33 portion.

Next, as shown in FIG. 1(8a), the program diffusion layer forming mask 7 is removed. In the subsequent steps, as in the conventional method, the gate electrodes 5a and 5b are selectively oxidized to form a silicon oxide film 29, an interlayer insulating film made of, for example, PSG is formed on the entire surface, and the interlayer insulating film is selectively oxidized. After forming a contact hole by etching, contact is made with the source/drain diffusion layer 6 through the contact hole. A semiconductor device is completed by forming a wiring layer consisting of .

That is, in the above embodiment, as shown in FIG. 1(7a), the process of forming the program diffusion layer 8 for forming the depletion type transistor 33 is performed as shown in FIGS. 1(4a) and (5).
After the gate electrodes 5a and 5b shown in a) are formed, the first
Since the process is performed after the formation of the source/drain diffusion layer 6 shown in FIG. The number of steps after forming 8 can be reduced (about 1/2), and TAT can be made faster. Therefore, it is easier to deliver the product on time than with the conventional method.

Further, since preparation can be carried out after the process has proceeded to the formation of the source/drain diffusion layer 6, there is an advantage that the influence of dust is less than in the conventional method and the yield can be improved.

In addition, in the case of the conventional method using the program diffusion layer forming mask 7 before forming the gate electrodes 5a and 5b, the gate electrodes 5a and 5b are
, 5b and the program diffusion layer forming mask 7 are aligned between layers, an extra margin in case of misalignment is required compared to direct alignment, whereas in the above embodiment, direct alignment is required. Therefore, no extra margin is required and it is suitable for miniaturization.

FIGS. 2(1a) and 2(2a) are diagrams for explaining the manufacturing process of an embodiment of the method for manufacturing a semiconductor device according to the second invention.

In this figure, the same reference numerals as in FIGS. 1(1a) to (8a) indicate the same or corresponding parts.

Next, the manufacturing process will be explained.

Note that the steps from the formation of the channel cut 2 to the formation of the enhancement-type transistor gate electrode 5a and the depletion-type transistor gate electrode 5b are the same as in the first embodiment of the invention, and will therefore be omitted.

Then, as shown in FIG. 2 (1a), the gate electrode 5a
, 5b, a resist is applied to the entire surface, exposed to light, and developed to form a gate electrode 5a for an enhancement type transistor.
A resist is patterned to cover the program diffusion layer forming mask 7. Next, impurities are introduced into the substrate 1 using the mask 7 for forming a program diffusion layer by an ion implantation method in which the impurity is, for example, As''(P'' may also be used) and the acceleration energy is, for example, 70 to 180 eV. form 8.

Next, as shown in FIG. 2 (2a), after removing the program diffusion layer forming mask 7, an ion implantation method using impurities such as P and an acceleration energy of 100 KeV is performed using the gate electrodes 5a and 5b as masks. Impurities are introduced into the substrate 1 to form source/drain diffusion layers 6. The subsequent steps are the same as those of the conventional method and will therefore be omitted.

That is, in the above embodiment, as shown in FIG. 2(1a), since the step of forming the program diffusion layer 8 for forming the depletion type transistor 33 is performed after forming the gate electrodes 5a and 5b, the gate? ? 1Fi5a, 5
Preparation can be performed while the process has proceeded up to the formation of b, and the number of steps after the formation of programmed diffusion N8 can be reduced (about 1/2) compared to the conventional method, and TAT
This makes it easier to deliver products on time than with conventional methods.

Further, since preparation can be carried out in a state where the process has proceeded to the formation of the gate electrodes 5a and 5b, there is an advantage that the influence of dust is less than that of the conventional method and the yield can be improved.

In addition, in the case of the conventional method using the program diffusion layer forming mask 7 before forming the gate electrodes 5a and 5b, the gate electrodes 5a and 5b are
, 5b and the mask 7 for forming a programmed diffusion layer are aligned between the eyebrows, so an extra margin in case of misalignment is required compared to the case of direct alignment. In the example, it is direct alignment, so
No extra margin is required and it is suitable for miniaturization.

In each of the embodiments of the first and second inventions, the acceleration energy of ion implantation in the day-precision transistor section is different when the distance between the gate electrodes of adjacent transistors is large or when the field oxide film 3 is thick. (approximately 8,000 people), high acceleration energy of around 180 KeV may be used, but as the distance between the gate electrodes becomes smaller, lateral diffusion of impurities becomes more pronounced, and leakage due to impurities penetrating the field oxide film 3 becomes more likely. If there is a risk, it is preferable to use the lowest possible acceleration energy of 100 KeV or less. The penetration of the impurity into the lateral diffusion layer and the impurity field oxide film 3 differs depending on the impurity to be introduced, for example, P' and As', so it is preferable to appropriately determine the penetration of the device to be applied.

(Effects of the Invention) According to the present invention, the number of steps after forming the program diffusion layer can be reduced, TAT can be made faster, and the product can be delivered on time.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the manufacturing process of an embodiment of the method for manufacturing a semiconductor device according to the first invention, and FIG. 2 is a diagram illustrating the manufacturing process of an embodiment of the method for manufacturing a semiconductor device according to the second invention. 3 to 5 are diagrams explaining a conventional method of manufacturing a semiconductor device, FIG. 3 is a diagram showing details of the structure of the conventional example, and FIG. 4 is a circuit diagram of the conventional example. FIG. 5 is a diagram illustrating the manufacturing process of a conventional example. ■...Substrate, 2...Channel cut, 3...Field oxide film,...Gate insulating film, a, 5b...Gate Electrode, ... Source/drain diffusion layer, ... Mask for forming the program diffusion layer, ... Program diffusion layer. 11/f A diagram illustrating the manufacturing process of an embodiment of the invention of No. 81 Figure 1 A diagram illustrating the manufacturing process of an embodiment of the invention of No. 1 (Q) (b) A diagram showing details of the W-stretched structure Figure 3: Figure 3 for explaining the manufacturing process of an embodiment of the second invention

Claims (2)

[Claims] (1) A step of sequentially forming a field oxide film and a gate insulating film on the substrate, a step of forming a gate electrode for an enhancement type transistor and a gate electrode for a depletion type transistor on the gate insulating film, and a step of forming each of the gate electrodes on the gate insulating film. forming a source/drain diffusion layer by introducing impurities into the substrate as a mask; forming a program diffusion layer formation mask covering the enhancement transistor gate electrode; and the program diffusion layer formation mask. 1. A method of manufacturing a semiconductor device, comprising: forming a program diffusion layer by introducing impurities into a substrate using the method; and removing the mask for forming the program diffusion layer. (2) a step of sequentially forming a field oxide film and a gate insulating film on the substrate; a step of forming a gate electrode for an enhancement type transistor and a gate electrode for a depletion type transistor on the gate insulating film; a step of forming a program diffusion layer formation mask covering the gate electrode; a step of introducing impurities into the substrate using the program diffusion layer formation mask to form a program diffusion layer; and the program diffusion layer formation mask. A method for manufacturing a semiconductor device, comprising: removing impurities into the substrate using each of the gate electrodes as a mask to form a source/drain diffusion layer.