JP3212689B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a method of manufacturing a mask ROM formed by an enhancement type transistor and a depletion type transistor. And a method of manufacturing the same, which can reduce the number of steps after completion of the ROM data.

[0002] A mask ROM is a ROM in which information is written in a manufacturing process. The mask ROM has a contact method of writing ON and OFF depending on whether a wiring window for a drain is opened or not, or a depletion method by an ion implantation method. There is an ED method in which the (D) type is formed as an enhancement (E) type, the depletion type is turned on, and the enhancement type is turned off to store information. The memory cell of this mask ROM is DR
Since it can be smaller than AM, there is an advantage that the storage capacity can be increased, and it is suitable for mass production and is inexpensive.

However, since the gate electrode is not formed and the gate oxide film is formed (waited) until information from the user is received, the number of steps after completion of the ROM data is very large, However, there was a disadvantage that it took a long time. For this reason, there is a demand from the user to reduce the number of steps after completion of the ROM data to shorten the delivery date.

[0004]

2. Description of the Related Art FIG. 3 is a view for explaining a conventional method for manufacturing a semiconductor device. The illustrated example is a case where the present invention is applied to a method of manufacturing a mask ROM. In FIG. 3, reference numeral 31 denotes a p-type substrate made of, for example, Si, 32 denotes a field oxide film such as SiO ₂ formed by selectively oxidizing the substrate 31, and 33 denotes a substrate formed between the field oxide films 32 by heat. Oxidized SiO ₂
And the like. Next, reference numeral 34 denotes a resist mask formed by patterning a resist corresponding to a depletion region and having an opening 35 in which the gate insulating film 33 is exposed, and 36 denotes an n-type, for example, of the opposite conductivity type to the substrate 31. Is a depletion area. Reference numeral 38 denotes, for example, an n-type source / drain diffusion layer.

Next, a method of manufacturing the semiconductor device will be described. First, as shown in FIG.
After the p-type Si substrate 31 is selectively oxidized to form the SiO ₂ field oxide film 32 by the
The i-substrate 31 is thermally oxidized to form a SiO ₂ gate insulating film 33. In this state, the program is stored until a program from the user enters.

Next, when a program is entered by a user, as shown in FIG. 3B, a resist is applied to the entire surface, and the resist corresponding to the depletion region is patterned by exposure and development to depletion. A resist mask 34 for forming a region is formed. At this time, an opening 35 is formed in which the portion of the gate insulating film 33 corresponding to the depletion region is exposed. Next, ion implantation for forming a depletion region is performed in the Si substrate 31 using the resist mask 34 through the gate insulating film 33 in the opening 35. At this time, an n-type impurity such as As is introduced.

Next, as shown in FIG. 3C, after removing the resist mask 34, heat treatment is performed to activate As ⁺ introduced into the substrate 31, thereby forming an n-type depletion region 36. . Next, after a polysilicon film is formed on the entire surface by a CVD method or the like, the polysilicon film is etched by RIE or the like to form a gate electrode 37. Then, as shown in FIG. 3D, after ion implantation for forming a source / drain by As ⁺ or the like is performed into the substrate 31 through the gate insulating film 33 using the gate electrode 37 as a mask.
Heat treatment is performed to activate As ⁺ introduced into the substrate 31 so that n ⁺
Type source / drain diffusion layer 38 is formed, and PSG
By forming an interlayer insulating film such as a contact hole, a wiring layer such as Al, etc., a mask RO composed of an enhancement type transistor and a depletion type transistor is formed.
M can be obtained.

The impurity was introduced under the gate electrode 37 only under the gate electrode 37 of the depletion type transistor as shown in FIG. 31. However, in order to change the surface concentration, the impurity was introduced under the gate electrode 37 of the enhancement type MOS transistor. Also, impurities may be introduced.

[0009]

As described above, according to the conventional method of manufacturing a semiconductor device, the gate insulating film 33 is formed and waited (stored) until information from a user is input.
Therefore, the number of steps after completion of the ROM data from the user is very large, and there is a problem that the delivery time is long.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of reducing the number of steps after completion of ROM data from a user and shortening a delivery time.

[0011]

In order to achieve the above object, a semiconductor device according to the present invention has a pair of gate electrodes formed separately on a gate insulating film formed on a substrate, and a pair of gate electrodes under each of the gate electrodes. is the formation in the substrate, and the substrate and the pair of diffusion layers having opposite conductivity type, the substrate of the pair of gate electrodes between the regions and each of the sides of the gate electrode opposite to the substrate with each other A source / drain diffusion layer formed to be in contact with the pair of diffusion layers and having a conductivity type opposite to that of the substrate, wherein the pair of gate electrodes apply a predetermined voltage. When applied, the depletion layers in the vicinity of each of the diffusion layers are separated from each other by a distance in which the depletion layers are in contact with each other. A region between the pair of gate electrodes of the substrate has at least the same conductivity type as the substrate. It is characterized in that it comprises means for enhancement mode operation by applying a predetermined voltage to the gate electrode of.

[0012] In the present invention, it can be preferably applied to the case where the logic gates by combining semiconductor device and a depletion-type transistor that can be enhancement mode operation of this is formed. Further, the present invention can be preferably applied to a case where a mask ROM is formed by this logic gate. In this case, the number of steps after completion of ROM data from a user can be reduced by the conventional enhancement gate composed of one gate electrode. It can be reduced compared to the case of the type transistor, and the delivery time can be shortened.

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention forms an element isolation insulating film on a substrate, forms a depletion transistor region on the substrate between the element isolation insulating films, and Forming an enhancement type transistor region adjacent to the type transistor region, then forming a gate insulating film on the substrate of the depletion type transistor region and the enhancement type transistor region, and then forming the depletion type transistor region Forming one depletion region in the enhancement transistor region and forming two depletion regions in the enhancement transistor region; and then depleting the depletion transistor region and the enhancement transistor region. Forming a gate electrode on the gate insulating film corresponding to the depletion region, and then adjacent to the depletion region so as not to be formed on the substrate between the two gate electrodes of the enhancement transistor region. And forming a source / drain diffusion layer in the substrate.

[0014]

FIG. 1 is a diagram illustrating the principle of the present invention. In FIG. 1, reference numeral 1 denotes a substrate of, for example, p-type Si, 2 denotes a field oxide film such as SiO ₂ formed by selectively oxidizing the Si substrate 1, and 3 denotes a film formed by thermally oxidizing the Si substrate 1. A gate insulating film such as SiO ₂ . Reference numeral 4 denotes two gate electrodes made of poly-Si or the like which are formed on the gate insulating film 3 and are separated from each other. Reference numeral 4 denotes a gate electrode which is separated between the two gate electrodes 4 and has two gate electrodes. Gate electrode 4
A depletion region formed in the lower substrate 1 and having a conductivity opposite to that of the substrate 1 (for example, between n-types). Reference numeral 6 denotes a substrate adjacent to the depletion region 5 and between the gate electrode 4 and the field oxide film 2. 1, for example, an n-type source / drain diffusion layer.

As described above, according to the present invention, the gate insulating film 3
Two gate electrodes 4 are formed above and separated from each other. A depletion region of the opposite conductivity type to the substrate 1 is formed in the substrate 1 below the two gate electrodes 4 and separated from each other. An enhancement-type transistor is formed by forming two of the gate electrodes 5, and a predetermined voltage is applied to the two gate electrodes 4 to deplete and contact the two depletion regions 5 to perform an enhancement-type operation. Note that the distance A between the two gate electrodes 4 is set in advance to a distance at which the two depletion regions 5 are depleted and contacted by applying a predetermined voltage to the two gate electrodes 4.

In the present invention, a mask ROM is formed by combining the enhancement type transistor comprising the two gate electrodes 4 and the same depletion type transistor as in the prior art, and this is applied to a method for manufacturing the mask ROM. Since the source / drain forming step can be performed after the completion of the ROM data from the user and the data can be written as in the embodiment, the number of steps to be performed after the completion of the ROM data from the user can be extremely reduced as compared with the related art. , Delivery time can be shortened.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 2 is a diagram illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 2, the same reference numerals as those in FIG. 1 denote the same or corresponding portions, and 11 denotes a resist mask having an opening 12 in which a resist corresponding to a depletion region is patterned and formed, and a gate insulating film 3 is exposed. And 13 are resist masks formed over the two gate electrodes 4 formed in the enhancement transistor region and over the gate insulating film 3 between the two gate electrodes 4. The resist mask 13 is formed by a user. R
This is the mask pattern selected after the completion of the OM data.

Next, a method of manufacturing the semiconductor device will be described. First, as shown in FIG.
After the p-type Si substrate 1 is selectively oxidized to form a SiO ₂ field oxide film 2 having a thickness of about 1 μm, the Si substrate 1 between the field oxide films 2 is thermally oxidized to form a Si
An O ₂ gate insulating film 3 is formed.

Next, as shown in FIG. 2B, a resist is applied to the entire surface, and the resist corresponding to the depletion region is patterned by exposure and phenomenon to form a resist mask 11 for forming a depletion region. . At this time, an opening 12 is formed in which a portion of the gate insulating film 3 corresponding to the depletion region is exposed. This opening 12
Are formed not only in the depletion type transistor region but also in the enhancement type transistor region. Next, ion implantation for forming a depletion region (for example, As ⁺ or P ⁺ , 10 ¹² cm ^{−2) is performed in the} substrate 1 through the gate insulating film 3 in the opening 12 using the resist mask 11.
Do).

Next, as shown in FIG. 2C, after the resist mask 11 is removed, a heat treatment is performed to activate the impurities (As ⁺ , P ^+, etc.) introduced into the substrate 1 to make n
The depletion region 5 of the mold is formed. Then, CVD
Polysilicon is deposited on the entire surface by a method or the like to form a polysilicon film having a thickness of several thousand Å, and then the polysilicon film is etched by RIE or the like to form a gate electrode 4 on the gate insulating film 3 corresponding to the depletion region 5. To form In this state, the program is stored until a program from the user enters.

Next, as shown in FIG.
When these programs come in, resist
Apply and pattern the resist by exposure phenomenon
Two transistors formed in the enhancement transistor region.
A gate insulating film between the gate electrodes 4 from above the gate electrodes 4
After a resist mask 13 is formed over
The resist mask 13 selected after the completion of the ROM data
To form source / drain in substrate 1
Injection (for example, As⁺Or P⁺, 10^Fifteencm ^-2degree)
And heat treatment is performed to introduce impurities (As) introduced into the substrate 1.
⁺, P⁺) To activate n-type source / drain diffusion
The layer 6 is formed. And an interlayer insulating film such as PSG,
By forming wiring layers such as tact holes and Al
Enhancement type transistor consisting of two gate electrodes 4
A transistor consisting of a transistor and one gate electrode 4 as in the prior art.
Mask ROM composed of compression transistors
Can be obtained.

As described above, in the present embodiment, two gate electrodes 4 are formed on the gate insulating film 3 at a distance, and the two gate electrodes 4 are separated from each other. An enhancement type transistor is formed by forming two depletion regions 5 of the opposite conductivity type to the substrate 1 in the lower substrate 1, and a predetermined voltage is applied to two gate electrodes 4 to form two depletion regions 5. Are depleted and brought into contact to perform an enhanced operation. In addition, two gate electrodes 4
The distance between them is set in advance to a distance where two depletion regions 5 are depleted and contacted by applying a predetermined voltage to the two gate electrodes 4.

In this embodiment, a mask ROM is formed by combining the enhancement type transistor including the two gate electrodes 4 and the same depletion type transistor as in the prior art, and this is applied to a mask ROM manufacturing method. Therefore, the depletion region 5 is formed not only in the depletion transistor region but also in the enhancement transistor region, and then the gate electrode 4 is formed on the gate insulating film 3 corresponding to the depletion transistor region and the depletion region 5 in the enhancement transistor region. Can be stored until a program from a user enters. Therefore,
The process can be advanced compared to the case where the storage is performed with the conventional gate insulating film 3 formed, and the source / drain forming process can be performed and the data can be written after the completion of the ROM data from the user. The number of steps to be performed after completion of the ROM data can be reduced as compared with the conventional case, and the delivery time can be shortened.

[0024]

According to the present invention, there is an effect that the number of steps after the completion of ROM data from the user can be reduced to shorten the delivery time.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 3 is a diagram illustrating a method of manufacturing a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Field oxide film 3 Gate insulating film 4 Gate electrode 5 Depletion area 6 Source / drain diffusion layer 11 Resist mask 12 Opening 13 Resist mask

Continuation of the front page (56) References JP-A-3-293763 (JP, A) JP-A-2-246365 (JP, A) JP-A-2-209767 (JP, A) JP-A-2-23658 (JP) JP-A-1-276757 (JP, A) JP-A-62-248251 (JP, A) JP-A-61-147565 (JP, A) JP-A-58-3265 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/8246 H01L 27/112

Claims (4)

(57) [Claims] A pair of gate electrodes (4) formed apart from each other on a gate insulating film (3) formed on a substrate (1).
A pair of diffusion layers (5) formed in the substrate (1) below each of the gate electrodes (4) and having an opposite conductivity type to the substrate (1); A region between the pair of gate electrodes (4) and the substrate (1) opposite to each other with the respective gate electrodes (4) interposed therebetween, each being formed so as to be in contact with the pair of diffusion layers (5); A source / drain diffusion layer having a conductivity type opposite to that of the substrate (1), wherein the pair of gate electrodes (4) are connected to each of the diffusion layers by applying a predetermined voltage. The depletion layer in the vicinity of the layer (5) is separated by a distance at which the depletion layer is in contact with the layer. , the predetermined voltage is applied to the pair of gate electrodes (4)
A semiconductor device having means for performing an enhanced operation. 2. A semiconductor device comprising a logic gate formed by combining the semiconductor device according to claim 1 with a depletion type transistor. 3. The semiconductor device according to claim 2, wherein a mask ROM is formed by said logic gate. 4. An element isolation insulating film (2) is formed on a substrate (1), and a depletion type transistor region is formed on said substrate (1) between said element isolation insulating films (2). Forming an enhancement-type transistor region adjacent to the transistor region; and forming a gate insulating film (3) on the substrate (1) of the depletion-type transistor region and the enhancement-type transistor region; Forming one depletion region (5) in the depletion type transistor region and forming two depletion regions (5) in the enhancement type transistor region; and then, forming the depletion type transistor region and the enhancement type transistor region. Depletion of transistor area Forming a gate electrode (4) on the gate insulating film (3) corresponding to the region (5); and then forming the substrate (1) between the two gate electrodes (4) in the enhancement transistor region. A) forming a source / drain diffusion layer (6) in the substrate (1) so as to be adjacent to the depletion region (5) so as not to be formed in the depletion region (5). .