JPH0485883A - Nonvolatile semiconductor memory device and manufacture thereof - Google Patents

Abstract

PURPOSE:To perform high integration with causing no deterioration in the capacity ratio by forming two storage electrodes on a gate oxidation film between a pair of source.drain band region and forming a control electrode between storage electrodes through an insulating film and forming a word line in order to take contact with a control electrode through a contact hole. CONSTITUTION:Two floating gate 6a are formed on a gate oxidation film 3 between a pair of source/drain diffusion layer 8 band regions, therebetween a control gate 4 is formed through an insulating film 5, thereon the insulating film 5 having a contact hole 9 and a word line 10a is formed to take contact with the control gate 4 therethrough. In this way, since two memory transistors are formed, an integration degree is about doubled as compared with a case where one floating gate exists to a pair of source/drain diffusion layers as in the past so as to allow high integration. 2/3 times Vcc voltage is impressed on the floating gate so that deterioration in the capacity ratio is not caused as compared with the past.

Description

[Detailed Description of the Invention] [Summary] Regarding a nonvolatile semiconductor memory device and a manufacturing method thereof, it is an object of the present invention to provide a nonvolatile semiconductor memory device and a manufacturing method thereof that can be highly integrated without causing deterioration in capacity ratio. For the purpose of an insulating film is formed, and a word line is formed to make contact with the control electrode through the contact hole,
Alternatively, a step of sequentially forming a field oxide film and a gate oxide film on the substrate, a step of forming a strip-shaped control electrode on the field oxide film and the gate oxide film, and a step of forming a first insulating film so as to cover the control electrode. forming a storage electrode on a first insulating film sidewall corresponding to the control electrode sidewall; forming a second insulating film to cover the storage electrode; forming a contact hole through which the control electrode is exposed in the insulating film of the substrate; and forming a word line to make contact with the control electrode through the contact hole; a step of forming a gate oxide film on the gate oxide film, a step of forming a strip-shaped control electrode on the gate oxide film, a step of forming a first insulating film to cover the control electrode, and a step of forming a first insulating film on the sidewall of the control electrode. forming a storage electrode on the corresponding side wall of the first insulating film;
forming a second insulating film to cover the storage electrode; forming a contact hole through which the control electrode is exposed in the first insulating film; and connecting the control electrode to the first insulating film through the contact hole. The method is configured to include the steps of forming a word line to make contact, exposing a control electrode, and oxidizing the control electrode and the substrate to form a field oxide film.

[Industrial application field]

The present invention relates to a nonvolatile semiconductor device such as an EEPROM and a method for manufacturing the same.

In recent years, there has been a demand for nonvolatile semiconductor devices and methods for manufacturing the same that can be highly integrated without causing deterioration in capacitance ratio.

[Conventional technology]

FIG. 7 is a diagram illustrating an example of a conventional nonvolatile semiconductor memory device. In FIG. 7, 31 is a floating gate (storage electrode) made of poly-Si, etc.;
Control gate (control electrode) consisting of etc., 33 is A
! 34 is a drain contact hole, 35 is a field oxide film made of SiO□, etc., 36
is the word line.

High integration of the conventional nonvolatile semiconductor memory device described above has been achieved by scaling each specification, as shown in FIG.
4 diameter and the margin between the drain contact hole 34 and the word line 36 which also serves as the gate electrode, there is a drawback that a limit has been reached.

In order to solve this drawback, it has been proposed to form the source and drain parallel to each other and form the word line perpendicular to the source and drain. Hereinafter, this will be explained in detail with reference to the drawings.

FIG. 8 is a diagram illustrating another example of a conventional nonvolatile semiconductor memory device. In FIG. 8, the same reference numerals as in FIG. 7 indicate the same or corresponding parts.

In the conventional non-volatile semiconductor memory device described above, as shown in FIG. 8, sources and drains are formed in parallel to each other, and word lines 36 are formed perpendicularly to the sources and drains to form drain contact holes. 34 can be substantially reduced compared to the case shown in FIG. 7, which is advantageous in that it is advantageous for high integration.

[Problem to be solved by the invention]

However, even in the conventional non-volatile semiconductor memory device shown in FIG. A problem arises in that the capacitance ratio deteriorates.

Specifically, as shown in FIG. 9, the capacitance ratio here is Co + C, so (2α+L)XW do . However, do: gate oxide film thickness, dl: interelectrode oxide film thickness.

Here, if do==d+, C1ζC0, therefore, only half of the voltage of VCG was applied to the floating gate.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a nonvolatile semiconductor memory device that can be highly integrated without causing deterioration in capacity ratio, and a method for manufacturing the same.

[Means to solve the problem]

In order to achieve the above object, the nonvolatile semiconductor memory device according to the present invention includes two storage electrodes formed on a gate oxide film between a pair of source/drain strip regions, and a control electrode placed between the storage electrodes via an insulating film. is formed, an insulating film having a contact hole is formed on the control electrode, and a word line is formed to make contact with the control electrode via the contact hole.

In order to achieve the above object, the method of manufacturing a non-volatile semiconductor memory device according to the present invention includes the steps of sequentially forming a field oxide film and a gate oxide film on a substrate, and forming control electrodes in a strip shape on the field oxide film and the gate oxide film. a step of forming;
forming a first insulating film to cover the control electrode; forming a storage electrode on the sidewall of the first insulating film corresponding to the sidewall of the control electrode; and forming a second insulating film to cover the storage electrode. forming an insulating film, forming a contact hole through which the control electrode is exposed in the first insulating film, and forming a word line to make contact with the control electrode through the contact hole. It includes a process.

In order to achieve the above object, the method for manufacturing a nonvolatile semiconductor memory device according to the present invention includes the steps of forming a gate oxide film on a substrate, forming a strip-shaped control electrode on the gate oxide film, and forming a control electrode on the gate oxide film. a step of forming a first insulating film so as to cover the control electrode, a step of forming a storage electrode on the side wall of the first insulating film corresponding to the side wall of the control electrode, and a step of forming a second insulating film so as to cover the storage electrode. forming a contact hole in the first insulating film through which the control electrode is exposed;
Through the contact hole! This step includes forming a word line so that IJ# is in contact with the pole, exposing a control electrode, and oxidizing the control electrode and the substrate to form a field oxide film.

[Effect]

In the present invention, as shown in FIG. 1, two floating gates 6a are formed for a pair of source/drain diffusion layers 8 to form two memory transistors. The degree of integration is approximately twice that of the case where one floating gate is provided for a pair of source/drain diffusion layers, and high integration can be achieved.

In addition, whereas conventionally only half of the VCG voltage was applied to the floating gate, in the present invention, 2/3 times the VCG voltage is applied to the floating gate, so that the capacitance ratio does not deteriorate more than in the past. I can do it.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

1 to 5 are diagrams for explaining an embodiment of a nonvolatile semiconductor memory device and a method for manufacturing the same according to the present invention, and FIG.
The figure is a main diagram showing the structure of one embodiment, FIG. 2 is a cell array diagram of one embodiment, FIG. 3 is a circuit block diagram of one embodiment, FIG. 4 is a supplementary diagram for explaining the operation of one embodiment, and FIG. The figure is a diagram illustrating a manufacturing method of one embodiment. Note that FIG. 1(a) is a plan view of the device, and FIG. 1(b) is the Xl-X shown in FIG. 1(a).
A cross-sectional view in two directions, FIG. 1(C) is the Y shown in FIG. 1(a).
FIG. 2 is a cross-sectional view taken in the l-Y2 direction. In these figures, 1
is a substrate made of Si or the like, 2 is a field oxide film made of SiO□ or the like, 3 is a gate oxide film made of 5i02 or the like, 4
is a control gate (control a@pole) made of poly-Si, etc.
, 5 is a silicon oxide film made of SiO□ etc., 6 is a polysilicon film, 6a is a floating gate (storage electrode) made of polySi etc., 7 is a silicon oxide film made of 5iOz etc., 8 is a source/drain diffusion layer, 9 is a contact hole formed in the silicon oxide film 5; 10 is a polysilicon film serving as a word line; 10a is a word line made of poly-Si or the like; 11 is a silicon oxide film made of Sing or the like; 12
13 is an interlayer insulating film made of PSG or the like, 13 is a bit line made of A2 or the like, and 14 is a cover film made of PSG or 5i=N4 or the like.

Next, the manufacturing method will be explained.

First, as shown in FIG. 5(a), a substrate 1 (not shown) is oxidized by LOGO3 to form a field oxide film 2 having a thickness of, for example, 6000, which will become a transistor insulating region, and After oxidizing the substrate 1 by, for example, thermal oxidation to form a gate oxide film 3 having a film thickness of, for example, 200, for example, boron, 50 keV
, lXIO"Cl11-" ion implantation introduces boron into the substrate l channel portion through the gate oxide film 3.

Next, as shown in FIG. 5(b), poly-Si is deposited on the entire surface by, for example, the CVD method, and the film thickness is, for example, 1000 to 400.
After forming a polysilicon film of 1,000 people, for example, RIE
The polysilicon film is selectively etched to form a band-shaped control gate 4.

Next, as shown in FIG. 5(C), the control gate 4 is oxidized by, for example, thermal oxidation, and the film thickness is reduced to, for example, 200 mm.
A silicon oxide film 5 of 400 layers is formed.

Next, as shown in FIG. 5(d), poly-Si is deposited on the entire surface by, for example, the CVD method, and the film thickness is, for example, 1000 to 400.
000 polysilicon film 6 is formed.

Next, as shown in FIG. 5(e), the polysilicon film 6 is etched, for example, by one step, and a floating gate (6a) consisting of a sidewall conductive film is formed on the sidewall of the silicon oxide film 5 corresponding to the sidewall of the control gate 4. form.

Next, as shown in FIG. 5(f), the floating gate 6a is oxidized by, for example, thermal oxidation to form a silicon oxide film 7 having a thickness of, for example, 200 to 400 layers on the floating gate 6a.

Next, as shown in FIGS. 5(g) and 5(h), ions of, for example, arsenic, 100 keV, I Source/drain diffusion layer 8 is formed by introducing arsenic into.

Next, as shown in FIG. 5(i), the silicon oxide film 5 on the control gate 4 is selectively etched by, for example, RIE to form a contact hole 9, and the control gate 4 is inserted into the contact hole 9. After the exposure, poly-Si is deposited on the entire surface by, for example, the CVD method so as to make contact with the control gate 4 in the contact hole 9 to a film thickness of, for example, 1000 to 4000.
A polysilicon film 10 that will become a human word line is formed.

Next, as shown in FIG. 5(j), a polysilicon film 10 corresponding to the field oxide film 2 is formed by, for example, RIE.
Control gate 4 and floating gate 1-6a
is selectively etched to form word line 10a and to expose field oxide film 2.

Then, the word line 10a is oxidized by, for example, thermal oxidation to form a silicon oxide film 11 having a thickness of, for example, 200.
For example, a PSG film is deposited on a silicon oxide film 11 by a CVD method to form a glabellar insulating film 12 having a film thickness of, for example, 1 μm, a contact hole is formed in the glabellar insulating film 12, and a contact hole is formed from /l by, for example, sputtering and tE. bit line 13
After forming PSG or 5
A cover film 14 having a thickness of, for example, 1 μm is formed by depositing i3Ns.
By forming this, a nonvolatile semiconductor memory device as shown in FIG. 5(k) can be obtained.

Next, the principle of operation will be explained using FIGS. 3 and 4. Here, a biasing method for reading out the cell (■) shown in FIG. 3 will be explained. Note that FIG. 3 is a circuit block diagram of the cell array shown in FIG. 2.

First, the word line W2 is set to High and the bit line B3 is selected as the ground (GND).

All of the bit lines to the right of the B2 bit line are floated or set to High, and all of the bit lines to the left of the B4 bit line are grounded. The memory transistor (2) is biased as shown in FIG. In this state, regardless of whether the memory transistor (2) is in the "0" state or the "1" state, that is, whether electrons are present or not, it has almost no effect on the drain current that senses the memory transistor (2). This is because the floating gate of the memory transistor (2) is located on the drain side of a MOS transistor, so it does not receive much load. Conversely, the floating gate of the memory transistor (2) is located on the source side of a MOS transistor, and this has a large effect on the drain current. Therefore, when the drain current of the transistor shown in FIG. 4 is sensed, the state of the memory transistor (2) is sensed naturally. Conversely, during writing, bit line 83 is selected as High.

The bit line to the right of the B2 bit line is grounded. Due to this bias condition, hot electrons are injected into the floating gate from the vicinity of the high electrode.

That is, in the above embodiment, two floating gates 6a are formed on the gate oxide film 3 between the pair of source/drain diffusion layer 8 band regions, and the floating gates 6a are
A control gate 4 is formed with an insulating film 5 in between,
An insulating film 5 having a contact hole 9 is formed on the control gate 4, and a word line 10 is formed so as to make contact with the control gate 4 through the contact hole 9.
I am trying to form a. In this way, the floating gate 6 is connected to the pair of source/drain diffusion layers 8.
Since two memory transistors are formed by forming two a, the conventional pair of sources/
The degree of integration is approximately twice that of the case where there is one floating gate for each drain diffusion layer, and high integration can be achieved. Furthermore, while only half of the conventional VCG voltage was applied to the floating gate, in the above embodiment, V((.

Since 2/3 times the voltage is applied to the floating gate, it is possible to prevent the capacitance ratio from deteriorating more than in the conventional case. Specifically, the capacitance ratio here is C, +C, as shown in FIG.

Therefore, assuming that the oxide film thickness does not change, the capacitance ratio becomes the area ratio, and the area of /3x will be applied to the floating gate.

In the above embodiment, a case has been described in which the field oxide film 2, which becomes the transistor insulating region, is formed before forming the gate oxide film 3. However, the present invention is not limited to this, and the word line 10a It may be formed after the formation. Hereinafter, this will be explained in detail with reference to the drawings.

FIG. 6 is a diagram illustrating another embodiment of the method for manufacturing a nonvolatile semiconductor memory device according to the present invention.
The same reference numerals as in FIG. 5 indicate the same or corresponding parts, and 21 is a silicon nitride film made of 5ixNa or the like.

Next, the manufacturing method will be explained.

First, as shown in FIGS. 6(a) to 6(C), the substrate 1 is oxidized, for example, by thermal oxidation, so that the film thickness is, for example, 200 to 400.
After forming the gate oxide film 3, for example, boron, 50%
Boron is introduced into the channel portion of the substrate 1 through the gate oxide film 3 by ion implantation of keν, I After forming a polysilicon film of ~4,000 layers and selectively etching the polysilicon film by, for example, RIE to form a belt-shaped control gate 4 on the gate oxide film 3, the control gate 4 is oxidized by, for example, thermal oxidation. If the film thickness is, for example, 200 to 4
00 silicon oxide film 5 is formed.

Next, as shown in FIGS. 6(d) to 6(f), poly-Si is deposited over the entire surface by, for example, the CVD method to form a polysilicon film having a film K of, for example, 1,000 to 4,000 layers, and then by, for example, RIE. A floating gate 6a is formed on the side wall of the silicon oxide film 5 corresponding to the side wall of the control gate 4 by etching back the polysilicon film, and the floating gate 6a is oxidized by, for example, thermal oxidation to form a film on the floating gate 6a with a film thickness of, for example, 200 mm. After forming the silicon oxide film 7 of 400 layers, for example, arsenic, 100 keV
, 1×10I5■-2 ions are implanted into the substrate 1 through the gate oxide film 3 using the silicon oxide film 5.7 as a mask.
A source/drain diffusion layer 8 is formed by introducing arsenic into the structure. Then, the control gate 4 is removed by RIE, for example.
The upper silicon oxide film 5 is selectively etched to form a contact hole 9.
A polysilicon film 10 having a film thickness of, for example, 1,000 to 4,000 is formed by exposing the control gate 4 in the contact hole 9 and depositing poly-Si on the entire surface so as to make contact with the control gate 4 in the contact hole 9 by, for example, the CVD method. After oxidizing the polysilicon film 10 by, for example, thermal oxidation to form a silicon oxide film 11 having a thickness of, for example, 200, Si 2 N4 is applied to the entire surface by, for example, CVD.
A silicon nitride film 2 with a film thickness of, for example, 2000 is deposited.
form 1.

Next, as shown in FIGS. 6(g) to (i), for example, RI
Silicon nitride film 21, silicon oxide film 11, polysilicon film 10, and silicon oxide film 5 are selectively etched using E to form word line 10a and expose control gate 4.

Next, as shown in Figure 6 N) to (I2),
By using the silicon nitride film 21 as a mask, the control gate 4 and the substrate 1 are selectively oxidized to a film thickness of, for example, 2.
A field oxide film 2 of 000 to 5000 layers is formed.

Then, the silicon nitride film 21 used as a mask is removed, and PSG is deposited on the entire surface using, for example, a CVD method to form a glabellar insulating film 12 with a film thickness of, for example, 1 μm, and a contact hole is formed in the glabellar insulating film 12. , for example, by sputtering and RIE. After forming the bit line 13 consisting of the following, 513Na is deposited on the entire surface by, for example, the CVD method to form the cover film 14 having a thickness of, for example, 1 μm, as shown in FIGS. 6(m) to (0). A nonvolatile semiconductor memory device can be obtained.

〔Effect of the invention〕

According to the present invention, there is an effect that high integration can be achieved without causing deterioration of the capacitance ratio.

[Brief explanation of the drawing]

1 to 5 are diagrams illustrating an embodiment of a nonvolatile semiconductor memory device and its manufacturing method according to the present invention, FIG. 1 is a main diagram showing the structure of one embodiment, and FIG. 2 is an implementation example. FIG. 3 is a circuit block diagram of one embodiment; FIG. 4 is a corrected diagram for explaining the operation of one embodiment; FIG. 5 is a diagram explaining the manufacturing method of one embodiment; FIG. 6 is a diagram of another embodiment. 7 is a diagram illustrating the manufacturing method of the embodiment, FIG. 7 is a diagram of a cell array of an example of the conventional example, FIG. 8 is a diagram of a cell array of another example of the conventional example, and FIG. 9 is a diagram illustrating the problems of the conventional example. be. 5...Silicon oxide film, 6...Polysilicon film, 6a...Floating gate, 7...
・Silicon oxide film, 8...Source/drain diffusion layer, 9...
・Contact hole, 10...Polysilicon film, 10a...Word line, 11...Silicon oxide film, 12...Interlayer insulating film, 13... ...Bit line, 14...Cover film. DESCRIPTION OF SYMBOLS 1...Substrate, 2...Field oxide film, 3...Gate oxide film, 4...Control case, Manufacturing method of the embodiment shown in FIG. Figure 5 to explain the polysilicon waist Figure 6 to explain the manufacturing method of one embodiment Figure to explain the manufacturing method to another embodiment Figure 6 to explain the manufacturing method to another embodiment Figure 7: Cell array diagram of conventional example →Cell array diagram of another example of conventional example Figure 9J8 Figure 9: Diagram explaining conventional example J

Claims (1)

[Claims] 1. Two storage electrodes (6a) are formed on a gate oxide film (3) between a pair of source/drain (8) strip regions, and an insulating film is formed between the storage electrodes (6a). A control electrode (4) is formed through the control electrode (5), an insulating film (5) having a contact hole (9) is formed on the control electrode (4), and a control electrode (4) is formed through the contact hole (9). A nonvolatile semiconductor memory device characterized in that a word line (10a) is formed so as to make contact with an electrode (4). 2. The step of sequentially forming a field oxide film (2) and a gate oxide film (3) on the substrate (1), and forming a control electrode (in a strip shape) on the field oxide film (2) and the gate oxide film (3). 4), a step of forming a first insulating film (5) to cover the control electrode (4), and a first insulating film (5) corresponding to the sidewall of the control electrode (4). forming a storage electrode (6a) on a side wall; forming a second insulating film (7) to cover the storage electrode (6a); and forming a control electrode on the first insulating film (5). (4) to expose the contact hole (9), and forming a word line (10a) so as to make contact with the control electrode (4) through the contact hole (9). A method of manufacturing a nonvolatile semiconductor memory device, comprising: 3. Forming a gate oxide film (3) on the substrate (1); Forming a strip-shaped control electrode (4) on the gate oxide film (3); Covering the control electrode (4). a step of forming a first insulating film (5) as shown in FIG.
forming a storage electrode (6a) on a side wall; forming a second insulating film (7) to cover the storage electrode (6a); and forming a control electrode on the first insulating film (5). (4) to expose the contact hole (9), forming a word line (10a) so as to make contact with the control electrode (4) through the contact hole (9), and controlling the control electrode (4). Manufacturing a non-volatile semiconductor device, comprising: exposing an electrode (4); and oxidizing the control electrode (4) and the substrate (1) to form a field oxide film (2). Method.