JPH0548113A - Nonvolatile semiconductor storage device and its manufacture - Google Patents

Nonvolatile semiconductor storage device and its manufacture

Info

Publication number
JPH0548113A
JPH0548113A JP3204190A JP20419091A JPH0548113A JP H0548113 A JPH0548113 A JP H0548113A JP 3204190 A JP3204190 A JP 3204190A JP 20419091 A JP20419091 A JP 20419091A JP H0548113 A JPH0548113 A JP H0548113A
Authority
JP
Japan
Prior art keywords
gate electrode
film
silicon oxide
semiconductor substrate
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3204190A
Other languages
Japanese (ja)
Inventor
Michio Morita
倫生 森田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP3204190A priority Critical patent/JPH0548113A/en
Publication of JPH0548113A publication Critical patent/JPH0548113A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To provide a nonvolatile storage device which can be reduced in size and increased in degree of integration by reducing its cell area and the manufacturing method of the storage device. CONSTITUTION:This nonvolatile storage device has such a gate structure that a thin silicon oxide film 12 is formed as a tunneling medium on a channel area between a source area and drain area 19 provided on a semiconductor substrate 11 and a silicon nitride film 13 and the first gate electrode 14 are formed on the film 12. The gate structure contains side-wall insulating films 15 formed on the side wall of the structure and the second gate electrodes 17 formed adjacent to the films 15 with gate insulating films 16 in between on the semiconductor substrate 11.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はMNOS(ゲート電極−
窒化シリコン膜−酸化シリコン膜−半導体基板)型の電
界効果トランジスタからなる不揮発性半導体記憶装置お
よびその製造方法に関する。
The present invention relates to MNOS (gate electrode).
The present invention relates to a nonvolatile semiconductor memory device including a silicon nitride film-silicon oxide film-semiconductor substrate) type field effect transistor and a method for manufacturing the same.

【0002】[0002]

【従来の技術】従来、電気的に書き換え可能な不揮発性
メモリの1つとして、MNOS型不揮発性半導体記憶装
置がよく知られている。MNOS型不揮発性半導体記憶
装置は、ゲート電極−半導体基板間に電圧を加え、半導
体基板から電子あるいは正孔をトンネリング媒体となり
うる薄い酸化シリコン膜をトンネリングさせ、窒化膜に
トラップさせることにより、しきい値電圧を変化させ、
そのしきい値電圧の変化によって記憶素子として動作さ
せることを原理としている。
2. Description of the Related Art Conventionally, an MNOS type nonvolatile semiconductor memory device is well known as one of electrically rewritable nonvolatile memories. The MNOS type non-volatile semiconductor memory device applies a voltage between a gate electrode and a semiconductor substrate to tunnel electrons or holes from the semiconductor substrate into a thin silicon oxide film that can serve as a tunneling medium and trap the electrons in a nitride film. Change the value voltage,
The principle is to operate as a memory element by the change of the threshold voltage.

【0003】以下従来のMNOS型不揮発性半導体記憶
装置について説明する。図3は従来のMNOS型不揮発
性半導体記憶装置の断面図である。図3において、1は
P型半導体基板、2はトンネリング媒体となる薄い酸化
シリコン膜、3は窒化シリコン膜、4は第1ゲート電
極、5は酸化シリコン膜、6は第2ゲート電極、7は比
較的浅いN型拡散層、8はソース領域およびドレイン領
域となるN型拡散層である。また、図3において、右側
のMOSトランジスタをMNOSトランジスタ、左側の
MOSトランジスタを選択トランジスタと呼ぶことにす
る。
A conventional MNOS type nonvolatile semiconductor memory device will be described below. FIG. 3 is a cross-sectional view of a conventional MNOS type nonvolatile semiconductor memory device. In FIG. 3, 1 is a P-type semiconductor substrate, 2 is a thin silicon oxide film serving as a tunneling medium, 3 is a silicon nitride film, 4 is a first gate electrode, 5 is a silicon oxide film, 6 is a second gate electrode, and 7 is A relatively shallow N-type diffusion layer, and 8 is an N-type diffusion layer to be a source region and a drain region. Further, in FIG. 3, the MOS transistor on the right side is called an MNOS transistor, and the MOS transistor on the left side is called a select transistor.

【0004】通常、MNOSトランジスタに記憶させた
情報を読み出す場合、MNOSトランジスタの誤書き込
みを防止するために、どうしても選択トランジスタが必
要となる。したがって、不揮発性メモリとして動作する
ためには、MNOSトランジスタと選択トランジスタの
2つのMOSトランジスタ構成が必要となっていた。
Normally, when reading the information stored in the MNOS transistor, a selection transistor is inevitably necessary in order to prevent erroneous writing in the MNOS transistor. Therefore, in order to operate as a non-volatile memory, two MOS transistor configurations of the MNOS transistor and the selection transistor have been required.

【0005】[0005]

【発明が解決しようとする課題】しかしながら上記の従
来の構成では、近年半導体メモリの大容量化が進む中で
MNOS型不揮発性半導体記憶装置においても高集積化
の要求が高まりつつあり、MNOSトランジスタと選択
トランジスタの2つのトランジスタを構成しなければな
らず、そのためセル面積が大きくなり、微細化、高集積
化を図ることができないという課題を有していた。
However, in the above-mentioned conventional configuration, the demand for higher integration is increasing in the MNOS type nonvolatile semiconductor memory device as the capacity of the semiconductor memory is increasing in recent years. Two transistors, which are the selection transistors, have to be formed, which causes a problem that the cell area becomes large and miniaturization and high integration cannot be achieved.

【0006】本発明は上記従来の課題を解決するもの
で、セル面積を縮小し、微細化、高集積化を可能にする
ことができる不揮発性半導体記憶装置およびその製造方
法を提供することを目的とする。
The present invention solves the above conventional problems, and an object of the present invention is to provide a nonvolatile semiconductor memory device capable of reducing the cell area, enabling miniaturization and high integration, and a method for manufacturing the same. And

【0007】[0007]

【課題を解決するための手段】この目的を達成するため
に本発明の不揮発性半導体記憶装置は、半導体基板に設
けられたソース領域およびドレイン領域に挟まれたチャ
ネル領域の上に、トンネリング媒体となる薄い酸化シリ
コン膜を備え、この薄い酸化シリコン膜の上に少なくと
も1層の窒化シリコン膜よりなる第1の絶縁膜を備え、
第1の絶縁膜の上に第1ゲート電極を備えたゲート構造
を有するMNOS(ゲート電極−窒化シリコン膜−酸化
シリコン膜−半導体基板)構造の不揮発性半導体記憶装
置において、ゲート構造の側壁に形成された第2の絶縁
膜と第2の絶縁膜に接し半導体基板の上に形成されたゲ
ート絶縁膜とを介して設けられた第2ゲート電極からな
る構成を有している。
In order to achieve this object, a nonvolatile semiconductor memory device of the present invention comprises a tunneling medium and a tunneling medium on a channel region sandwiched by a source region and a drain region provided on a semiconductor substrate. And a first insulating film made of at least one layer of a silicon nitride film on the thin silicon oxide film,
Formed on a sidewall of a gate structure in a nonvolatile semiconductor memory device having a MNOS (gate electrode-silicon nitride film-silicon oxide film-semiconductor substrate) structure having a gate structure having a first gate electrode on a first insulating film. The second gate electrode is provided via the formed second insulating film and the gate insulating film formed on the semiconductor substrate in contact with the second insulating film.

【0008】また本発明の不揮発性半導体記憶装置の製
造方法は、一導電型半導体基板の上に薄い酸化シリコン
膜を形成し、薄い酸化シリコン膜の上に窒化シリコン膜
を形成し、窒化シリコン膜の上に第1の多結晶シリコン
膜よりなる第1ゲート電極を形成した後に酸化処理を施
し、半導体基板の上および前記第1ゲート電極の上に酸
化シリコン膜を形成する工程と、酸化シリコン膜の上に
第2の多結晶シリコン膜を全面に堆積し異方性エッチン
グを施すことにより、第1ゲート電極の側壁に第2ゲー
ト電極を形成する工程と、第1ゲート電極および第2ゲ
ート電極をマスクとしてソース領域およびドレイン領域
を形成する工程からなる構成を有している。
According to the method of manufacturing a nonvolatile semiconductor memory device of the present invention, a thin silicon oxide film is formed on a one conductivity type semiconductor substrate, a silicon nitride film is formed on the thin silicon oxide film, and a silicon nitride film is formed. Forming a first gate electrode made of a first polycrystalline silicon film on the silicon oxide film, and then performing an oxidation treatment to form a silicon oxide film on the semiconductor substrate and on the first gate electrode; Forming a second gate electrode on the side wall of the first gate electrode by depositing a second polycrystalline silicon film on the entire surface and performing anisotropic etching, and the first gate electrode and the second gate electrode. Is used as a mask to form a source region and a drain region.

【0009】[0009]

【作用】この構成によって、MNOSトランジスタのゲ
ート電極として用いる第1ゲート電極の側壁に選択トラ
ンジスタのゲート電極である第2ゲート電極を形成して
いるため、第2ゲート電極を自己整合的に製造すること
ができかつMNOS型不揮発性半導体記憶装置の微細
化、高集積化の著しい向上を図ることが可能となる。
With this structure, since the second gate electrode, which is the gate electrode of the select transistor, is formed on the sidewall of the first gate electrode used as the gate electrode of the MNOS transistor, the second gate electrode is manufactured in a self-aligned manner. In addition, it is possible to make the MNOS nonvolatile semiconductor memory device finer and highly integrated.

【0010】[0010]

【実施例】以下、本発明の一実施例について、図面を参
照しながら説明する。図1は本発明の一実施例における
MNOS型不揮発性半導体記憶装置の断面図である。図
1において、11はP型半導体基板、12はトンネリン
グ媒体となる薄い酸化シリコン膜、13は窒化シリコン
膜、14は第1ゲート電極、15は側壁絶縁膜、16は
ゲート絶縁膜、17は第2ゲート電極、18は比較的浅
いN型拡散層、19はソース領域およびドレイン領域と
なるN型拡散層である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of a MNOS type nonvolatile semiconductor memory device according to an embodiment of the present invention. In FIG. 1, 11 is a P-type semiconductor substrate, 12 is a thin silicon oxide film serving as a tunneling medium, 13 is a silicon nitride film, 14 is a first gate electrode, 15 is a sidewall insulating film, 16 is a gate insulating film, and 17 is a first insulating film. 2 is a gate electrode, 18 is a relatively shallow N-type diffusion layer, and 19 is an N-type diffusion layer serving as a source region and a drain region.

【0011】P型半導体基板11に比較的浅いN型拡散
層18、ソース領域およびドレイン領域19が形成さ
れ、比較的浅いN型拡散層18に挟まれた領域の上にト
ンネリング媒体となる薄い酸化シリコン膜12、窒化シ
リコン膜13および第1ゲート電極14が順次積層さ
れ、第1ゲート構造を形成している。この第1ゲート構
造の側壁に側壁絶縁膜15が形成されている。この側壁
絶縁膜15は第1ゲート構造の両側のP型半導体基板1
1の上に形成されたゲート絶縁膜16に連なっている。
また第1ゲート構造の側壁に、側壁絶縁膜15およびゲ
ート絶縁膜16を介して第2ゲート電極17が形成され
ている。
A relatively shallow N-type diffusion layer 18, a source region and a drain region 19 are formed on the P-type semiconductor substrate 11, and a thin oxide serving as a tunneling medium is formed on the region sandwiched by the relatively shallow N-type diffusion layer 18. The silicon film 12, the silicon nitride film 13, and the first gate electrode 14 are sequentially stacked to form a first gate structure. A sidewall insulating film 15 is formed on the sidewall of the first gate structure. The sidewall insulating film 15 is formed on the P-type semiconductor substrate 1 on both sides of the first gate structure.
1 and the gate insulating film 16 formed on the first insulating film 16.
Further, the second gate electrode 17 is formed on the sidewall of the first gate structure with the sidewall insulating film 15 and the gate insulating film 16 interposed therebetween.

【0012】次に本発明のMNOS型半導体記憶装置の
製造方法について説明する。図2(a)〜(d)は本発
明の一実施例におけるMNOS型半導体記憶装置の工程
断面図である。まず図2(a)に示すように、P型半導
体基板11の上にトンネリング媒体となる2nm程度の薄
い酸化シリコン膜12を酸素雰囲気中での酸化により形
成し、次にジクロルシランとアンモニアの化学反応に基
づく気相成長法により窒化シリコン膜13を約20nm形
成し、次に第1ゲート電極14となる全面にりんを添加
した多結晶シリコン膜を約300nm堆積する。次にフォ
トレジストを用いた公知のエッチング技術により、第1
ゲート電極14、窒化シリコン膜13および薄い酸化シ
リコン膜12をエッチングし第1ゲート構造を形成す
る。次に図2(b)に示すように、酸素および水素雰囲
気中での処理により側壁絶縁膜15および20nm程度の
ゲート絶縁膜16を同時に形成し、次に第2ゲート電極
17となる全面にりんを添加した多結晶シリコン膜を約
200nm堆積する。次に図2(c)に示すように、第1
ゲート構造の側壁に第2ゲート電極17となる多結晶シ
リコン膜の一部が残るように、公知の異方性エッチング
技術により多結晶シリコン膜を除去して、第2ゲート構
造を形成する。次に図2(d)に示すように、第1ゲー
ト構造および第2ゲート構造をマスクとして、りんイオ
ンを半導体基板11に30keV、1×1013cm-2の条件
で打ち込み、比較的浅いN型拡散層18を形成する。次
にフォトレジストをマスクとして砒素イオンを半導体基
板11に40keV、4×1015cm-2の条件で打ち込み、
ソース領域およびドレイン領域19を形成する。その
後、図示はしていないが、層間絶縁膜の堆積、コンタク
トホールの開孔、アルミニウム配線層の堆積およびパタ
ーンニング、保護層の堆積などの諸工程を経てMNOS
型不揮発性半導体記憶装置が完成する。
Next, a method of manufacturing the MNOS type semiconductor memory device of the present invention will be described. 2A to 2D are process cross-sectional views of the MNOS type semiconductor memory device in one embodiment of the present invention. First, as shown in FIG. 2A, a thin silicon oxide film 12 of about 2 nm that serves as a tunneling medium is formed on a P-type semiconductor substrate 11 by oxidation in an oxygen atmosphere, and then a chemical reaction of dichlorosilane and ammonia is performed. A silicon nitride film 13 is formed to a thickness of about 20 nm by a vapor phase growth method based on the above, and then a polycrystalline silicon film to which phosphorus is added is deposited to a thickness of about 300 nm on the entire surface to be the first gate electrode 14. Next, by a known etching technique using a photoresist, the first
The gate electrode 14, the silicon nitride film 13 and the thin silicon oxide film 12 are etched to form a first gate structure. Next, as shown in FIG. 2B, a sidewall insulating film 15 and a gate insulating film 16 having a thickness of about 20 nm are simultaneously formed by a treatment in an oxygen and hydrogen atmosphere, and then a phosphorus film is formed on the entire surface to be the second gate electrode 17. A polycrystalline silicon film added with about 200 nm is deposited. Next, as shown in FIG. 2C, the first
The polycrystalline silicon film is removed by a known anisotropic etching technique so that a part of the polycrystalline silicon film to be the second gate electrode 17 remains on the side wall of the gate structure to form the second gate structure. Next, as shown in FIG. 2D, using the first gate structure and the second gate structure as a mask, phosphorus ions are implanted into the semiconductor substrate 11 under the conditions of 30 keV and 1 × 10 13 cm -2 , and a relatively shallow N The mold diffusion layer 18 is formed. Next, using the photoresist as a mask, arsenic ions are implanted into the semiconductor substrate 11 under the conditions of 40 keV and 4 × 10 15 cm -2 ,
The source region and the drain region 19 are formed. Thereafter, although not shown, the MNOS is subjected to various steps such as deposition of an interlayer insulating film, opening of contact holes, deposition and patterning of an aluminum wiring layer, and deposition of a protective layer.
Type nonvolatile semiconductor memory device is completed.

【0013】以上のように構成された本実施例のMNO
S型不揮発性半導体記憶装置においては、MNOSトラ
ンジスタの第1ゲート構造の側壁に第2ゲート構造を形
成するようにしたため、第2ゲート電極を自己整合的に
製造することができ、微細化、高集積化を図ることがで
きる。
The MNO of this embodiment constructed as described above
In the S-type non-volatile semiconductor memory device, since the second gate structure is formed on the side wall of the first gate structure of the MNOS transistor, the second gate electrode can be manufactured in a self-aligned manner, and it can be miniaturized and high in size. Integration can be achieved.

【0014】なお上記実施例では、NチャネルMOSト
ランジスタの場合について説明したが、PチャネルMO
Sトランジスタでも良い。またゲート絶縁膜として酸化
シリコン膜、窒化シリコン膜の2層構造を用いたが、窒
化シリコン膜の上を酸化して酸化シリコン膜、窒化シリ
コン膜、酸化シリコン膜の3層構造としても良い。
In the above embodiment, the case of the N channel MOS transistor is explained, but the P channel MO transistor is used.
It may be an S transistor. Although the two-layer structure of the silicon oxide film and the silicon nitride film is used as the gate insulating film, a three-layer structure of the silicon oxide film, the silicon nitride film, and the silicon oxide film may be formed by oxidizing the top of the silicon nitride film.

【0015】[0015]

【発明の効果】以上のように本発明は、MNOSトラン
ジスタの側壁に選択トランジスタを設けることにより、
容易にメモリセルの微細化、高集積化を図ることができ
る優れた不揮発性半導体記憶装置およびその製造方法を
実現できるものである。
As described above, according to the present invention, by providing the selection transistor on the side wall of the MNOS transistor,
It is possible to realize an excellent non-volatile semiconductor memory device that can easily achieve miniaturization and high integration of memory cells and a manufacturing method thereof.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例におけるMNOS型不揮発性
半導体記憶装置の断面図
FIG. 1 is a cross-sectional view of a MNOS type nonvolatile semiconductor memory device according to an embodiment of the present invention.

【図2】(a)〜(d)は本発明の一実施例におけるM
NOS型半導体記憶装置の工程断面図
2 (a) to (d) are M in one embodiment of the present invention.
Process sectional view of the NOS type semiconductor memory device

【図3】従来のMNOS型不揮発性半導体記憶装置の断
面図
FIG. 3 is a cross-sectional view of a conventional MNOS type nonvolatile semiconductor memory device.

【符号の説明】[Explanation of symbols]

11 P型半導体基板(半導体基板) 12 薄い酸化シリコン膜 13 窒化シリコン膜(第1の絶縁膜) 14 第1ゲート電極 15 側壁絶縁膜(第2の絶縁膜) 16 ゲート絶縁膜 17 第2ゲート電極 19 N型拡散層(ソース領域およびドレイン領域) 11 P-type semiconductor substrate (semiconductor substrate) 12 Thin silicon oxide film 13 Silicon nitride film (first insulating film) 14 First gate electrode 15 Side wall insulating film (second insulating film) 16 Gate insulating film 17 Second gate electrode 19 N-type diffusion layer (source region and drain region)

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板に設けられたソース領域およ
びドレイン領域に挟まれたチャネル領域の上にトンネリ
ング媒体となる薄い酸化シリコン膜を備え、前記薄い酸
化シリコン膜の上に窒化シリコン膜よりなる第1の絶縁
膜を備え、前記第1の絶縁膜の上に第1ゲート電極を備
えたゲート構造を有するMNOS(ゲート電極−窒化シ
リコン膜−酸化シリコン膜−半導体基板)構造の不揮発
性半導体記憶装置において、前記ゲート構造の側壁に形
成された第2の絶縁膜と前記第2の絶縁膜に接し半導体
基板の上に形成されたゲート絶縁膜とを介して設けられ
た第2ゲート電極を有する不揮発性半導体記憶装置。
1. A thin silicon oxide film serving as a tunneling medium is provided on a channel region sandwiched by a source region and a drain region provided on a semiconductor substrate, and a thin silicon nitride film is formed on the thin silicon oxide film. Non-volatile semiconductor memory device having an MNOS (gate electrode-silicon nitride film-silicon oxide film-semiconductor substrate) structure having a gate structure having a first gate electrode on the first insulating film. A nonvolatile memory having a second gate electrode provided via a second insulating film formed on a sidewall of the gate structure and a gate insulating film formed on the semiconductor substrate in contact with the second insulating film. Semiconductor memory device.
【請求項2】 一導電型半導体基板の上に薄い酸化シリ
コン膜を形成し、前記薄い酸化シリコン膜の上に窒化シ
リコン膜を形成し、前記窒化シリコン膜の上に第1の多
結晶シリコン膜よりなる第1ゲート電極を形成した後に
酸化処理を施し、前記半導体基板の上および前記第1ゲ
ート電極の上に酸化シリコン膜を形成する工程と、前記
酸化シリコン膜の上に第2の多結晶シリコン膜を全面に
堆積し異方性エッチングを施すことにより、前記第1ゲ
ート電極の側壁に第2ゲート電極を形成する工程と、前
記第1ゲート電極および前記第2ゲート電極をマスクと
してソース領域およびドレイン領域を形成する工程とを
有する不揮発性半導体記憶装置の製造方法。
2. A thin silicon oxide film is formed on a semiconductor substrate of one conductivity type, a silicon nitride film is formed on the thin silicon oxide film, and a first polycrystalline silicon film is formed on the silicon nitride film. Forming a first gate electrode made of, and then performing an oxidation treatment to form a silicon oxide film on the semiconductor substrate and on the first gate electrode; and a second polycrystalline film on the silicon oxide film. A step of forming a second gate electrode on the sidewall of the first gate electrode by depositing a silicon film on the entire surface and performing anisotropic etching; and a source region using the first gate electrode and the second gate electrode as a mask. And a step of forming a drain region, a method of manufacturing a nonvolatile semiconductor memory device.
JP3204190A 1991-08-14 1991-08-14 Nonvolatile semiconductor storage device and its manufacture Pending JPH0548113A (en)

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Application Number Priority Date Filing Date Title
JP3204190A JPH0548113A (en) 1991-08-14 1991-08-14 Nonvolatile semiconductor storage device and its manufacture

Publications (1)

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JPH0548113A true JPH0548113A (en) 1993-02-26

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