JPH01165162A - Manufacture of semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce the lead time significantly by a method wherein, after 2nd insulating films are formed on the side walls of gate electrodes, the insulating films on the side walls of the specific gate electrode are removed at least selectively and impurity ions are implanted into a semiconductor substrate. CONSTITUTION:Element isolation insulating films 2 and gate insulating films 3 are formed on a substrate 1 and, after polycrystalline Si is deposited and etched to form gate electrodes 6, first insulating films 8a are formed. Then impurity ions are implanted into source and drain regions to form low concentration impurity regions 7. Then SiO2 is deposited over the whole surface and etched back to form second insulating films 8b on the side walls of the gate electrodes 6. Then peripheral circuit parts are covered with resist 4 and the second insulating films 8b on the side walls of the gate electrodes 6 of a memory cell part are selectively removed by wet-etching. After resist 4 is applied and patterned, punch through is produced in the source and drain regions by ion implantation and a thermal oxidation.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention is directed to an LDD (Lightly Doped
A semiconductor memory device that can significantly reduce TAT (turnaround time; the time from specifying program data to product delivery) in a manufacturing method for a semiconductor memory device having an MIS type transistor with a drain) structure. The present invention relates to a manufacturing method.

[Summary of explanation]

The present invention includes a memory cell section configured with a series-connected MIS type transistor array, and a peripheral circuit section having an MIS type transistor in which at least a motrain region includes a low concentration impurity region and a high concentration impurity region. In a method for manufacturing a semiconductor memory device, a gate electrode covered with a first insulating film and having low concentration impurity regions formed in source and drain regions is formed on a semiconductor substrate, and a second insulating film is formed on side walls of the gate electrode. After forming the film, at least selectively remove the second insulating film on a side of a predetermined gate electrode of the gate electrode in the memory cell portion, and then remove the second insulating film. By introducing impurities into the semiconductor substrate below the gate electrode, many parts can be formed before the program is determined, making it possible to obtain a semiconductor memory device with a significantly shortened TAT. .

[Conventional technology]

Conventionally, mask ROM (Mask ROM is ROM (Re) where data is written during the wafer process.
The NOR type, which uses a contact hole programming method, has been the mainstream (ad only memory), but as the degree of integration improves, the NAND type, which uses ion implantation programming, is becoming mainstream. In addition, there is a tendency to adopt transistors with an LDD structure as the integration becomes higher, and by adopting an LDD structure, it is possible to prevent hot electrons from being injected into the gate insulating film due to the high electric field near the drain and deteriorating the transistor characteristics. Can be done. The mask ROM programming technique is described in the Ultra High Speed Digital Device Series "2 Ultra High Speed MDS Devices" (Baifukan), supervised by Takuo Kanno and edited by Susumu Koyama.

A method for manufacturing a semiconductor memory device having an LDD structure transistor will be specifically described below with reference to the drawings.

As a semiconductor memory device, it can be applied to a read-only memory.

FIGS. 4A to 4C are diagrams for explaining an example of a conventional method for manufacturing a semiconductor memory device.

In this figure, 1 is a semiconductor substrate made of Si, for example;
2 is an element isolation insulating film made of, for example, SiO□, 3 is a gate insulating film made of, for example, SiO□, 4 is a resist, 5 is a data writing area, 6 is a gate electrode made of, for example, poly-Si, and 7 is a low concentration impurity region. , 8 is, for example, SiO2
9 is a high concentration impurity region; 10 is an interlayer insulating film made of, for example, SiO□ (PSG may also be used); 11
is a wiring layer made of At, for example.

Note that the source and drain regions are composed of a low concentration impurity region 7 and a high concentration impurity region 9.

Next, the manufacturing process will be explained.

First, as shown in FIG. 4(a), an element isolation insulating film 2 is formed on a semiconductor substrate by thermal oxidation and photoetching, and then a gate insulating film 3 is formed by thermal oxidation. Next, by ion implantation, impurities (
For example, p") is introduced to write data. At this time, a data write region 5 is formed, and the region where the impurity is implanted becomes a depletion transistor.

Next, as shown in the 41st peak), after removing the resist 4, poly-Si is deposited by, for example, CVD, and unnecessary portions of the poly-Si are selectively etched to form the gate electrode 6. Next, an impurity (for example, Pa) is introduced by ion implantation using the gate electrode 6 as a mask to form a low concentration impurity region 7, and after depositing SiO□ on the entire surface by, for example, CVD, unnecessary portions of SiO□ are removed by, for example, RIE. An insulating film 8 is formed on the wall portion of the gate electrode by selectively etching.

Next, an impurity (for example, As'') is introduced by ion implantation using the insulating film 8 as a mask to form a high concentration impurity region 9.

After depositing SiO□ by, for example, CVD, selectively etching unnecessary portions of Sing by, for example, RIE to form the glabellar insulating film 10, the wiring layer 11 is brought into contact with the high concentration impurity M349. By forming this, a semiconductor memory device as shown in FIG. 4(e) is completed.

[Problem that the invention seeks to solve]

In the semiconductor memory device obtained by the conventional manufacturing method described above, data of 0" and "l" are generally written by changing the threshold voltage of the transistor, but the process requires gate insulation. After forming the film 3 and writing data by ion implantation using a resist mask process to form the data writing region 5, the gate electrode 6, source, drain region, etc. are formed, so that the programming is easy. Since the data write area 5 cannot be formed until the data write area 5 is determined, and each area must be formed after writing, there is a drawback that the TAT becomes very long.

[Purpose of the invention]

The present invention was made to solve such problems, and an object of the present invention is to provide a method for manufacturing a semiconductor memory device that can write data after forming the source and drain regions, and can significantly shorten the TAT. shall be.

[Means for solving problems]

A method for manufacturing a semiconductor memory device according to the present invention includes the steps of forming a gate electrode covered with a first insulating film on a semiconductor substrate and having low concentration impurity regions formed in source and drain regions; a step of forming a second insulating film on the gate electrode of the memory cell portion, a step of selectively removing at least a second insulating film on a side of a predetermined gate electrode, and a step of removing the second insulating film. This method includes a step of introducing impurities into the semiconductor substrate under the gate electrode.

The configuration of the present invention will be described below using an embodiment of the present invention which will be described in detail later.

That is, the method for manufacturing a semiconductor memory device of the present invention is as shown in FIG.
As illustrated in a) to (e), the first
To form a gate electrode 6 covered with an insulating film 8a and having a source and drain region 12 and a low concentration impurity region 7 formed thereon, as shown in FIG. 1(al) and FIG. After forming the second insulating film 8b, as shown in FIG.
), of the gate electrode 6 in the memory cell section, the second insulating film 8b on the side of a predetermined gate electrode 6 is at least selectively removed, and as shown in FIG.
Semiconductor substrate 1 under gate electrode 6 with insulating film 8b removed
In this method, an impurity (As'' in the example) is introduced.

In the present invention, the step of forming a gate electrode covered with a first insulating film on a semiconductor substrate and having low concentration impurity regions formed in the source and drain regions means
One embodiment involves introducing impurities to form low concentration impurity regions in the source and drain regions before covering the gate electrode with the first insulating film, and then covering the gate electrode with the first insulating film. After covering with an insulating film, impurities are introduced to create a source.

The present invention includes an embodiment in which a low concentration impurity region is formed in the drain region.

Further, in the present invention, the step of selectively removing at least the second insulating film on the side of a predetermined gate electrode of the gate electrode of the memory cell section means The step may be any step in which at least the second insulating film is removed, and the second insulating film on the side of the gate electrode in the memory cell portion may be entirely removed.

[Effect]

In the present invention, data writing is performed by punching through the source and drain regions connected under the gate electrode by, for example, thermal diffusion of the impurity region for bunch-through, so that the TAT can be significantly shortened.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

Note that, as a matter of course, the present invention is not limited to the embodiments described below.

1(a) to +8) are diagrams for explaining an embodiment of the method for manufacturing a semiconductor memory device of the present invention. As a semiconductor memory device, it can be applied to a read-only memory.

In this figure, the same reference numerals as in FIGS. 4(3) to 4(C) indicate the same or corresponding parts, and 8a is a first insulating film made of, for example, SiJ, which has different etching characteristics from the gate insulating film 3. 8b is a second insulating film made of, for example, SiO□, and 21 is an impurity region for punch-through of the source and drain regions.

The memory cell section is composed of two series-connected MIS type transistor arrays on the left side as shown in Figure 1(e), and the peripheral circuit section is as shown on the right side of the drawing (Figure 1(e)). A MIS type transistor is provided, the source and drain regions of which are sandwiched between wiring layers 11 and each of which includes a low concentration impurity region 7 and a high concentration impurity region 9.

Next, the manufacturing process will be explained.

First, as shown in FIG. 1(a), an element isolation insulator Jiff2 is formed on a semiconductor substrate l by thermal oxidation and photoetching.
After forming the gate electrode 6, a gate insulating film 3 is formed by thermal oxidation. Next, for example, poly-Si is deposited, and unnecessary parts of the poly-Si are selectively etched to form the gate electrode 6. Then, for example, Si3N is deposited by CVD. , to a film thickness of 30
A first insulating film 8a of approximately 0 A is formed. Next, impurities (for example, p) are added to the source and drain regions by ion implantation.
”) to form a resistive concentration region 7. This is covered with a first insulating film on the semiconductor substrate of the present invention, and a gate electrode is formed in which a low concentration impurity region is formed in the source and drain regions. Applies to.

Next, as shown in FIG. 1 (bl), a second insulating film 8b is formed on the side wall portion of the gate electrode 6 by depositing SiO□ over the entire surface by, for example, CVD, and etching back the entire surface by, for example, RIE. This corresponds to the step of forming the second insulating film on the side wall portion of the gate electrode of the present invention.
Impurities (for example, As'') are introduced by ion implantation using the second insulating film 8b as a mask to form high concentration impurity regions 9.

Next, as shown in FIG. 1C, the peripheral circuit portion is covered with a resist using a photoresist process, and the second layer on the side of the gate electrode 6 of the memory cell portion is etched using the resist as a mask using, for example, wet etching. Insulating film 8b is selectively removed. This corresponds to the step of selectively removing the second insulating film on the side of the gate electrode of the present invention.

Next, as shown in FIG. 1(d), after applying a resist 4, a transistor part (a transistor part from which the second insulating film 8b is removed, for example, a depression MOS) where the source and drain regions are to be bunched through is applied. The resist 4 is patterned using a mask (not shown) that opens only the run lister, and an impurity (for example, p'') is introduced by ion implantation using the resist 4 as a mask to form an impurity region 21 for punch-through. time, the dose is I
It is about IO "elm-".

Then, by diffusion by heat treatment (particularly the impurity region 21 for punch-through), the source and drain regions are connected under the gate electrode 6 and bunch-through occurs. This corresponds to the step of introducing impurities into the semiconductor substrate under the gate electrode of the present invention. Next, Sing is deposited by, for example, CVD, and unnecessary portions of Sing are selectively etched by, for example, RIH to form interlayer insulating film 10, and then wiring layer 11 is formed to make contact with high concentration impurity region 19. By doing so, a semiconductor memory device as shown in FIG. 1(e) is completed.

That is, in the above embodiment, data writing is performed by thermally diffusing the impurity region 21 for punch-through to connect the source and drain regions under the gate electrode 6 and performing bunch-through, so that the TAT can be significantly shortened. Can be done.

Note that in the above embodiment, the gate electrode 6 is connected to the first insulating film 8.
After covering with a, impurities are introduced to make the sauce.

Although a case has been described in which the low concentration impurity region 7 is formed in the drain region, the present invention is not limited to this. It may also be the case where impurity region 7 is formed.

Further, in the above embodiment, after removing the second insulating film 8b of all the transistors in the memory cell part in the salt shown in FIG. 1(C), impurities are introduced and punched as shown in FIG. 1(d). Although we have described the case where the impurity region 21 for through is formed, the invention is not limited to this, and as shown in FIG. After removing the film 8b, the second
As shown in Figure (b), an impurity region 21 for punch-through may be formed by introducing impurities. In this case as well, as shown in FIG. 2(C), similar to the above embodiment explained in FIG.
As shown in FIG. 2, the source and drain regions can be bunched through under the gate electrode 6.

In addition, in the above embodiment, as shown in FIG. 1(b), the second
A case will be described in which a high concentration impurity region 9 is formed using the insulating film 8b as a mask, and impurity regions 21 for punch-through are formed in the source and drain regions of a transistor to be punch-through, as shown in FIG. 1 (dl). However, the present invention is not limited to this, and as shown in FIG. 3(a), a transistor in which it is desired to perform bunch-through in the memory cell portion without forming the high concentration impurity region 9 shown in FIG. 1(b) may be used. After removing the second insulating film 8b, as shown in FIG. 3(b), impurities (for example, As'') are introduced into the entire surface to form the high concentration impurity region 9 and the bunch-through impurity region 21 at the same time. In this case as well, if the gate length is set appropriately short and the implantation conditions are set appropriately, the source and drain regions can be punched through under the gate electrode 6, as shown in FIG. 3(C). Can be done.

〔Effect of the invention〕

As described above, according to the present invention, data reading can be performed after forming the source and drain regions, and the TAT can be significantly shortened.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining one embodiment of the method of manufacturing a semiconductor memory device of the present invention, and FIGS. 2 and 3 are diagrams for explaining other embodiments of the method of manufacturing a semiconductor memory device of the present invention. and FIG. 4 are diagrams for explaining other embodiments of the conventional semiconductor memory device. 1...Semiconductor base, 6...Gate electrode, 7...Low concentration impurity region, 8a...
First insulating film, 8b... Second insulating film, 9...
...High concentration impurity region.

Claims (1)

[Claims] 1. A memory cell section composed of a series-connected MIS type transistor array, and a peripheral circuit section having an MIS type transistor whose drain region is composed of a low concentration impurity region and a high concentration impurity region. A method of manufacturing a semiconductor memory device comprising: forming a gate electrode covered with a first insulating film on a semiconductor substrate and having low concentration impurity regions formed in source and drain regions; a step of forming a second insulating film; a step of selectively removing at least a portion of the second insulating film on a side of a predetermined gate electrode of the gate electrode of the memory cell portion; A method for manufacturing a semiconductor memory device, comprising the step of introducing an impurity into the semiconductor substrate below the gate electrode from which the insulating film has been removed.