JP2870131B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a MOS semiconductor device, and more particularly to a method of manufacturing a mask ROM that stores “0” and “1” by ion implantation.

[Prior Art] A mask ROM using an ion implantation method is most commonly used for a large-capacity ROM, a one-chip microcomputer, and the like because of a very small cell size. In the method of manufacturing a mask ROM by this ion implantation method, an ion implantation step for performing I / T control of P-type and N-type enhancement transistors is performed before forming a gate electrode, and then an ion implantation step for a mask ROM portion is also performed. Had been. However, for a mask ROM product or a one-chip microcomputer, a very large number of products are ordered by changing the contents of the ROM. From the viewpoint of shortening the TAT, it is preferable to perform the process in the latter half of the process as much as possible. In recent years, after the formation of the gate electrode and the formation of the source / drain and before the formation of the interlayer insulating film, ion implantation into the ROM is performed to shorten the TAT. By the way, in order to implant ions below the gate electrode after forming the gate electrode, it is necessary to perform the ion implantation with a higher energy than in the past. Is taking.

With reference to FIG. 3, a method of manufacturing a mask ROM portion using divalent ions will be described. FIG. 3 (b) shows a cross section taken along line AA 'in FIG. 3 (a), and FIG. 3 (c) shows a cross section taken along line BB' in FIG. After the selective oxidation conventionally used, a gate oxide film 26 is formed on a P-type Si substrate 24, a gate electrode 22 is formed, and an N-type high concentration impurity layer 25 serving as a source / drain is formed. Are sequentially performed, and then a photoresist 30 is formed to form an N-type low-concentration impurity layer 28 of the mask ROM.
Is performed, and then ion implantation with divalent ions is performed. In the figure, 21 is an element region, and 23 is a ROM ion implantation pattern. Then, a mask ROM or a one-chip microcomputer with a built-in mask ROM is manufactured by a conventional method of manufacturing a MOS LSI by forming an interlayer insulating film, forming a contact opening, and forming an Al wiring.

[Problems to be solved by the invention]

This conventional divalent ion implantation method has the following problems.

First, it takes time to complete the device after ion implantation of ROM. In the prior art, after the ion implantation of the ROM, a contact opening step, a reflow step, and an aluminum wiring forming step are required. Each is subjected to high-concentration ion implantation. Also, as for aluminum wiring, products with two-layer wiring are increasing, and the number of photolithography processes is 6 to 7 processes, which is about the same as the time when ROM ion implantation was performed before forming gate electrodes. There's a problem.

Second, in the case of ROM ion implantation using divalent ions, the implantation is performed at higher energy.
In the ROM ion implantation, an N-type low-concentration impurity region 30 is formed in a region not ion-implanted, that is, below the field oxide film 29 shown in FIG. As a result, the spacing between adjacent elements needs to be increased with respect to the implantation of monovalent ions, and the unit cell size increases. Therefore, this is a very serious problem for increasing the capacity of the ROM.

An object of the present invention is to provide a mask ROM just before forming aluminum wiring.
It is an object of the present invention to provide a method of manufacturing a semiconductor device which solves the conventional problems by performing ion implantation of the above.

[Means for solving the problem]

In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes a photoresist forming step, an etching step, an ion implantation step, and a wiring step,
A method of manufacturing a mask ROM for storing “0” and “1” by ion implantation or a semiconductor device having a built-in mask ROM, wherein a photoresist forming step includes element isolation by selective oxidation, formation of a gate oxide film, and a gate electrode. After the formation of the high-concentration impurity layers of the source / drain, the formation of the interlayer insulating film, and the opening of the contact, the area other than the ROM area is selectively covered with a first photoresist, and the entire area is covered with a second photoresist. In the etching step, the ROM area is flattened by etch-back, and the interlayer insulating film is etched until the gate electrode is exposed. The ion implantation step is performed in the first photo-area other than the ROM area. The resist is removed, a thin insulating film is formed, and impurities are selectively implanted by ion implantation below the gate electrode of the desired transistor in the ROM area. Is intended to perform the heat treatment, the wiring process is to form the desired aluminum wiring, and is intended to form a passivation film.

Further, in the present invention, the interlayer insulating film is formed between gate electrodes.

[Action]

According to the present invention, the ion implantation of the mask ROM is performed immediately before the formation of the aluminum wiring, thereby making it possible to shorten the TAT. Further, by forming an interlayer insulating film between the gate electrodes, injection of impurities below the field oxide film is prevented.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1A is a plane pattern diagram showing one embodiment of the present invention, showing a state in which ion implantation of a mask ROM portion is performed. FIG. 1 (b) shows a cross section taken along the line AA 'in FIG. 1 (a), and FIG. 1 (c ()) shows a cross section taken along the line BB' in FIG. 1 (a). The major difference between the present invention and the conventional example is that ion implantation of a mask ROM is performed before aluminum wiring is formed and that an interlayer insulating film exists between polysilicon electrodes. Reference numeral 1 denotes an element region, 3 denotes a ROM ion implantation pattern, and 11 denotes a contact.

FIG. 2 is a sectional view showing the manufacturing method of the present invention, and FIG.
This corresponds to a cross section taken along line AA ′ of FIG. Second
As shown in FIG. 1A, after element isolation is performed on a P-type Si substrate 4 by forming a field oxide film 9 by conventional selective oxidation, a gate oxide film 6 is formed by, for example, a thermal oxidation method. The gate electrode 2 is formed by growing the polysilicon by LPCVD, for example, introducing impurities by thermal diffusion, and then patterning the polysilicon by, for example, photolithography and etching, and further forming the source and drain of the mask ROM section. Is formed using, for example, an ion implantation technique. Here, the gate electrode 2 is made of high melting point metal polycide or high melting point metal silicide.

Next, as shown in FIG. 2 (b), an interlayer insulating film 7 is formed between the gate electrodes 2, 2 by, for example, a CVD method and a heat treatment.
For example, a contact opening is made by a photolithography technique and an etching technique. Thereafter, ion implantation for improving the margin between the contact and the element region is performed, if necessary.

Next, as shown in FIG. 2C, a first photoresist 12 is applied, a photoresist is selectively formed in a region other than the ROM area, and a second photoresist for etching back is further formed.
13 is formed in the whole area.

Next, as shown in FIG. 2 (d), etching back is performed using the above-mentioned photoresist 13 as a sacrificial film to make it flat and to expose the gate electrode 2 in the ROM region. At this time, the normal transistor portion is protected by the first photoresist 12 and is not etched back. After this, the first
The photoresist 12 is removed.

Next, as shown in FIG. 1 (b), after a thin insulating film is formed, patterning of the photoresist 10 is performed by, for example, a photolithography technique to perform ion implantation into a mask ROM portion. By heat treatment, an N-type low concentration impurity layer 8 is formed below the gate electrode 2 in a desired transistor portion.

Finally, as shown in FIG. 2 (e), by forming an aluminum wiring 14 and forming a passivation film 15, a mask ROM portion and a normal transistor are respectively formed.

Further, in the present invention, an N-type transistor on a P-type Si substrate has been described. However, it is apparent that exactly the same effect can be obtained for a P-type transistor on an N-type Si substrate.

〔The invention's effect〕

As described above, the present invention makes it possible to perform ion implantation of a mask ROM immediately before forming an aluminum wiring,
TAT can be reduced because it is performed in a later process than before. Further, at the time of performing the divalent ion implantation, as shown in FIG. 1C, since the interlayer insulating film is formed between the gate electrodes, the implantation of the impurity under the field oxide film is eliminated. The present invention has the effect of realizing the manufacture of a mask ROM and a one-chip microcomputer having a built-in mask ROM, which have the same unit cell area as the conventional one.

[Brief description of the drawings]

FIG. 1 (a) is a plane pattern diagram showing one embodiment of the present invention, FIG. 1 (b) is a sectional view taken along line AA 'of FIG. 1 (a),
FIG. 1C is a sectional view taken along the line BB ′ of FIG.
3 (a), 3 (b), 3 (c), 3 (d) and 3 (e) are cross-sectional views showing the manufacturing method of the present invention in the order of steps. FIG. 3 (a) is a plan view showing a conventional example. FIG. 3B is a sectional view taken along line AA ′ of FIG. 3A, and FIG. 3C is a sectional view taken along line B-A of FIG.
It is B 'line sectional drawing. DESCRIPTION OF SYMBOLS 1 ... Element area 2 ... Gate electrode 3 ... ROM ion implantation pattern 4 ... P type Si substrate 5 ... N type high concentration impurity layer 6 ... Gate oxide film, 7 ... Interlayer insulating film 8 ... N-type low concentration impurity layer 9 ... Field oxide film 10,12,13 ... Photoresist

Claims (2)

(57) [Claims] 1. A semiconductor device having a photoresist forming step, an etching step, an ion implantation step, and a wiring step, and incorporating a mask ROM or a mask ROM for storing “0” and “1” by ion implantation. The photoresist forming step includes element isolation by selective oxidation,
After forming a gate oxide film, forming a gate electrode, a high-concentration impurity layer of a source / drain, forming an interlayer insulating film, and performing a contact opening, a portion except for the ROM region is selectively covered with a first photoresist, and the whole is further covered. The area is covered with a second photoresist. The etching step is to flatten the ROM area by etch-back and to etch the interlayer insulating film until the gate electrode is exposed. The first photoresist other than the ROM region is removed, a thin insulating film is formed, and impurities are selectively introduced by ion implantation under a gate electrode of a desired transistor portion in the ROM region to perform heat treatment. The method of manufacturing a semiconductor device, wherein the wiring step forms a desired aluminum wiring and forms a passivation film. 2. The method according to claim 1, wherein said interlayer insulating film is formed between gate electrodes.