JP3037100B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a process for the manufacture of semiconductor equipment.

[0002]

2. Description of the Related Art The structure of a conventional MOS transistor having both a P-type gate electrode and an N-type gate electrode and a method of manufacturing the same will be described with reference to Japanese Patent Application Laid-Open No. 3-203366.
As shown in FIG. 5, an N-channel MOS transistor composed of an n-type polysilicon electrode 8 and an n-type diffusion layer 6 and a P-channel MOS transistor composed of a P-type diffusion layer 7 are provided. The type polysilicon electrode 8 and the P type polysilicon electrode 9 are connected to an aluminum wiring 13 via a contact 12.

As shown in FIG. 6, a P-well 2, an N-well 3, and a LOCOS oxide film 4 for element isolation are provided on a semiconductor substrate 1. A gate oxide film 5 is provided, and a polycide gate electrode composed of an N-type polysilicon electrode 8 and Ti silicide 10 is provided in a region of the gate oxide film 5 for an N-channel MOS transistor. In this embodiment, a polycide gate electrode composed of a P-type polysilicide electrode 9 and Ti silicide 10 is provided.
The N-type polysilicon electrode 8 and the P-type polysilicon electrode 9 are connected at the upper part of the LOCOS oxide film 4.
Numerals 0 are separated at the upper part of the LOCOS oxide film 4. This is because, when the Ti silicide 10 on the N-channel MOS transistor is connected to the Ti silicide 10 on the P-channel MOS transistor, arsenic in the N-type polysilicon electrode 8 or boron or the like in the P-type polysilicon electrode 9 is heat-treated in a later step. Is to prevent the N-type polysilicide electrode 8 from being diffused in the Ti silicide 10 and the P-type polysilicide electrode 9 from being N-type, thereby preventing the transistor characteristics from changing. The connection between the gate electrode and the aluminum wiring 13 is performed via the contact 12.

Next, a conventional manufacturing method will be described with reference to FIG. As shown in FIG. 7A, a P well 2, an N well 3, and a LOCOS oxide film 4 for element isolation are formed on a semiconductor substrate 1. Next, after forming the gate oxide film 5, the polysilicon electrode is patterned, and an N-type polysilicon electrode 8 and a P-type polysilicon electrode 9 are formed by ion implantation at the time of forming the source and drain.

[0007] Next, as shown in FIG. 7 (b), an oxide film 13 is formed on the P-type polysilicon electrode 9 and the N-type polysilicon electrode 8, and thereafter, only in the region of the connection portion between the polysilicon electrodes 8, 9. Patterning is performed so that oxide film 13 remains.

Next, as shown in FIG. 7C, a Ti silicide 10 is formed on the P-type polysilicon electrode 9 and the N-type polysilicon electrode 8 by sputtering and annealing of Ti. At this time, Ti on oxide film 13 is not silicided.
Next, Ti on oxide film 13 is removed.

[0007] Finally, as shown in FIG.
3 is removed, an interlayer film 11 is formed, and a contact hole 1 is formed.
2a is opened and the contact 12 is inserted into the contact hole 12a.
And the aluminum wiring 13 is laminated on the contact 12 and the aluminum wiring 13 is patterned to complete the semiconductor device.

[0008]

In the prior art described above, the N-type polysilicon electrode 8 forming the gate electrode of the N-channel MOS transistor and the P-type polysilicon electrode 9 forming the gate electrode of the P-channel MOS transistor are separately provided. The resistance of each of the polysilicon electrodes 8 and 9 is controlled by ion implantation. However, since the N-type polysilicon electrode 8 and the P-type polysilicon electrode 9 are formed in series, When separate impurities are implanted, the boundaries of the impurities cannot be specified, and thus it is impossible to give each transistor the characteristics as designed.

Furthermore, impurities other than the necessary impurities may be mixed in the boundary regions of the impurities on the polysilicon electrodes 8 and 9, and the mutual diffusion of the impurities between the polysilicon electrodes 8 and 9 is completely prevented. However, there is a problem that the characteristics of the transistor are deteriorated.

Further, it is necessary to use a photolithography technique for separating the Ti silicide 10 of the gate electrode, and there is a problem that the manufacturing process becomes complicated.

An object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which completely prevent the mutual diffusion of impurities and simplify the manufacturing process.

[0012]

In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention comprises the steps of:
Forming an element isolation oxide film, conductivity type in the isolation acid <br/> of film is mutually different gate electrode across a gap
And forming a pair so as to face each other.
Of the opposite end face of the
A step of covering the oxide film for element isolation with a film for an etching stopper, a step of forming an interlayer insulating film made of an oxide film on a semiconductor substrate, and using the film for the etching stopper as a stopper , Part of the gate electrode
Forming an opening by etching the interlayer insulating film in a region including the opening, and thereafter, etching the etching stopper film; and filling the opening with a conductor.

[0013]

[0014]

[0015]

[0016]

[0017]

The gate electrodes having different conductivity types are physically separated from each other. Therefore, the boundary of the impurity to be implanted into the gate electrode can be specified, and it is possible to prevent impurities other than the necessary impurity from being mixed into the counterpart gate electrode, thereby completely preventing mutual diffusion of impurities. As a result, deterioration of transistor characteristics can be prevented.

[0018]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

( Reference Example ) FIG. 1 is a plan view showing a semiconductor device according to a reference example of the present invention, and FIG. 2 is a sectional view taken along line AA 'of FIG.

In the figure, a semiconductor device according to the present invention has a pair of transistors and a contact as a basic configuration, and the pair of transistors is provided adjacently on the same substrate 1. , and the gate electrode G ₁ and G ₂ of the transistor in the pair is different conductivity type to each other, which is provided with relatively separated, the contact 12 is different from the gate electrode G ₁ conductivity type, it is intended to electrically connect the G _2.

Further, the gate electrodes G ₁ and G ₂ have a two-layer structure of ion-implanted polycrystalline silicon films 8 and 9 and a refractory metal silicide film 10, and a contact hole 12a is provided between the gate electrodes. The contact 12 is filled in the contact hole 12a.

Next, the semiconductor device of the present invention will be described with reference to FIG. 1 using a specific example in which an N-channel MOS transistor and a P-channel transistor are used as a pair of transistors.
A description will be given based on FIG. As shown in the figure, a P well 2 and an N well 3 are provided adjacent to each other on a semiconductor substrate 1, and a locos oxide film 4 for element isolation is provided at a boundary between the P well 2 and the N well 3. An N-channel MOS transistor is formed in a region of n-type diffusion layer 6 separated by oxide film 4, and a P-channel MOS transistor is formed in a region of p-type diffusion layer 7.

On the P well in the region of the n-type diffusion layer 6 and on the N well 3 in the region of the p-type diffusion layer 7, a gate electrode film 5 is provided with a locos oxide film 4 interposed therebetween. and the gate electrode G ₂ of the gate electrode G ₁ and the P-channel MOS transistor of the N-channel MOS transistor is formed on the film 5. In the present invention, the gate electrode G ₁ and the gate electrode G ₂ is provided physically separate.

The gate electrode G ₁ of the N-channel MOS transistor is an N-type polysilicon electrode (polycrystalline silicon film)
8, Ti silicide (high melting point metal silicide film) 10
The gate electrode G ₂ of the P-channel MOS transistor has a two-layer structure of a P-type polysilicon electrode (polycrystalline silicon film) 9 and a Ti silicide (refractory metal silicide film) 10. ing. Arsenic as an impurity is ion-implanted into the N-type polysilicon electrode 8, and boron as an impurity is ion-implanted into the P-type polysilicon electrode 9. According to the present invention, the interlayer film 11 is formed over the physically separated gate electrode G ₁ and the gate electrode G _2, and the physically separated gate electric electrode G 1 is formed.
Contact holes 12a are provided through the interlayer film 11 toward the gap S between the ₁ and the gate electrode G _2, the contact hole 12
a is filled with a contact (conductor) 12, and the gate electrode G ₁ and the gate electrode G ₂ which are physically separated are electrically connected via the contact 12.

Next, a method of manufacturing a semiconductor device according to the present invention will be described. The manufacturing method of the present invention has, as a basic configuration, a gate electrode forming step, an opening step, and a contact forming step. Specific examples of each step will be described with reference to FIG.

As shown in FIG. 3A, a P-well 2 and an N-well 3 are provided adjacent to each other on a semiconductor substrate 1, and a LOCOS oxide for element isolation is provided in a boundary region between the P-well 2 and the N-well 3. The film 4 is formed at 5000 °. Next, after a gate oxide film 5 is formed on the P well 2 and the N well 3, a polycrystalline silicon film is grown on the gate oxide film 5 by 1500 °, and this polycrystalline silicon film is formed into gate electrodes G ₁ and G ₂ . Perform patterning. When patterning the polycrystalline silicon film into the shapes of the gate electrodes G ₁ and G ₂ , the polycrystalline silicon film is formed with a gap S between the polycrystalline silicon films.

Next, an impurity such as arsenic is ion-implanted into the polycrystalline silicon film patterned in the shape of the gate electrode G ₁ of the N-channel MOS transistor to form an N-type polysilicon electrode 8. On the other hand by the impurities e.g., boron fluoride into the polycrystalline silicon film is patterned into the shape of the gate electrode G ₂ of the P-channel MOS transistor by ion implantation and heat treatment to form a P-type polysilicon electrode 9. In this case, although not shown, the collector electrode and the source electrode of the N-channel MOS transistor and the P-channel MOS transistor are formed in the same manner as the gate electrode.

Next, as shown in FIG. 3B, an oxide film is formed on the N-type polysilicon electrode 8 and the P-type polysilicon electrode 9 by 500.
After the growth, anisotropic etching is performed to form sidewalls 14 on the separated end faces of the N-type polysilicon electrode 8 and the P-type polysilicon electrode 9, and to form the N-type polysilicon electrode 8.
Then, the oxide film on the P-type polysilicon electrode 9 is removed.

Next, a high melting point metal such as Ti is sputtered on the N-type polysilicon electrode 8 and the P-type polysilicon electrode 9 at 300 ° and annealed at 600 to 800 ° C. to perform the N-type polysilicon electrode 8 and the P-type polysilicon electrode 9. A Ti silicide (refractory metal silicide film) 10 is formed thereon. In the above steps, the gate electrode G ₁ of the N-channel MOS transistor including the Ti silicide 10 and the N-type polysilicide electrode 8, the Ti silicide 10 and the P-type polysilicide electrode 9
The gate electrode forming step of forming physically separates the gate electrode G ₂ of the P-channel MOS transistor consisting of the ends.

Next, as shown in FIG. 3C, an oxide film is formed on the Ti silicide
Grow 0 °. Next, a photoresist is applied on the interlayer film 11, and the photoresist is patterned by a photolithography technique to form a gate electrode G physically separated.
_1, a mask having a suitable shape to form a contact hole 12 reaching the gap S between the G ₂ is formed by the photoresist.

Next, contact holes 12a are formed in the interlayer film 11 by anisotropic etching using the photoresist as a mask.
To form In this case, since it is necessary to provide a contact hole reaching the collector electrode and the source electrode of the N-channel MOS transistor and the P-channel MOS transistor in the interlayer film 11, the interlayer film 11 is etched about 11000 ° by anisotropic etching. In this case, the contact hole 12 is etched to a position where the contact hole 12 has penetrated a part of the LOCOS oxide film 4. In the above steps, the gate electrode G
_1, the step of opening the contact hole 12 between the G ₂ is completed.

Next, as shown in FIG. 3B, after a barrier metal such as titanium or titanium nitride is sputtered in the contact hole 12 of the interlayer film 11, a contact is formed in the contact hole 12a by using a technique such as tungsten growth. (conductor)
The gate electrodes G ₁ and G ₂ are electrically connected by the contact 12. After that, aluminum is vapor-deposited on the interlayer film 11, the aluminum is patterned, and an aluminum wiring 13 connected to the contact 12 is formed. In the above process, the contact hole 12 between the gate electrodes G ₁ and G _{2 is formed.}
a is filled with the contact 12, and the contact forming step of electrically connecting the gate electrodes G ₁ and G ₂ by the contact 12 is completed.

[0033] (Embodiment) FIG. 4 is a sectional view showing an embodiment of the present invention in order of steps.

In the opening step of the reference example, the contact hole 12 was opened by etching in a state where the opposing end faces of the separated gate electrodes G1 and G2 were covered with the sidewalls 14. Is a method in which a contact hole is opened by an etching process in a state where the opposing end faces of the separated gate electrodes G1 and G2 and the oxide film for element isolation under the gate electrode are covered with a film for an etching stopper.

[0035] That is Ti on polysilicon electrode in the embodiment
Until the step of forming the silicide 10 (FIG. 3B),
This is the same as in the above-described reference example , and thereafter, for example, a nitride film 15 is grown on the entire surface of the semiconductor substrate by 1000 ° as an etching stopper film at the time of contact opening (FIG. 4A).

Next, for example, an oxide film is grown on the entire surface of the semiconductor substrate 1, and an interlayer film 11 is formed at 10,000. Next, a resist for forming a contact on the upper part of the N-type polysilicon electrode 8 and the P-type polysilicon electrode 9 is patterned by photolithography, and then the interlayer film 11 is etched by about 11000 ° by anisotropic etching. At this time, since the nitride film 15 functions as an etching stopper, the LOCOS oxide film 4 is not etched as in the aforementioned reference example. Then the nitride film 15 is etched, after a contact hole 12a, after sputtering a barrier metal such as titanium or titanium nitride in the contact holes 12 a of the reference example as well as the interlayer film 11 of the foregoing, tungsten growth such as A contact (conductor) 12 is filled in the contact hole 12a by using the technique described above, and the contact 12 electrically connects the gate electrodes G1 and G2. Thereafter, aluminum is vapor-deposited on the interlayer film 11, and the aluminum is patterned to form an aluminum wiring 13 connected to the contact 12 (FIG. 4B).

[0037]

As described above, according to the present invention, separate ions are implanted into the gate electrodes of a pair of transistors, and the gate electrodes are formed separately for controlling the resistance. When different impurities are ion-implanted, a boundary between the impurities can be specified, and thus each transistor can have characteristics as designed.

Further, the boundary region of the impurities on the gate electrode is separated, so that impurities other than the necessary impurities are not mixed in, and the mutual diffusion of impurities between the gate electrodes is completely prevented. And deterioration of the characteristics of the transistor can be prevented. Further, since the gate electrodes are connected via the contacts after the ion implantation, it is possible to prevent the characteristics of the transistor from being affected.

Further, in order to prevent mutual diffusion due to ion implantation into the gate electrodes, a method is provided in which the gate electrodes are spaced apart from each other and the gate electrodes are electrically connected via contacts. Compared with the prior art in which only the polysilicon electrode of the gate electrode is connected and the refractory metal silicide layer on the polysilicon electrode is spaced apart, the photolithography technique is not required once in the present invention, and the number of steps is small. In comparison, about 7 steps can be reduced.

Further, in a state where the opposing end faces of the separated gate electrode are covered with the sidewalls, the contact holes can be opened by the etching process, so that the manufacturing process can be simplified. Alternatively, instead of the above method, a contact hole is opened by etching in a state where the opposite end face of the separated gate electrode and the element isolation oxide film below the gate electrode are covered with an etching stopper film. The element isolation oxide film below the electrode is not etched, and the element isolation oxide film is not affected.

[Brief description of the drawings]

FIG. 1 is a plan view illustrating a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view taken along line AA ′ of FIG.

FIG. 3 is a sectional view illustrating a manufacturing method according to the first embodiment of the present invention in the order of steps.

FIG. 4 is a sectional view illustrating a manufacturing method according to a second embodiment of the present invention in the order of steps.

FIG. 5 is a plan view showing a conventional example.

FIG. 6 is a sectional view taken along line BB ′ of FIG. 5;

FIG. 7 is a sectional view showing a conventional example in the order of steps.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 P well 3 N well 4 Locos oxide film 5 Gate oxide film 6 N-type diffusion layer 7 P-type diffusion layer 8 N-type polysilicon electrode 9 P-type polysilicon electrode 10 Ti silicide 11 Interlayer film 12 Contact 12 Contact hole 13 Aluminum Wiring 14 Sidewall 15 Nitride film

Claims (1)

(57) [Claims] A step of forming an element isolation oxide film on a semiconductor substrate; and a step of forming a gate having a different conductivity type on the element isolation oxide film.
A step of electrodes are formed so as to face each other with a gap, the end faces及opposite the gate electrode facing separating said gap
Covering the element isolation oxide film below the gate electrode with a film for an etching stopper, forming an interlayer insulating film made of an oxide film on a semiconductor substrate, and using the film for the etching stopper as a stopper.
The layer in the region including the gap and part of the gate electrode on both sides thereof
A method for manufacturing a semiconductor device, comprising: a step of forming an opening by etching an inter- insulating film; and thereafter, a step of etching the film for the etching stopper; and a step of filling the opening with a conductor.